Double data rate quad-switching multi-bit digital-to-analog converter and continuous-time modulator

Abstract

The embodiments of the present disclosure relate to a double data rate quad switching multi-bit digital to analog converter and a continuous time modulator. N -1 bit thermometer coded signal generates four 2 N -1 bit control signal. The DAC circuit has 2 N -1 unit DAC element, each unit DAC element consists of four 2 N - Four switching circuits controlled by the corresponding bit of the 1-bit control signal. N -1 unit DAC element output summed to generate the analog output signal. The four-element signal generator circuit generates four 2 N -1-bit control signal controls relative to 2 N - The time delay of the 1-bit thermometer coded signal applied to the clock signal and the time delay relative to the delayed clock signal applied to the 2 N The analog output signal is the feedback signal in the sigma-delta analog-to-digital converter circuit, which includes a multi-bit quantization circuit that operates to quantize the filter loop signal to generate a 2 N - 1-bit thermometer coded signal.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to U.S. Provisional Application No. 63 / 054,317, filed on July 21, 2020, the disclosure of which is incorporated by reference. Technical Field

[0003] The present invention generally relates to a digital-to-analog converter (DAC) circuit, and more particularly to a multi-bit DAC circuit for use in a continuous-time (CT) sigma-delta (SD) modulator circuit. Background Art

[0004] Figure 1 A time-domain block diagram of a conventional continuous-time (CT) sigma-delta (SD) analog-to-digital converter (ADC) circuit 10 is shown. Circuit 10 includes a continuous-time sigma-delta modulator circuit 12 (illustrated here as a first-order circuit) having an input configured to receive an analog input signal A and an output configured to generate a digital output signal B. The first-order implementation of sigma-delta modulator circuit 12 includes a difference amplifier 20 (or accumulation circuit) having a first (non-inverting) input receiving the analog input signal A and a second (inverting) input receiving the analog feedback signal D. Difference amplifier 20 outputs an analog difference signal vdif (i.e., vdif(t) = A(t) - D(t)) in response to the difference between the analog input signal A and the analog feedback signal D. The analog difference signal vdif is integrated by an integrator circuit 22 (a first-order loop filter) to generate a variation signal vc, the slope and amplitude of which depend on the sign and amplitude of the analog difference signal vdif. The quantization circuit 24 samples the variation signal vc at a sampling rate fs set by the sampling clock CLK, and the quantization circuit 24 generates a digital output signal B as a 2 for each sample. N - 1-bit thermometer coded output word (where N is an integer N>1, for example N=4). The circuit 10 also includes a decimator circuit 14 for decimating 2 of the stream of digital output signal B. N The 1-bit thermometer code word is low-pass filtered and downsampled to generate a digital signal C consisting of a stream of multi-bit (M bits, i.e., the desired resolution, where M is an integer M>>N) digital words generated at the output word rate fd set by the decimation factor.

[0005] The multi-bit digital-to-analog converter (DAC) circuit 26 in the feedback loop converts the digital output signal B to a corresponding analog signal level for the analog feedback signal D. The DAC circuit 26 is a resistor circuit that includes 2 N- 1 unit resistor DAC element (UE), which is composed of 2 parts of the thermometer code word of the digital output signal B. N - 1-bit drive, where the current outputs from the driven unit resistance DAC elements are summed at the DAC circuit output to generate an analog signal level of the analog feedback signal D.

[0006] The use of multi-bit quantization presents a number of advantages, including: allowing the modulator to be operated using a lower sampling rate fs to achieve a given resolution; or allowing the modulator to be operated to achieve a higher resolution for a given sampling rate fs. A key characteristic of the sigma-delta modulator circuit 12 is its ability to push the quantization noise generated by the operation of the quantization circuit 24 to higher frequencies away from the signal of interest. This is known in the art as noise shaping. The decimator circuit 14 can then be implemented with a low-pass filtering characteristic (i.e., frequency response) to substantially remove the high-frequency components of the shaped quantization noise.

[0007] However, due to the 2 of the DAC circuit 26 in the feedback loop N The inherent mismatch in the 1-bit resistor DAC element makes the use of multi-bit quantization in the sigma-delta modulator circuit difficult. As known to those skilled in the art, this DAC mismatch directly translates into nonlinearity in the entire modulator 12. This nonlinearity is due to, for example, the unequal analog signal output steps of the multi-bit DAC circuit (i.e., due to the 2 N -1 unit resistance mismatch between DAC elements).

[0008] As a result of the nonlinearity introduced into the analog output of DAC circuit 26 due to the mismatch between the unit resistance DAC elements, the noise floor is increased and harmonic distortion is increased within the desired signal frequency band compared to the modulator output spectrum. DAC nonlinearity also modulates the quantization noise of quantization circuit 24 into the signal frequency band, resulting in degradation of the signal-to-noise ratio (SNR) and signal-to-noise and distortion ratio (SNDR).

[0009] Now refer to Figure 2 It is known in the art to solve the problem of DAC nonlinearity in multi-bit quantization implementations by employing circuit 30 in the feedback loop, which implements a data weighted averaging (DWA) algorithm to achieve a 2-bit DAC nonlinearity. N -1 unit resistance DAC element first order mismatch shaping. Circuit 30 receives a series of 2 outputs from quantization circuit 24. N -1 bit thermometer code word and generates a series of 2 N - 1-bit control word to activate 2 bits of DAC circuit 26 N -1 unit resistor DAC element, so that over time, all 2 NThe 1-unit resistance DAC elements will all be actuated relatively equally when generating the analog feedback signal D.

[0010] In addition to the quantization delay, the execution of the DWA algorithm also introduces processing delay into the signal processing loop. It is important that the total delay, known as excess loop delay (ELD), does not exceed one period Ts of the sampling clock CLK, as this could lead to modulator instability. More specifically, the ELD preferably satisfies the following constraint: 0.5Ts < ELD < 0.75Ts.

[0011] DWA modifies the switching of the DAC elements so that the DAC elements switch at every clock cycle. Therefore, the switching in the DAC is not temperature-dependent. As a result, nonlinear glitch energy as well as data-dependent switching (in response to DWA) can introduce significant distortion into the output of the modulator. A solution to this problem is to perform quad switching of the DAC. One option is to use half data rate (HDR) quad switching. However, the purpose of DWA to eliminate the effects of mismatch in the DAC elements by first-order mismatch shaping is not fully utilized in HDR quad switching. Due to the mismatch, some residual distortion remains in the modulator output. It is worth noting that this residual distortion arises due to the unequal number of times the resistors of the DAC switching circuit are selected by HDR quad switching. The selection of resistors by the switching transistors depends on the data pattern, which is reflected in the Figure 6B This can be clearly seen in the timing diagram shown in .

[0012] The quaternary switching signal generation circuit can introduce small glitches into the control signal, resulting in severe harmonic distortion of the modulator output. Prior art solutions address this issue by latching the control signal. However, the signal latching operation will also increase latency and risk unacceptable ELD levels, leading to instability. In this regard, it is worth noting that the continuous-time delta-sigma modulator operating in the GHz sampling frequency (fs) range presented herein includes a feedback path having a quantizer, a DWA, a quaternary signal generator, and a DAC. In this configuration, it is difficult to guarantee ELD in the feedback path, where 0.5Ts < ELD < 0.75Ts (where Ts = 1 / fs), but adding a latch circuit to the quaternary switching signal will also add signal delay and jeopardize the ability to meet ELD performance requirements.

[0013] Therefore, there is a need in the art to solve the above problems. Summary of the Invention

[0014] The present invention utilizes double data rate (DDR) quad switching of the DAC. The generation of the quad switching signal is controlled to ensure that the excess loop delay (ELD) requirement is met and also to ensure that no glitches occur.

[0015] In an embodiment, the circuit includes: a digital-to-analog converter (DAC) circuit having 2 N -1 unit resistor DAC element, each of which consists of four 2 N -1 bit control signal corresponding to the four switching circuits controlled, of which 2 N - the outputs of the 1 unit resistor DAC elements are summed to generate an analog output signal; and a quaternary signal generator circuit configured to respond to 2 N -1-bit thermometer coded input signal generates four 2 N -1-bit control signal.

[0016] In an embodiment, a quad signal generator circuit includes a clock phase circuit configured to generate a first clock signal and a second clock signal, the clock signals being 180° out of phase with each other, and the clock phase circuit configured to apply a first delay to set clock edges of the first clock signal and the second clock signal to track the 2 N - 1-bit thermometer coded input signal logic switching; the first circuit is configured to convert 2 N -1-bit thermometer coded input signal is logically combined with the first clock signal to generate four 2 N - The first 2 in the 1-bit control signal N -1-bit control signal; the second circuit is configured to convert 2 N The delay of the 1-bit thermometer coded input signal is logically combined with the second clock signal to generate four 2 N - The second 2 in the 1-bit control signal N -1-bit control signal, where the second circuit applies a second delay to set the delay of 2 N - logic switching of a 1-bit thermometer coded input signal to track the clock edges of the first clock signal and the second clock signal; a third circuit configured to convert the 2 N - The logical inversion of the 1-bit thermometer coded input signal is logically combined with the first clock signal to generate four 2 N - The third 2 in the 1-bit control signal N -1 bit control signal; and a fourth circuit configured to convert 2 N - The delayed, logically inverted 1-bit thermometer coded input signal is logically combined with the second clock signal to generate four 2 N - The fourth 2 in the 1-bit control signal N -1-bit control signal, where the fourth circuit applies a third delay to set the 2 N - 1-bit thermometer coded input signal delayed logical inversion logic switching to track the clock edges of the first clock signal and the second clock signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] For a better understanding of the embodiments, reference will now be made, by way of example only, to the accompanying drawings, in which:

[0018] Figure 1 is a time domain block diagram of a conventional sigma-delta analog-to-digital converter circuit with multi-bit quantization;

[0019] Figure 2 It is a time domain block diagram of a conventional sigma-delta analog-to-digital converter circuit with multi-bit quantization and data weighted averaging;

[0020] Figure 3A It is a time domain block diagram of a continuous time sigma-delta analog-to-digital converter circuit with a multi-bit quantizer, a data weighted average, and a quaternary signal generator for controlling a quaternary switching digital-to-analog converter;

[0021] Figure 3B A third-order modulator is used Figure 3A A circuit diagram of a differential signal implementation method of a circuit;

[0022] Figure 4 is a block diagram of a digital-to-analog converter (DAC) circuit in the differential signaling form;

[0023] Figure 5 is Figure 4 a block diagram of a quaternion signal generator circuit used in the circuit of; and

[0024] Figure 6A It's a picture Figure 5 A timing diagram of a double data rate (DDR) quad switching operation of a quad signal generator circuit;

[0025] Figure 6B is a timing diagram illustrating half data rate (HDR) quad switching operation. DETAILED DESCRIPTION

[0026] Now refer to Figure 3A , which shows a time domain block diagram of a continuous time sigma-delta analog-to-digital converter (modulator) circuit 100 having a multi-bit quantizer, a data weighted average, and a quaternary signal generator that controls a quaternary switching digital-to-analog converter. Circuit 100 includes a continuous time sigma-delta modulator circuit 12 (illustrated here as a first order circuit, but it is understood that the loop filter of the modulator can have any order suitable for the circuit application requirements; see Figure 3B) and has an input configured to receive an analog input signal A and a digital output signal B consisting of a stream of thermometer-encoded data words. The thermometer-encoded values in the pulse stream of signal B at the sampling rate fs are processed in a decimation circuit 14 (including a low-pass filter and a downsampler) to generate an equivalent digital signal C of the input signal A with a desired resolution and a desired output word rate fd, where fd << fs, set by a decimation factor.

[0027] The first-order sigma-delta modulator circuit 12 includes a difference amplifier 20 (or summing circuit) having a first (non-inverting) input receiving the analog input signal A and a second (inverting) input receiving an analog feedback signal D. The difference amplifier 20 outputs an analog difference signal (i.e., vdif(t) = A(t) - D(t)) in response to the difference between the analog input signal A and the analog feedback signal D. The analog difference signal vdif is integrated by an integrator circuit 22 (a loop filter, here of first-order type but not limited to) to generate a varying signal vc, whose slope and magnitude depend on the sign and magnitude of the analog difference signal vdif. The N-bit quantization circuit 24 samples the varying signal vc at the sampling rate fs in response to a clock CLK and generates a digital output signal B as a 2 N -1-bit thermometer-encoded output word (where N is an integer N > 1). A circuit 30 implementing a data-weighted averaging (DWA) algorithm receives the 2 N -1-bit thermometer-encoded output word and outputs a 2 N -1-bit output DWA word for first-order mismatch shaping of a DAC element. A quaternary signal generator circuit 104 receives the 2 N -1-bit output DWA word and the sampling clock CLK and generates four 2 N -1-bit control words DP1, DP2, DM1, and DM2, whose data values change at the same rate as the rate of the sampling clock CLK. The DAC circuit 126 includes 2 N -1 unit resistor DAC elements (UE), which are respectively driven by the 2 N -1-bit corresponding bits of the control words DP1, DP2, DM1, and DM2 to generate currents, which are summed at the output of the DAC circuit to produce an analog signal for the analog feedback signal D. The decimation circuit 14 low-pass filters and downsamples the 2 N -1-bit code words in the stream of the digital output signal B to generate a digital signal C, which consists of a stream of multi-bit (M-bit, desired resolution, where M is an integer M >> N) digital words generated at an output word rate fd set by the decimation factor.

[0028] Figure 3AThe embodiment shown is a simplified version. In a preferred embodiment, the analog signal processing portion of circuit 100 is configured as a fully differential circuit. Figure 3B shows the use of a third-order modulator Figure 3A 1 is a circuit diagram of a differential signal implementation of the circuit. The loop filter is formed by operational amplifiers OP1, OP2, and OP3 to provide a difference amplifier 20 and an integrator circuit 22 for a third-order implementation of the sigma-delta modulator circuit 12 in a configuration with a cascaded integrator with feedforward and feedback (CIFF-FB). Due to the choice of a third-order implementation with CIFF-FB, two DACs 126 are required. Each DAC 126 receives two of the control words DP1, DP2, DM1, and DM2 output from the quaternary signal generator circuit 104. N -1 bit, and provides a differential output signal D (Outm and Outp). Operational amplifier OP1 receives signals A (Inm and Inp) and D1 (Outm1 and Outp1 from one of the DACs) as a differential signal. Operational amplifier OP3 receives signal D2 (Outm2 and Outp2 from the other of the DACs) as a differential signal combined with the differential signal output from operational amplifier OP2 and differential input signal A (Inp and Inm). Quantization circuit 24 receives signal vc output from integrator circuit 22 as a differential signal.

[0029] exist Figure 3B In the context of differential signaling shown, Figure 4 FIG. 1 shows a block diagram of a DAC circuit 126 as a differential circuit. The DAC circuit 126 includes two N - 1 unit resistance DAC element (UE) 110(1) to 110(2 N -1), these elements are selectively activated in response to the control word output of the quaternary signal generator circuit 104 to generate the analog feedback signal D. Each unit resistance DAC element 110 receives the control word DP1<2 N -1:1>、DP2<2 N -1:1>、DM1<2 N -1:1>and DM2<2 N -1:1>. For example, the unit resistance DAC element 110(1) receives the first bits DP1(1), DP2(1), DM1(1) and DM2(1), the unit resistance DAC element 110(2) receives the second bits DP1(2), DP2(2), DM1(2) and DM2(2) ..., and the unit resistance DAC element 110(2) receives the second bits DP1(2), DP2(2), DM1(2) and DM2(2) ... N -1) Receive the second N -1 DP1(2 N-1), DP2(2 N -1),DM1(2 N -1) and DM2(2 N -1). The quaternary signal generator circuit 104 generates the quaternary signal from 2 in the manner described in detail herein. N -1 bit output DWA word generates control word DP1<2 N -1:1>、DP2<2 N -1:1>、DM1<2 N -1:1>and DM2<2 N -1:1>bit. Control word DP1<2 N -1:1>、DP2<2 N -1:1>、DM1<2 N -1:1>and DM2<2 N The bits of -1:1> change at the same rate as the sampling clock CLK.

[0030] For each given X, where X is from 1 to 2 N -1, the unit resistance DAC element 110 (X) includes a first CMOS inverter (switching) circuit, which is formed by a pMOS transistor 142 and an nMOS transistor 144, whose source-drain paths are coupled in series between a first reference voltage Vrefp and a second reference voltage Vrefm. The first switching circuit switches between the first reference voltage and the second reference voltage in response to some of the control words, wherein: the gate of the pMOS transistor 142 receives the bit DP1B (X), which is the control word DP1 < 2 N The gate of the nMOS transistor 144 receives the control word DM1<2 N The cell resistance DAC element 110(X) further includes a second CMOS inverter (switching) circuit formed by a pMOS transistor 152 and an nMOS transistor 154, whose source-drain paths are coupled in series between the first reference voltage Vrefp and the second reference voltage Vrefm. The second switching circuit switches between the first reference voltage and the second reference voltage in response to certain of the control words, wherein: the gate of the pMOS transistor 152 receives the bit DP2B(X) (generated by the inverter 156), which is the control word DP2<2 N The gate of the nMOS transistor 124 receives the control word DM2<2 NThe common drain terminal of transistors 142 and 144 at node 160 is connected to a first output node 164 of the unit resistance DAC element 110 (X) through resistor 161. The common drain terminal of transistors 152 and 154 at node 163 is connected to a first output node 164 of the unit resistance DAC element 110 (X) through resistor 162. A first output current signal is generated at first output node 164.

[0031] The cell resistance DAC element 110(X) further includes a third CMOS inverter (switching) circuit formed by a pMOS transistor 172 and an nMOS transistor 174, whose source-drain paths are coupled in series between a first reference voltage Vrefp and a second reference voltage Vrefm. The third switching circuit switches between the first reference voltage and the second reference voltage in response to certain of the control words, wherein: the gate of the pMOS transistor 172 receives the bit DM1B(X) (generated by the inverter 176), which is the control word DM1<2 N The gate of the nMOS transistor 174 receives the control word DP1<2 N The cell resistance DAC element 110(X) further includes a fourth CMOS inverter (switching) circuit formed by a pMOS transistor 182 and an nMOS transistor 184, whose source-drain paths are coupled in series between the first reference voltage Vrefp and the second reference voltage Vrefm. The fourth switching circuit switches between the first reference voltage and the second reference voltage in response to certain of the control words, wherein: the gate of the pMOS transistor 182 receives the bit DM2B(X) (generated by the inverter 186), which is the control word DM2<2 N The gate of nMOS transistor 184 receives control word DP2<2 N The common drain terminal of transistors 172 and 174 at node 190 is connected to a second output node 194 of the unit resistance DAC element 110(X) through resistor 191. The common drain terminal of transistors 182 and 184 at node 193 is connected to a second output node 194 of the unit resistance DAC element 110(X) through resistor 192. A second output current signal is generated at second output node 194.

[0032] Including resistors (161, 162, 191, 192) in the output current path of each CMOS inverter (switching) circuit provides operational advantages. It will be noted that the circuit nodes for the first reference voltage Vrefp and the second reference voltage Vrefm are typically connected to external pins (pads) of the integrated circuit device. The reference voltages will be applied to these pins. Because the circuit nodes are external, there will be some parasitic resistance in their paths. As opposed to using a shared resistor for each pair of CMOS inverter (switching) circuits, using a separate output resistor for each CMOS inverter (switching) circuit reduces the sensitivity of the modulator's dynamic performance to the presence of parasitic resistance.

[0033] The first reference voltage Vrefp and the second reference voltage Vrefm are selected by the circuit designer based on the design voltage of the circuit. In an embodiment, for example, the first reference voltage Vrefp = 1.1 V and the second reference voltage Vrefm = 0 V. Any suitable regulated voltage generator circuit can be used to provide the first reference voltage Vrefp and the second reference voltage Vrefm.

[0034] In the unit resistance DAC elements 110(1) to 110(2 N The first output current signals generated at the first output nodes 164 of the differential analog feedback signal D are connected together at the summing node to generate a first net output DAC current, thereby providing a first component Outp of the differential analog feedback signal D. N The second output current signals at the second output nodes 194 of the differential analog feedback signal D are connected together at the summing node to generate a second net output DAC current, thereby providing a second component Outm of the differential analog feedback signal D. In this embodiment, the analog feedback signal D is a differential current signal formed by the Outp component and the Outm component. The Outp component and the Outm component forming the analog feedback signal D are then input to the second (inverting) differential signal input of the difference amplifier 20. Figure 3B In an embodiment, the Outp and Outm components forming the analog feedback signal D correspond to the Outpx and Outmx components of the signal Dx (where x is 1 or 2 depending on the particular DAC).

[0035] Figure 5A block diagram of the quad signal generator circuit 104 is shown. The sampling clock CLK input to the quad signal generator circuit 104 is processed by the clock phase circuit 200 to output a pair of clock signals DCLK and DCLKB that are 180° out of phase. In an embodiment, the clock DCLK and its logical inverse (i.e., 180° out of phase) clock DCLKB are at the same frequency as the sampling clock CLK. In another embodiment, the clock DCLK and its logical inverse (i.e., 180° out of phase) clock DCLKB are at a different frequency than the sampling clock CLK (e.g., at half frequency using the quad signal generator circuit 104 that also includes a divider for dividing by 2). The clock phase circuit 200 also applies a timing delay that ensures that the edges of the DCLK / DCLB clock track DWAout<2 N In other words, the temporally aligned edges of the DCLK / DCLB clocks cause the DWAout generated in response to the edge of the sampling clock CLK to be less than 2 N The corresponding switching edge transitions of the -1:1> word are delayed by a certain amount of timing delay. The length of the delay imposed by the clock phase circuit 200 is less than half a clock period of the DCLK / DCLB clock, and specifically, less than half a clock period of the sampling clock CLK.

[0036] It is important to resolve the timing misalignment issue in order to avoid generating glitches in the control signals DP1(X), DP2(X), DM1(X), and DM2(X). The quad signal generator circuit 104 is configured to generate glitches by adjusting DWAout<2 N A slight delay of the -1:1> word relative to the DCLK clock and / or DCLKB clock controls the timing alignment to ensure that no glitches are generated.

[0037] 2 received from the DWA circuit 102 N - 1-bit output DWA word (DWAout<2 N -1:1>) is logically inverted by circuit 202 to generate an inverted 2 N - 1-bit output DWA word (DWAoutB<2 N -1:1>). Quaternary control word DP1<2 N -1:1>、DP2<2 N -1:1>、DM1<2 N -1:1>and DM2<2 N -1:1>is obtained by setting DWAout<2 N -1:1>word, DWAoutB<2 N -1:1> word, DCLK clock and DCLKB clock are logically combined as follows to generate the control word DP1<2 N-1:1>is achieved by DWAout<2 N -1:1> word and DCLK clock logic AND operation 210 to generate. Control word DP2 <2 N -1:1> is achieved by using the buffer delay circuit 230 to delay DWAout<2 N -1:1> words and DWAout for delay <2 N -1:1> word and DCLKB clock are logically ANDed 214 to generate the control word DM1<2 N -1:1>is achieved by DWAoutB<2 N -1:1> word and DCLK clock are logically ANDed 218 to generate the control word DM2<2 N -1:1>is achieved by using the buffer delay circuit 232 to delay DWAoutB<2 N -1:1> word and DWAoutB<2 for delay N The -1:1> word is generated by performing a logical AND operation 222 with the DCLKB clock.

[0038] In an embodiment, each of the buffer delay circuits 230 and 232 may include a plurality of buffer / inverter circuits connected in series, where the number of such circuits sets the length of the applied signal delay. In each case, the buffer delay circuits 230 and 232 each apply a timing delay that ensures that the delayed DWAout is less than 2 N -1:1> The switching edge transition of the word tracks the edge of the DCLK / DCLB clock. In other words, the delayed DWAout < 2 N The switching edge transition of the -1:1> word causes the temporarily aligned edge of the DCLK / DCLB clock to lag by the length of the applied signal delay. It will also be understood that in embodiments, the length of the applied signal delay can be dynamically controlled (e.g., in response to voltage and temperature variations during circuit operation). Additionally, the length of the applied signal delay can be set during a calibration operation to account for process variations. The length of the delay applied by each of the buffered delay circuits 230 and 232 is typically the same as and less than half a clock period of the DCLK / DCLB clock, and specifically, less than half a clock period of the sampling clock CLK.

[0039] In a preferred embodiment, the total length of the sum of the length of the delay applied by clock phase circuit 200 and the length of any one of the delays applied by one of buffer delay circuits 230 and 232 is less than half a clock period of the DCLK / DCLB clock, and specifically, less than half a clock period of the sampling clock CLK.

[0040] Delay the DCLK / DCLB clocks to track DWAout < 2 N -1:1 > The switching edge transition of the word ensures that there are no glitches in the control signals DP1(X) and DM1(X). The delays introduced by the buffer delay circuits 230, 232 also ensure that DWAout < 2 of the delays used in generating the control signals DP2(X) and DM2(X) N -1:1 > The switching edge transition of the word tracks the edges of the DCLK / DCLB clocks, so that there are no glitches in the control signals DP2(X) and DM2(X). By undergoing control of the timing alignment, this solution does not require latching the control signals DP1(X), DP2(X), DM1(X), and DM2(X), and supports operation in which the excess loop delay (ELD) is kept below one period Ts of the sampling clock CLK (ELD preferably satisfies the following constraint: 0.5Ts < ELD < 0.75Ts).

[0041] Figure 6A A timing diagram showing the operation of the quaternary signal generator circuit 104 is shown. The quaternary signal generator circuit 104 operates to provide double data rate (DDR) quaternary switching for <1100101>0>example data signals. For purposes of comparison, Figure 6B a timing diagram of the same data signal when using half data rate (HDR) quaternary switching is shown. [[ID=​​​​​​​​​​​​​​​​​​​​

[0043] 2 N The output of a single unit DAC element is summed at the virtual ground node of the first and third integrators of a third-order, four-bit CIFFB continuous-time Sigma Delta modulator. Multi-bit quantizers and DACs are used in Sigma Delta ADCs to achieve high SQNR with low OSR and reduce dither noise.

[0044] Multi-bit DAC nonlinearity increases the noise floor and introduces harmonic distortion in the ADC output. As a result, the dynamic performance of the ADC (SNR, SFDR, THD) is severely degraded. To provide more linear multi-bit DAC linearity, DWA is used to minimize the effects of mismatch in the DAC elements. With DWA, the DAC elements are switched on every rising edge of the clock. Due to DWA, the data-dependent switching is significantly higher and therefore increases the noise floor and introduced distortion in the modulator output spectrum. Double Data Rate (DDR) performs quad switching of the multi-bit DAC and quad signal generation (with minimum delay to minimize ELD effects and glitches) to achieve excellent dynamic performance of approximately 100 dB.

[0045] Although disclosed herein in the context of a continuous-time delta sigma modulator, it will be understood that the circuits and operations disclosed herein are equally applicable to discrete-time modulators.

[0046] Although the present invention has been illustrated and described in detail in the drawings and the foregoing description, such illustration and description are to be considered illustrative rather than restrictive; the invention is not limited to the disclosed embodiments. Other variations of the disclosed embodiments can be understood and effected by those skilled in the art in practicing the claimed invention, from a study of the drawings, the disclosure, and the appended claims.

Claims

1. A circuit comprising: DAC circuit with 2 N - 1 unit resistance DAC element, wherein each unit resistance DAC element includes four switching circuits, the four switching circuits are composed of four 2 N -1 bit control signal corresponding to the bit control, and wherein the 2 N The outputs of the 1-unit resistor DAC elements are summed to generate an analog output signal, where N is a positive integer. as well as A four-element signal generator circuit is configured to respond to 2 N -1-bit thermometer coded input signal generates the four 2 N -1-bit control signal, wherein the quaternary signal generator circuit includes: A clock phase circuit configured to generate a first clock signal and a second clock signal, the first clock signal and the second clock signal being 180° out of phase with each other, and the clock phase circuit configured to apply a first delay to set clock edges of the first clock signal and the second clock signal to track the two N - Logic switching of 1-bit thermometer coded input signal; The first circuit is configured to convert the 2 N -1 bit thermometer coded input signal is logically combined with the first clock signal to generate the four 2 N - The first 2 in the 1-bit control signal N -1-bit control signal; The second circuit is configured to convert the 2 N -1 bit thermometer coded input signal is delayed and logically combined with the second clock signal to generate the four 2 N - The second 2 in the 1-bit control signal N -1 bit control signal, wherein the second circuit applies a second delay to set the delayed 2 N - said logic switching of a 1-bit thermometer coded input signal to track said clock edges of said first clock signal and said second clock signal; The third circuit is configured to convert the 2 N - The logical inversion of the 1-bit thermometer coded input signal is logically combined with the first clock signal to generate the four 2 N - The third 2 in the 1-bit control signal N - 1-bit control signal; and The fourth circuit is configured to convert the 2 N - The delayed logic inversion of the 1-bit thermometer coded input signal is logically combined with the second clock signal to generate the four 2 N - The fourth 2 in the 1-bit control signal N -1 bit control signal, wherein the fourth circuit applies a third delay to set the 2 N - said logical switching of said delayed logical inversion of a 1-bit thermometer coded input signal to track said clock edges of said first clock signal and said second clock signal.

2. The circuit according to claim 1, wherein the clock phase circuit of the quaternary signal generator circuit further applies frequency division to N The sampling clock is divided by the clock edge aligned with the logic switching of the 1-bit thermometer coded input signal to generate the first clock signal and the second clock signal. The circuit of claim 2 , wherein the frequency division is division by two.

4. The circuit of claim 1 , wherein the clock phase circuit of the quaternary signal generator circuit is a clock phase circuit having a phase with the 2 N The first clock signal and the second clock signal are derived by aligning the logic switching of the 1-bit thermometer coded input signal with the clock edge of the sampling clock. The circuit of claim 4 , wherein the first delay is less than half a clock period of the sampling clock. 6 . The circuit of claim 5 , wherein the second delay and the third delay are each less than half the clock period of the sampling clock. 7 . The circuit of claim 6 , wherein a sum of one of the second delay and the third delay and the first delay is less than half the clock period of the sampling clock.

8. The circuit of claim 4, wherein the second delay and the third delay are equal. 9 . The circuit of claim 4 , wherein the second delay and the third delay are each less than half a clock period of the sampling clock.

10. The circuit of claim 1 , wherein each of the four switching circuits of each unit resistance DAC element comprises: The first switching circuit is configured to respond to the four 2 N -1-bit control signal in the first 2 N -1-bit control signal logic inversion and the four 2 N -1 bit control signal in the third 2 N - a 1-bit control signal to switch the first common node between a first reference voltage and a second reference voltage; The second switching circuit is configured to respond to the four 2 N -1-bit control signal in the second 2 N -1-bit control signal logic inversion and the four 2 N -1 bit control signal in the fourth 2 N - a 1-bit control signal to switch the second common node between the first reference voltage and the second reference voltage; The third switching circuit is configured to respond to the four 2 N -1 bit control signal in the third 2 N -1-bit control signal logic inversion and the four 2 N -1-bit control signal in the first 2 N - a 1-bit control signal to switch the third common node between the first reference voltage and the second reference voltage; as well as The fourth switching circuit is configured to respond to the four 2 N -1 bit control signal in the fourth 2 N -1-bit control signal logic inversion and the four 2 N -1-bit control signal in the second 2 N −1-bit control signal, switching the fourth common node between the first reference voltage and the second reference voltage.

11. The circuit of claim 10 , further comprising: a first resistive circuit coupled between the first common node and a first summing output node to provide a first component of the analog output signal; a second resistive circuit coupled between the second common node and the first summing output node to provide the first component of the analog output signal; a third resistive circuit coupled between the third common node and a second summing output node to provide a second component of the analog output signal; as well as A fourth resistive circuit is coupled between the fourth common node and the second summing output node to provide the second component of the analog output signal. 12 . The circuit of claim 11 , wherein the first component and the second component are differential currents of the analog output signal.

13. The circuit according to claim 1, wherein said 2 N The 1-bit thermometer coded input signal is generated using data weighted averaging (DWA).

14. The circuit of claim 13 , further comprising: The data weighted average DWA circuit is configured to receive 2 N -1 bit thermometer coded signal is subjected to data weighted averaging to generate the 2 N - 1-bit thermometer coded input signal.

15. The circuit of claim 14, further comprising: A multi-bit quantization circuit is configured to generate the 2 N - 1-bit thermometer coded signal.

16. The circuit of claim 1 , further comprising: The loop filter circuit is configured to generate a difference signal from a difference between an analog input signal and the analog output signal, and to filter the difference signal to generate a change signal.

17. The circuit of claim 16, further comprising: A multi-bit quantization circuit is configured to quantize the change signal and generate 2 N -1 bit thermometer code signal, the 2 N -1 bit thermometer coded input signal is from the 2 N - 1-bit thermometer coded signal generated.

18. The circuit of claim 17, further comprising: The data weighted average DWA circuit is configured to provide the 2 N -1 bit thermometer coded signal is subjected to data weighted averaging to generate the 2 N - 1-bit thermometer coded input signal.

19. The circuit of claim 1, wherein the first delay is less than half of a clock period of the first clock signal and the second clock signal.

20. The circuit of claim 19, wherein the second delay and the third delay are each less than half the clock period of the first clock signal and the second clock signal. 21 . The circuit of claim 20 , wherein a sum of one of the second delay and the third delay and the first delay is less than half of the clock period of the first clock signal and the second clock signal.

22. The circuit of claim 1, wherein the second delay and the third delay are equal.

23. The circuit of claim 1, wherein the second delay and the third delay are each less than half a clock period of the first clock signal and the second clock signal.

Images