Display panel and display device

Abstract

In order to solve the problem caused by uneven overlapping of data fan-out lines and control signal lines, the utility model provides a display panel and a display device, the display panel comprises a substrate, a plurality of sub-pixels and a plurality of data lines which are located in a display area, and a plurality of data fan-out lines and a plurality of control signal lines which are located in a first frame area. The plurality of data fan-out lines comprise a first group of data fan-out lines and a second group of data fan-out lines, and the plurality of control signal lines comprise a first group of control signal lines and a second group of control signal lines. The number of control signal lines in the first group of control signal lines is greater than the number of control signal lines in the second group of control signal lines. Each data fan-out line in the first group of data fan-out lines is overlapped with the orthographic projection of the first group of control signal lines on the substrate, and each data fan-out line in the second group of data fan-out lines is overlapped with the orthographic projection of the second group of control signal lines on the substrate. And at least one organic insulating layer is arranged between the data fan-out lines and the control signal lines with overlapped orthographic projections on the substrate.

Description

Technical Field

[0001] The present invention relates to but is not limited to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] Organic Light Emitting Diode (OLED) is an active light-emitting display device with the advantages of self-luminescence, wide viewing angle, high contrast, low power consumption, and extremely high response speed. With the continuous development of display technology, display devices using OLED as a light-emitting device and thin film transistors (TFT) for signal control have become the mainstream products in the current display field. Utility Model Content

[0003] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0004] To address display defects such as low-grayscale dark stripes caused by uneven overlap of data fan-out lines and control signal lines, embodiments of the present invention provide a display panel and a display device.

[0005] On the one hand, the present embodiment provides a display panel, comprising: a substrate, a plurality of sub-pixels, a plurality of data lines, a plurality of data fan-out lines, and a plurality of control signal lines. The substrate comprises: a display area, and a first frame area located on one side of the display area. A plurality of sub-pixels and a plurality of data lines are located in the display area, and the plurality of data lines are connected to the plurality of sub-pixels and configured to provide data signals to the plurality of sub-pixels. A plurality of data fan-out lines and a plurality of control signal lines are located in the first frame area. The plurality of data fan-out lines are configured to provide data signals to the plurality of data lines; the plurality of data fan-out lines comprise: a first group of data fan-out lines and a second group of data fan-out lines, and the plurality of control signal lines comprise: a first group of control signal lines and a second group of control signal lines. The number of control signal lines in the first group of control signal lines is greater than the number of control signal lines in the second group of control signal lines. Each data fan-out line in the first group of data fan-out lines overlaps with the first group of control signal lines on the orthographic projection of the substrate, and each data fan-out line in the second group of data fan-out lines overlaps with the second group of control signal lines on the orthographic projection of the substrate. At least one organic insulating layer is provided between the data fan-out lines and the control signal lines whose orthographic projections overlap with the substrate.

[0006] In some exemplary embodiments, the control signal line includes: a first control line segment, the first control line segment having an orthographic projection on the substrate overlapping with the orthographic projection of the first group of data fan-out lines or the second group of data fan-out lines on the substrate, the first control line segment being located on a side of the first group of data fan-out lines or the second group of data fan-out lines away from the substrate, and the first control line segment intersecting with an extension direction of the multiple data fan-out lines.

[0007] In some exemplary embodiments, in a direction perpendicular to the display panel, the display panel at least includes: a first gate metal layer, a second gate metal layer, a first source-drain metal layer, and a second source-drain metal layer arranged in a direction away from the substrate; at least a first planar layer is arranged between the first source-drain metal layer and the second source-drain metal layer. The plurality of data fan-out lines are located in at least one of the first gate metal layer and the second gate metal layer, and a first control line segment of the plurality of control signal lines is located in the second source-drain metal layer.

[0008] In some exemplary embodiments, in a direction perpendicular to the display panel, the display panel at least includes: a first gate metal layer, a second gate metal layer, a first source-drain metal layer, a second source-drain metal layer, and a third source-drain metal layer arranged in a direction away from the substrate; at least a first flat layer is arranged between the first source-drain metal layer and the second source-drain metal layer, and at least a second flat layer is arranged between the second source-drain metal layer and the third source-drain metal layer. The plurality of data fan-out lines are located in at least one of the first gate metal layer and the second gate metal layer, and the first control line segment of the plurality of control signal lines is located in the third source-drain metal layer.

[0009] In some exemplary embodiments, the plurality of data fan-out lines include: a plurality of first data fan-out lines located in the first gate metal layer and a plurality of second data fan-out lines located in the second gate metal layer. The plurality of first data fan-out lines and the plurality of second data fan-out lines are arranged one by one at intervals, and the orthographic projections of the plurality of first data fan-out lines and the plurality of second data fan-out lines on the substrate do not overlap.

[0010] In some exemplary embodiments, the control signal line further includes: a second control line segment and a third control line segment, the second control line segment being connected to one end of the first control line segment, the third control line segment being connected to the other end of the first control line segment, the orthographic projections of the second control line segment and the third control line segment on the substrate not overlapping with the orthographic projections of the multiple data fan-out lines on the substrate; the second control line segment and the third control line segment are of the same layer structure, and are located on a side of the first control line segment close to the substrate.

[0011] In some exemplary embodiments, each data fan-out line in the first group of data fan-out lines has a first overlapping area with the first group of control signal lines on the orthographic projection of the substrate, each data fan-out line in the second group of data fan-out lines has a second overlapping area with the second group of control signal lines on the orthographic projection of the substrate, and the ratio of the first overlapping area to the second overlapping area ranges from 0.9 to 1.1.

[0012] In some exemplary embodiments, each data fan-out line in the first group of data fan-out lines includes: a first sub-line segment that overlaps with an orthographic projection of the first group of control signal lines on the substrate. Each data fan-out line in the second group of data fan-out lines includes: a second sub-line segment that overlaps with an orthographic projection of the second group of control signal lines on the substrate. The line width of the first sub-line segment is smaller than the line width of the second sub-line segment.

[0013] In some exemplary embodiments, a ratio of a line width of the second sub-line segment to a line width of the first sub-line segment is greater than 1 and less than 2.

[0014] In some exemplary embodiments, each data fan-out line in the first group of data fan-out lines further includes: a third sub-segment connected to one end of the first sub-segment, and a fourth sub-segment connected to the other end of the first sub-segment; the orthographic projections of the third sub-segment and the fourth sub-segment on the substrate do not overlap with the orthographic projections of the first group of control signal lines on the substrate; the first sub-segment, the third sub-segment, and the fourth sub-segment of each data fan-out line in the first group of data fan-out lines are interconnected as an integrated structure. Each data fan-out line in the second group of data fan-out lines further includes: a fifth sub-segment connected to one end of the second sub-segment, and a sixth sub-segment connected to the other end of the second sub-segment; the orthographic projections of the fifth sub-segment and the sixth sub-segment on the substrate do not overlap with the orthographic projections of the second group of control signal lines on the substrate. The second sub-segment, the fifth sub-segment, and the sixth sub-segment of each data fan-out line in the second group of data fan-out lines are interconnected as an integrated structure. The first sub-line segment, the third sub-line segment, the fourth sub-line segment, the fifth sub-line segment, and the sixth sub-line segment have the same line width.

[0015] In some exemplary embodiments, each data fan-out line in the first group of data fan-out lines includes: a first sub-line segment that overlaps with the orthographic projection of the first group of control signal lines on the substrate. Each data fan-out line in the second group of data fan-out lines includes: a second sub-line segment that overlaps with the orthographic projection of the second group of control signal lines on the substrate. The orthographic projection of the first sub-line segment on the substrate is a straight line, and the orthographic projection of the second sub-line segment on the substrate is a serpentine line.

[0016] In some exemplary embodiments, each data fan-out line in the second group of data fan-out lines further includes: a fifth sub-segment connected to one end of the second sub-segment, and a sixth sub-segment connected to the other end of the second sub-segment; the orthographic projections of the fifth sub-segment and the sixth sub-segment on the substrate do not overlap with the orthographic projections of the second group of control signal lines on the substrate. The second sub-segment, the fifth sub-segment, and the sixth sub-segment of each data fan-out line in the second group of data fan-out lines are interconnected as an integral structure; the orthographic projection of the fifth sub-segment or the sixth sub-segment of at least one data fan-out line in the second group of data fan-out lines on the substrate is a serpentine routing.

[0017] In some exemplary embodiments, each control signal line within the first group of control signal lines includes: a first control line segment that overlaps with the orthographic projection of the first group of data fan-out lines on the substrate; each control signal line within the second group of control signal lines includes: a first control line segment that overlaps with the orthographic projection of the second group of data fan-out lines on the substrate; a line width of the first control line segment of at least one control signal line within the second group of control signal lines is greater than a line width of the first control line segment of the control signal line within the first group of control signal lines.

[0018] In some exemplary embodiments, the substrate further includes: a second frame region and a third frame region located on both sides of the display region along the first direction, and the second frame region and the third frame region are both connected to the first frame region. The display panel further includes: a first group of gate drive circuits located in the second frame region and a second group of gate drive circuits located in the third frame region, and the number of gate drive circuits included in the first group of gate drive circuits is greater than the number of gate drive circuits included in the second gate drive circuit. The first group of control signal lines includes: a plurality of first drive control lines, and the plurality of first drive control lines are configured to provide drive control signals to the first group of gate drive circuits. The second group of control signal lines includes: a plurality of second drive control lines, and the plurality of second drive control lines are configured to provide drive control signals to the second group of gate drive circuits.

[0019] In some exemplary embodiments, at least one of the plurality of sub-pixels includes: a pixel circuit. The first group of gate drive circuits includes: a light-emitting drive circuit, a first reset drive circuit, and a second reset drive circuit; the light-emitting drive circuit is configured to provide a light-emitting control signal to the pixel circuit, the first reset drive circuit is configured to provide a first reset control signal to the pixel circuit, and the second reset drive circuit is configured to provide a second reset control signal to the pixel circuit. The second group of gate drive circuits includes: a first scan drive circuit and a second scan drive circuit; the first scan drive circuit is configured to provide a first scan signal to the pixel circuit, and the second scan drive circuit is configured to provide a second scan signal to the pixel circuit.

[0020] On the other hand, this embodiment provides a display device, including the display substrate as mentioned above.

[0021] On the other hand, the present embodiment provides a display panel, comprising: a substrate, a plurality of sub-pixels, a plurality of data lines, a plurality of data fan-out lines, and a plurality of control signal lines. The substrate comprises: a display area, and a first frame area located on one side of the display area. A plurality of sub-pixels and a plurality of data lines are located in the display area, and the plurality of data lines are connected to the plurality of sub-pixels and configured to provide data signals to the plurality of sub-pixels. A plurality of data fan-out lines and a plurality of control signal lines are located in the first frame area, and the plurality of data fan-out lines are configured to provide data signals to the plurality of data lines. The plurality of data fan-out lines comprise: a first group of data fan-out lines and a second group of data fan-out lines, and the plurality of control signal lines comprise: a first group of control signal lines and a second group of control signal lines; the number of control signal lines in the first group of control signal lines is greater than the number of control signal lines in the second group of control signal lines. Each data fan-out line in the first group of data fan-out lines overlaps with the orthographic projection of the first group of control signal lines on the substrate, and each data fan-out line in the second group of data fan-out lines overlaps with the orthographic projection of the second group of control signal lines on the substrate. Each data fan-out line in the first group of data fan-out lines has a first overlapping area with the orthographic projection of the first group of control signal lines on the substrate, and each data fan-out line in the second group of data fan-out lines has a second overlapping area with the orthographic projection of the second group of control signal lines on the substrate, and the ratio of the first overlapping area to the second overlapping area ranges from 0.9 to 1.1.

[0022] In some exemplary embodiments, each data fan-out line in the first group of data fan-out lines includes: a first sub-line segment that overlaps with an orthographic projection of the first group of control signal lines on the substrate. Each data fan-out line in the second group of data fan-out lines includes: a second sub-line segment that overlaps with an orthographic projection of the second group of control signal lines on the substrate. The line width of the first sub-line segment is smaller than the line width of the second sub-line segment.

[0023] In some exemplary embodiments, each data fan-out line in the first group of data fan-out lines includes: a first sub-line segment that overlaps with the orthographic projection of the first group of control signal lines on the substrate. Each data fan-out line in the second group of data fan-out lines includes: a second sub-line segment that overlaps with the orthographic projection of the second group of control signal lines on the substrate. The orthographic projection of the first sub-line segment on the substrate is a straight line, and the orthographic projection of the second sub-line segment on the substrate is a serpentine line.

[0024] In some exemplary embodiments, each control signal line in the first group of control signal lines includes: a first control line segment that overlaps with an orthographic projection of the first group of data fan-out lines on the substrate. Each control signal line in the second group of control signal lines includes: a first control line segment that overlaps with an orthographic projection of the second group of data fan-out lines on the substrate. The line width of the first control line segment of at least one control signal line in the second group of control signal lines is greater than the line width of the first control line segment of the control signal line in the first group of control signal lines.

[0025] In the display panel provided in the present embodiment, at least one organic insulating layer is provided between the data fan-out line and the overlapping control signal line in the first frame area, so that the distance between the data fan-out line and the overlapping control signal line can be increased, thereby reducing the parasitic capacitance between the data fan-out line and the overlapping control signal line, and improving the display defects such as low grayscale dark stripes caused by the uneven overlap between the data fan-out line and the control signal line transmitting the AC signal. Alternatively, by adjusting the overlapping area between each data fan-out line and the plurality of control signal lines, the parasitic capacitance between the data fan-out line and the overlapping control signal line is adjusted, so that the parasitic capacitance between the two groups of data fan-out lines and the control signal line is substantially the same, thereby optimizing the display defects such as low grayscale dark stripes caused by the uneven overlap between the data fan-out line and the control signal line transmitting the AC signal.

[0026] Other features and advantages of the utility model will be described in the following description, and partly become apparent from the description, or understood by implementing the utility model. Other advantages of the utility model can be realized and obtained by the schemes described in the description and the drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] The accompanying drawings are used to provide a further understanding of the technical solution of the utility model and constitute a part of the specification. Together with the embodiments of the utility model, they are used to explain the technical solution of the utility model and do not constitute a limitation on the technical solution of the utility model.

[0028] Figure 1 A schematic diagram of a display panel according to at least one embodiment of the present invention;

[0029] Figure 2 is an equivalent circuit diagram of a pixel circuit of at least one embodiment of the present utility model;

[0030] Figure 3 for Figure 2 The working timing diagram of the pixel circuit provided;

[0031] Figure 4 A partial cross-sectional schematic diagram of a display area of ​​at least one embodiment of the utility model;

[0032] Figure 5 A schematic diagram of the gate drive circuit of at least one embodiment of the present utility model;

[0033] Figure 6 It is a partial plan view of the first border area of ​​at least one embodiment of the utility model;

[0034] Figure 7 for Figure 6 A partial enlarged schematic diagram of the middle area S1;

[0035] Fig. 8A for Figure 7 An example of a local cross section along the Q1-Q1' direction;

[0036] Figure 8B for Figure 7 An example of a local cross section along the Q2-Q2' direction;

[0037] Fig. 9 Another partial cross-sectional schematic diagram of a display panel of at least one embodiment of the present utility model;

[0038] Fig. 10A for Figure 7 Another example of a local cross-section along the Q1-Q1' direction;

[0039] Fig. 10B for Figure 7 Another example of a partial cross-section along the Q2-Q2' direction;

[0040] Fig.11 Another partial plan view of the first border region of at least one embodiment of the utility model;

[0041] Fig. 12Afor Fig.11 A partial enlarged schematic diagram of the middle area S2;

[0042] Fig. 12B for Fig. 12A A partial schematic diagram of the first set of data fan-out lines;

[0043] Fig.13A for Fig.11 A partial enlarged schematic diagram of the middle area S3;

[0044] Fig. 13B for Fig.13A A partial schematic diagram of the second set of data fan-out lines;

[0045] Fig.14A for Fig.11 Another partial enlarged schematic diagram of the middle area S3;

[0046] Fig. 14B for Fig.14A A partial schematic diagram of the second set of data fan-out lines;

[0047] Fig.15 for Fig.11 Another partial enlarged schematic diagram of the middle area S3;

[0048] Fig.16A for Fig.11 Another partial enlarged schematic diagram of the middle area S2;

[0049] Fig. 16B for Fig.16A A partial schematic diagram of the first set of data fan-out lines;

[0050] Fig.17A for Fig.11 Another partial enlarged schematic diagram of the middle area S3;

[0051] Fig. 17B for Fig.17A A partial schematic diagram of the second set of data fan-out lines;

[0052] Fig.18 It is a schematic diagram of a display device according to at least one embodiment of the present invention. DETAILED DESCRIPTION

[0053] The following will describe the embodiments of the present invention in detail with reference to the accompanying drawings. The embodiments can be implemented in a plurality of different forms. A person skilled in the art can easily understand the fact that the method and content can be transformed into various forms without departing from the purpose and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the contents of the utility model described in the following embodiments. In the absence of conflict, the embodiments of the present invention and the features in the embodiments can be combined with each other arbitrarily.

[0054] In the drawings, the size of one or more components, the thickness of a layer, or an area is sometimes exaggerated for the sake of clarity. Therefore, one embodiment of the utility model is not necessarily limited to the size, and the shape and size of one or more components in the drawings do not reflect the true proportion. In addition, the drawings schematically show ideal examples, and one embodiment of the utility model is not limited to the shapes or values ​​shown in the drawings.

[0055] The ordinal numbers such as "first", "second", "third" and the like in this specification are provided to avoid confusion of constituent elements, rather than to limit the quantity. The "plurality" in this utility model means two or more.

[0056] In this specification, for the sake of convenience, the words and phrases indicating the orientation or positional relationship such as "middle", "upper", "lower", "front", "back", "vertical", "horizontal", "top", "bottom", "inside", "outside" and the like are used to illustrate the positional relationship of the constituent elements with reference to the drawings. This is only for the convenience of describing this specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation, and therefore cannot be understood as a limitation on the present utility model. The positional relationship of the constituent elements is appropriately changed according to the direction in which each constituent element is described. Therefore, it is not limited to the words and phrases described in the specification, and can be appropriately replaced according to the situation.

[0057] In this specification, unless otherwise clearly specified and limited, the terms "installed", "connected" and "connected" should be understood in a broad sense. For example, it can be a fixed connection, or a detachable connection, or an integral connection; it can be a mechanical connection, or a connection; it can be a direct connection, or an indirect connection through an intermediate, or the internal communication of two elements. For ordinary technicians in this field, the meanings of the above terms in this utility model can be understood according to the circumstances.

[0058] In this specification, a transistor refers to an element including at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. In this specification, a channel region refers to a region where current mainly flows.

[0059] In this specification, the first electrode may be a drain electrode and the second electrode may be a source electrode, or the first electrode may be a source electrode and the second electrode may be a drain electrode. In the case of using transistors with opposite polarities or when the direction of current changes during circuit operation, the functions of the "source electrode" and the "drain electrode" are sometimes interchanged. Therefore, in this specification, the "source electrode" and the "drain electrode" may be interchanged.

[0060] In this specification, "connection" includes the case where the components are connected together through an element having some electrical function. There is no particular limitation on the "element having some electrical function" as long as it can transmit electrical signals between the connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having various functions.

[0061] In this specification, "parallel" means a state where the angle formed by two straight lines is greater than -10° and less than 10°, and therefore, also includes a state where the angle is greater than -5° and less than 5°. In addition, "perpendicular" means a state where the angle formed by two straight lines is greater than 80° and less than 100°, and therefore, also includes a state where the angle is greater than 85° and less than 95°.

[0062] The terms “approximately” and “substantially” in the present invention do not strictly define the limits, but allow for process and measurement errors.

[0063] In this specification, A extends along direction B means that A may include a main part and a secondary part connected to the main part, the main part is a line, line segment or strip-shaped body, the main part extends along direction B, and the length of the main part extending along direction B is greater than the length of the secondary part extending along other directions. In this specification, "A extends along direction B" means "the main part of A extends along direction B".

[0064] In this specification, "A and B are of the same layer structure" means that A and B are formed simultaneously by the same patterning process. "The same layer" does not always mean that the thickness of the layer or the height of the layer is the same in the cross-sectional view. "The orthographic projection of A includes the orthographic projection of B" means that the orthographic projection of B falls within the orthographic projection range of A, or the orthographic projection of A covers the orthographic projection of B.

[0065] With the development of display technology, users' requirements for display quality are gradually increasing. In the lower frame area of ​​the display panel, the capacitance generated by the overlapping of the traces will affect the load difference of the signal transmitted by the traces (for example, the load difference of the data signal), resulting in poor display of the display panel. Taking the display panel applied to wearable products such as watches as an example, the data fan-out line transmitting the data signal overlaps with the trace transmitting the AC signal, which will cause signal load difference, resulting in poor display such as light and dark stripes or split screen.

[0066] The present embodiment provides a display panel, comprising: a substrate, a plurality of sub-pixels, a plurality of data lines, a plurality of data fan-out lines, and a plurality of control signal lines. The substrate comprises: a display area, and a first frame area located on one side of the display area. A plurality of sub-pixels and a plurality of data lines are located in the display area, and a plurality of data lines are connected to a plurality of sub-pixels and configured to provide data signals to the plurality of sub-pixels. A plurality of data fan-out lines and a plurality of control signal lines are located in the first frame area, and a plurality of data fan-out lines are configured to provide data signals to a plurality of data lines. A plurality of data fan-out lines comprise: a first group of data fan-out lines and a second group of data fan-out lines, and a plurality of control signal lines comprise: a first group of control signal lines and a second group of control signal lines; the number of control signal lines in the first group of control signal lines is greater than the number of control signal lines in the second group of control signal lines. Each data fan-out line in the first group of data fan-out lines overlaps with the first group of control signal lines in their orthographic projection on the substrate, and each data fan-out line in the second group of data fan-out lines overlaps with the second group of control signal lines in their orthographic projection on the substrate. At least one organic insulating layer is disposed between the data fan-out line and the control signal line overlapping in an orthographic projection of the substrate.

[0067] In the display panel provided in the present embodiment, in the first frame area, at least one organic insulating layer is arranged between the data fan-out line and the overlapping control signal line, which can increase the distance between the data fan-out line and the overlapping control signal line, thereby reducing the parasitic capacitance between the data fan-out line and the overlapping control signal line, and can improve display defects such as low grayscale dark stripes caused by uneven overlap of the data fan-out line and the control signal line transmitting the AC signal.

[0068] In some exemplary embodiments, the control signal line may include: a first control line segment, the orthographic projection of the first control line segment on the substrate overlaps with the orthographic projection of the first group of data fan-out lines or the second group of data fan-out lines on the substrate, the first control line segment may be located on the side of the first group of data fan-out lines or the second group of data fan-out lines away from the substrate, and the first control line segment and the extension direction of the plurality of data fan-out lines may intersect. In some examples, in a direction perpendicular to the display panel, the display panel may include at least: a first gate metal layer, a second gate metal layer, a first source-drain metal layer, and a second source-drain metal layer arranged along a direction away from the substrate; at least a first flat layer is arranged between the first source-drain metal layer and the second source-drain metal layer. The plurality of data fan-out lines may be located in at least one of the first gate metal layer and the second gate metal layer, and the first control line segment of the plurality of control signal lines may be located in the second source-drain metal layer. In other examples, in a direction perpendicular to the display panel, the display panel may include at least: a first gate metal layer, a second gate metal layer, a first source-drain metal layer, a second source-drain metal layer, and a third source-drain metal layer arranged in a direction away from the substrate; at least a first flat layer may be arranged between the first source-drain metal layer and the second source-drain metal layer, and at least a second flat layer may be arranged between the second source-drain metal layer and the third source-drain metal layer. A plurality of data fan-out lines may be located in at least one of the first gate metal layer and the second gate metal layer, and a first control line segment of a plurality of control signal lines may be located in the third source-drain metal layer. In this example, by setting a film layer where the first control line segment of the control signal line is located (for example, the first control line segment is located in the second source-drain metal layer or the third source-drain metal layer), the distance between the data fan-out line and the first control line segment of the overlapping control signal line is increased, and the parasitic capacitance between the data fan-out line and the overlapping control signal line can be reduced, thereby effectively improving the display defects such as low grayscale dark stripes caused by the uneven overlap of the data fan-out line and the control signal line.

[0069] In some exemplary embodiments, each data fan-out line in the first group of data fan-out lines has a first overlapping area with the orthographic projection of the first group of control signal lines on the substrate, and each data fan-out line in the second group of data fan-out lines has a second overlapping area with the orthographic projection of the second group of control signal lines on the substrate, and the ratio of the first overlapping area to the second overlapping area may range from 0.9 to 1.1, such as 1.0. For example, the first overlapping area and the second overlapping area may be substantially the same. This example adjusts the parasitic capacitance between the data fan-out line and the overlapping control signal line by adjusting the overlapping area between each data fan-out line and the plurality of control signal lines, so that the parasitic capacitance between the two groups of data fan-out lines and the control signal line is substantially the same, thereby optimizing display defects such as low grayscale dark stripes caused by uneven overlap between the data fan-out line and the control signal line transmitting the AC signal.

[0070] In some exemplary embodiments, each data fan-out line in the first group of data fan-out lines may include: a first sub-line segment that overlaps with the orthographic projection of the first group of control signal lines on the substrate; each data fan-out line in the second group of data fan-out lines may include: a second sub-line segment that overlaps with the orthographic projection of the second group of control signal lines on the substrate. The line width of the first sub-line segment may be smaller than the line width of the second sub-line segment. For example, the ratio of the line width of the second sub-line segment to the line width of the first sub-line segment may be greater than 1 and less than 2. In this example, by increasing the line width of the second sub-segment of the second group of data fan-out lines, the overlapping area between the second group of data fan-out lines and the second group of control signal lines can be increased, so that the second overlapping area corresponding to the data fan-out lines in the second group of data fan-out lines can be roughly the same as the first overlapping area corresponding to the data fan-out lines in the first group of data fan-out lines, and the parasitic capacitance between the second group of data fan-out lines and the overlapping wiring is increased, so that the parasitic capacitance between the two groups of data fan-out lines and the overlapping wiring is roughly the same, thereby improving display defects such as low grayscale dark stripes caused by uneven overlap of the data fan-out lines and the control signal lines.

[0071] In some exemplary embodiments, each data fan-out line in the first group of data fan-out lines may include: a first sub-line segment that overlaps with the orthographic projection of the first group of control signal lines on the substrate; each data fan-out line in the second group of data fan-out lines may include: a second sub-line segment that overlaps with the orthographic projection of the second group of control signal lines on the substrate. The orthographic projection of the first sub-line segment on the substrate may be a straight line, and the orthographic projection of the second sub-line segment on the substrate may be a serpentine line. The serpentine line is a meandering curve. For example, after one end of the line extends a distance in one direction, it bends and twists and extends a distance in the opposite direction to the direction, bends and twists again and extends in the direction, and bends and twists repeatedly several times to form a serpentine line. This example uses a serpentine line design for some segments of the second group of data fan-out lines to increase the overlapping area between the second group of data fan-out lines and the second group of control signal lines, thereby reducing the difference in parasitic capacitance between the two groups of data fan-out lines and the overlapping control signal lines.

[0072] In some exemplary embodiments, each control signal line in the first group of control signal lines may include: a first control line segment that overlaps with the orthographic projection of the first group of data fan-out lines on the substrate; each control signal line in the second group of control signal lines may include: a first control line segment that overlaps with the orthographic projection of the second group of data fan-out lines on the substrate. The line width of the first control line segment of at least one control signal line in the second group of control signal lines may be greater than the line width of the first control line segment of the control signal line in the first group of control signal lines. In this example, by increasing the line width of the first control line segment of the second group of control signal lines, the overlapping area between the second group of data fan-out lines and the second group of control signal lines can be increased, so that the parasitic capacitance between the two groups of data fan-out lines and the overlapping control signal lines is approximately the same, thereby improving display defects such as low grayscale dark stripes caused by uneven overlap of the data fan-out lines and the control signal lines.

[0073] The solution of this embodiment is described below by means of some examples.

[0074] Figure 1 is a schematic diagram of a display panel of at least one embodiment of the present utility model. In some examples, such as Figure 1 As shown, the display panel may include: a display area AA, a peripheral frame area B2 surrounding the display area AA, and a first frame area B1 located on one side of the display area AA. The first frame area B1 may be located on the side of the peripheral frame area B2 away from the display area AA along the second direction Y. The first frame area B1 may be connected to the peripheral frame area B2. For example, the first frame area B1 may be the lower frame of the display panel. The peripheral frame area B2 may include: a second frame area B21 and a third frame area B22 located on both sides of the display area AA along the first direction X. The second frame area B21 may be connected to the first frame area B1, and the third frame area B22 may be connected to the first frame area B1. For example, the second frame area B21 may be the left frame of the display panel, and the third frame area B22 may be the right frame of the display panel.

[0075] In some examples, such as Figure 1 As shown, the display area AA may be a flat area including a plurality of sub-pixels PX constituting a pixel array, and the plurality of sub-pixels PX may be configured to display a dynamic picture or a still image. The display area AA may be referred to as an active area. In some examples, the display area AA may be circular or elliptical. However, this embodiment is not limited thereto. For example, the display area may be other shapes such as a rectangle. In some examples, the display panel may be a flexible panel, and thus the display panel may be deformable, such as curling, bending, folding, or rolling up.

[0076] In some examples, such as Figure 1As shown, the display area AA may include: a display structure layer arranged on a substrate, or may include a display structure layer and a touch structure layer arranged on a substrate in sequence. For example, the display panel may integrate a touch structure to form a structure of a touch structure on a thin film encapsulation (Touch on Thin Film Encapsulation, referred to as Touch on TFE). The Touch on TFE structure mainly includes a Flexible Multi-Layer On Cell (FMLOC) structure and a Flexible Single-Layer On Cell (FSLOC) structure. The FMLOC structure is based on the working principle of mutual capacitance detection. Generally, two layers of metal are used to form a driving (Tx) electrode and a sensing (Rx) electrode. The driving chip (IC) realizes the touch action by detecting the mutual capacitance between the driving electrode and the sensing electrode. The FSLOC structure is based on the working principle of self-capacitance (or voltage) detection. Generally, a single layer of metal is used to form a touch electrode. The integrated circuit realizes the touch action by detecting the self-capacitance (or voltage) of the touch electrode.

[0077] In some examples, the display structure layer may include a plurality of sub-pixels PX, a plurality of gate lines GL, and a plurality of data lines DL. The plurality of gate lines GL may extend along a first direction X, and the plurality of data lines DL may extend along a second direction Y. The orthographic projections of the plurality of gate lines GL and the plurality of data lines DL on the substrate may intersect to form a plurality of sub-pixel regions. A sub-pixel PX may be disposed in a sub-pixel region. The plurality of data lines DL may be electrically connected to the plurality of sub-pixels PX, and the plurality of data lines DL may be configured to provide data signals to the plurality of sub-pixels PX. The plurality of gate lines GL may be electrically connected to the plurality of sub-pixels PX, and the plurality of gate lines GL may be configured to provide a gate drive signal to the plurality of sub-pixels PX. For example, the gate drive signal may include a scan signal, or may include a scan signal and a light emitting control signal, or may include a scan signal, a reset control signal, and a light emitting control signal.

[0078] In some examples, such as Figure 1 As shown, the first direction X may be the extension direction (e.g., row direction) of the gate lines GL in the display area AA, and the second direction Y may be the extension direction (e.g., column direction) of the data lines DL in the display area AA. The first direction X and the second direction Y may intersect each other, for example, may be perpendicular to each other.

[0079] In some examples, a pixel unit of display area AA may include three sub-pixels, and the three sub-pixels may be a first sub-pixel emitting a first color light (e.g., red light), a second sub-pixel emitting a second color light (e.g., green light), and a third sub-pixel emitting a third color light (e.g., blue light). However, this embodiment is not limited to this. In some examples, a pixel unit may include four sub-pixels, and the four sub-pixels may be a sub-pixel emitting red light, a sub-pixel emitting green light, a sub-pixel emitting blue light, and a sub-pixel emitting white light. For another example, a pixel unit may include four sub-pixels, and the four sub-pixels may include a sub-pixel emitting red light, a sub-pixel emitting blue light, and two sub-pixels emitting green light.

[0080] In some examples, the shape of the sub-pixel may be a rectangle, a rhombus, a pentagon, or a hexagon. When a pixel unit includes three sub-pixels, the three sub-pixels may be arranged in parallel horizontally, vertically, or in a triangular pattern; when a pixel unit includes four sub-pixels, the four sub-pixels may be arranged in parallel horizontally, vertically, or in a square pattern. However, this embodiment is not limited to this.

[0081] In some examples, a sub-pixel may include: a pixel circuit and a light-emitting element electrically connected to the pixel circuit. The pixel circuit may include multiple transistors and at least one capacitor. For example, the pixel circuit may be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C or 8T1C structure. Wherein, T in the above circuit structure refers to a thin film transistor, C refers to a capacitor, the number before T represents the number of thin film transistors in the circuit, and the number before C represents the number of capacitors in the circuit. In some examples, the multiple transistors in the pixel circuit may include P-type transistors and N-type transistors. In other examples, the multiple transistors in the pixel circuit may be P-type transistors or may be N-type transistors. Using the same type of transistors in the pixel circuit can simplify the process flow, reduce the process difficulty of the display substrate, and improve the yield of the product.

[0082] In some examples, the light-emitting element may be any one of a light-emitting diode (LED), an organic light-emitting diode (OLED), a quantum dot light-emitting diode (QLED), a micro-LED (including: mini-LED or micro-LED), etc. For example, the light-emitting element may be an OLED, and the light-emitting element may emit red light, green light, blue light, or white light, etc. when driven by its corresponding pixel circuit. The color of the light emitted by the light-emitting element may be determined as required. In some examples, the light-emitting element may include: an anode, a cathode, and an organic light-emitting layer located between the anode and the cathode. The anode of the light-emitting element may be electrically connected to the corresponding pixel circuit. However, this embodiment is not limited to this.

[0083] Figure 2 is an equivalent circuit diagram of a pixel circuit of at least one embodiment of the present utility model. The pixel circuit of this example is described by taking an 8T1C structure as an example. In some examples, such as Figure 2 As shown, the pixel circuit of this example may include eight transistors (i.e., the first transistor T1 to the eighth transistor T8) and a storage capacitor Cst. The first transistor T1 may also be referred to as a first reset transistor, the second transistor T2 may also be referred to as a threshold compensation transistor, the third transistor T3 may also be referred to as a drive transistor, the fourth transistor T4 may also be referred to as a data writing transistor, the fifth transistor T5 may also be referred to as a first light emission control transistor, the sixth transistor T6 may also be referred to as a second light emission control transistor, the seventh transistor T7 may also be referred to as a second reset transistor, and the eighth transistor T8 may also be referred to as a third reset transistor. The light emitting element EL may include an anode, a cathode, and an organic light emitting layer disposed between the anode and the cathode.

[0084] In some examples, the first transistor T1, the third transistor T3 to the eighth transistor T8 may be first type transistors, for example, P type transistors, and the second transistor T2 may be second type transistors, for example, N type transistors. However, this embodiment is not limited to this. For example, the plurality of transistors of the pixel circuit may all be P type transistors, or may all be N type transistors.

[0085] In some examples, the first type of transistor of the pixel circuit (for example, including the first transistor T1, the third transistor T3 to the eighth transistor T8) can adopt a low-temperature polysilicon thin film transistor, and the second type of transistor of the pixel circuit (for example, including the second transistor T2) can adopt an oxide thin film transistor. The active layer of the low-temperature polysilicon thin film transistor adopts low-temperature polysilicon (LTPS), and the active layer of the oxide thin film transistor adopts an oxide semiconductor (Oxide). Low-temperature polysilicon thin film transistors have the advantages of high mobility and fast charging, and oxide thin film transistors have the advantages of low leakage current. Integrating low-temperature polysilicon thin film transistors and oxide thin film transistors on a display substrate to form a low-temperature polycrystalline oxide (LTPS+Oxide) display substrate can take advantage of the advantages of both, achieve low-frequency driving, reduce power consumption, and improve display quality.

[0086] In some examples, such as Figure 2 As shown, the pixel circuit can be electrically connected to the first scan line GL1, the second scan line GL2, the data line DL, the first power line PL1, the second power line PL2, the light emission control line EML, the first initial signal line INIT1, the second initial signal line INIT2, the third initial signal line INIT3, the first reset control line RST1 and the second reset control line RST2. The first power line PL1 can be configured to provide a constant first voltage signal VDD to the pixel circuit, the second power line PL2 can be configured to provide a constant second voltage signal VSS to the pixel circuit, and the first voltage signal VDD is greater than the second voltage signal VSS. The first scan line GL1 can be configured to provide a first scan signal SCAN1 to the pixel circuit. The second scan line GL2 can be configured to provide a second scan signal SCAN2 to the pixel circuit. The data line DL can be configured to provide a data signal to the pixel circuit. The light emission control line EML can be configured to provide a light emission control signal EM to the pixel circuit. The first reset control line RST1 can be configured to provide a first reset control signal RESET1 to the pixel circuit. The second reset control line can be configured to provide a second reset control signal RESET2 to the pixel circuit.

[0087] In some examples, such as Figure 2As shown, the gate of the third transistor T3 is electrically connected to the first node N1, the first electrode of the third transistor T3 is electrically connected to the second node N2, and the second electrode of the third transistor T3 is electrically connected to the third node N3. The gate of the fourth transistor T4 is electrically connected to the first scan line GL1, the first electrode of the fourth transistor T4 is electrically connected to the data line DL, and the second electrode of the fourth transistor T4 is electrically connected to the second node N2. The gate of the second transistor T2 is electrically connected to the second scan line GL2, the first electrode of the second transistor T2 is electrically connected to the third node N3, and the second electrode of the second transistor T2 is electrically connected to the first node N1. The gate of the fifth transistor T5 is electrically connected to the light emission control line EML, the first electrode of the fifth transistor T5 is electrically connected to the first power line PL1, and the second electrode of the fifth transistor T5 is electrically connected to the second node N2. The gate of the sixth transistor T6 is electrically connected to the light emission control line EML, the first electrode of the sixth transistor T6 is electrically connected to the third node N3, and the second electrode of the sixth transistor T6 is electrically connected to the fourth node N4. The gate of the first transistor T1 is electrically connected to the first reset control line RST1, the first electrode of the first transistor T1 is electrically connected to the first initial signal line INIT1, and the second electrode of the first transistor T1 is electrically connected to the third node N3. The first transistor T1 can be configured to reset the third node N3. The gate of the seventh transistor T7 is electrically connected to the second reset control line RST2, the first electrode of the seventh transistor T7 is electrically connected to the second initial signal line INIT2, and the second electrode of the seventh transistor T7 is electrically connected to the fourth node N4. The seventh transistor T7 can be configured to reset the fourth node N4. The gate of the eighth transistor T8 is electrically connected to the second reset control line RST2, the first electrode of the eighth transistor T8 is electrically connected to the third initial signal line INIT3, and the second electrode of the eighth transistor T8 is electrically connected to the second node N2. The eighth transistor T8 can be configured to reset the second node N2. The first electrode of the storage capacitor Cst is electrically connected to the first node N1, and the second electrode of the storage capacitor Cst is electrically connected to the first power line PL1.

[0088] In this example, the first node N1 is the connection point of the storage capacitor Cst, the second transistor T2 and the third transistor T3, the second node N2 is the connection point of the fifth transistor T5, the fourth transistor T4, the eighth transistor T8 and the third transistor T3, the third node N3 is the connection point of the first transistor T1, the third transistor T3, the second transistor T2 and the sixth transistor T6, and the fourth node N4 is the connection point of the sixth transistor T6, the seventh transistor T7 and the light emitting element EL.

[0089] Figure 3 for Figure 2 The working timing diagram of the pixel circuit provided is as follows. Figure 3 right Figure 2The working process of the pixel circuit shown in FIG. 1 is described as follows. The first transistor T1, the third transistor T3 to the eighth transistor T8 of the pixel circuit are P-type transistors, and the second transistor T2 is an N-type transistor.

[0090] In some examples, such as Figure 2 and Figure 3 As shown, in a frame display time period, the working process of the pixel circuit may at least include: a first stage S11, a second stage S12, a third stage S13 and a fourth stage S14.

[0091] The first stage S11 is called the first reset stage. The second reset control signal RESET2 provided by the second reset control line RST2 is a low-level signal, which turns on the seventh transistor T7 and the eighth transistor T8; the second scan signal SCAN2 provided by the second scan line GL2 is a high-level signal, which turns on the second transistor T2. The eighth transistor T8 is turned on, so that the third initial signal provided by the third initial signal line INIT3 is provided to the second node N2. The seventh transistor T7 is turned on, so that the second initial signal provided by the second initial signal line INIT2 is provided to the fourth node N4, and the fourth node N4 is initialized. The first scan signal SCAN1 provided by the first scan line GL1 is a high-level signal, the first reset control signal RESET1 provided by the first reset control line RST1 is a high-level signal, and the light control signal EM provided by the light control line EML is a high-level signal, so that the fourth transistor T4, the first transistor T1, the fifth transistor T5 and the sixth transistor T6 are turned off. In this stage, the light-emitting element EL does not emit light.

[0092] The second stage S12 is called the second reset stage. The first reset control signal RESET1 provided by the first reset control line RST1 is a low-level signal, and the first transistor T1 is turned on; the second scan signal SCAN2 provided by the second scan line GL2 is a high-level signal, and the second transistor T2 is turned on. The first transistor T1 and the second transistor T2 are turned on, so that the first initial signal line provided by the first initial signal line INIT1 is provided to the first node N1, and the first node N1 is initialized. The second reset control signal RESET2 provided by the second reset control line RST2 is a high-level signal, the first scan signal SCAN1 provided by the first scan line GL1 is a high-level signal, and the light-emitting control signal EM provided by the light-emitting control line EML is a high-level signal, so that the seventh transistor T7, the eighth transistor T8, the fourth transistor T4, the fifth transistor T5 and the sixth transistor T6 are turned off. In this stage, the light-emitting element EL does not emit light.

[0093] The third stage S13 is called the data writing stage or the threshold compensation stage. The first scanning signal SCAN1 provided by the first scanning line GL1 is a low level signal, and the fourth transistor T4 is turned on; the second scanning signal SCAN2 provided by the second scanning line GL2 is a high level signal, and the second transistor T2 is turned on. In this stage, the first electrode of the storage capacitor Cst is at a low level, and the third transistor T3 is turned on. The second transistor T2, the fourth transistor T4 and the third transistor T3 are turned on, so that the data voltage Vdata output by the data line DL is provided to the first node N1 through the second node N2, the turned-on third transistor T3, the third node N3 and the turned-on second transistor T2, and the difference between the data voltage Vdata output by the data line DL and the threshold voltage of the third transistor T3 is charged into the storage capacitor Cst, and the voltage of the first electrode (i.e., the first node N1) of the storage capacitor Cst is Vdata-|Vth|, where Vdata is the data voltage output by the data line DL, and Vth is the threshold voltage of the third transistor T3. The first reset control signal RESET1 provided by the first reset control line RST1 is a high level signal, the second reset control signal RESET2 provided by the second reset control line RST2 is a high level signal, and the light control signal EM provided by the light control line EML is a high level signal, so that the first transistor T1, the seventh transistor T7, the eighth transistor T8, the fifth transistor T5 and the sixth transistor T6 are disconnected.

[0094] In the fourth stage S14, the light control signal EM provided by the light control line EML can be switched from a high level signal to a low level signal, so that the fifth transistor T5 and the sixth transistor T6 are turned on. The second scan signal SCAN2 provided by the second scan line GL2 is a low level signal, so that the second transistor T2 is turned off. The first scan signal SCAN1 provided by the first scan line GL1, the first reset control signal RESET1 provided by the first reset control line RST1, and the second reset control signal RESET2 provided by the second reset control line RST2 are high level signals, so that the fourth transistor T4, the first transistor T1, the seventh transistor T7, and the eighth transistor T8 are turned off. The first voltage signal VDD output by the first power line PL1 provides a driving voltage to the anode of the light emitting element EL through the turned-on fifth transistor T5, the third transistor T3, and the sixth transistor T6, so as to drive the light emitting element EL to emit light.

[0095] During the driving process of the pixel circuit, the driving current flowing through the third transistor T3 is determined by the voltage difference between its gate and the first electrode. Since the voltage of the first node N1 is Vdata-|Vth|, the driving current of the third transistor T3 is:

[0096] I=K×(Vgs-Vth) 2 =K×[(VDD-Vdata+|Vth|)-Vth]2 =K×[VDD-Vdata] 2 ;

[0097] Among them, I is the driving current flowing through the third transistor T3, that is, the driving current driving the light-emitting element, K is a constant, Vgs is the voltage difference between the gate and the first electrode of the third transistor T3, Vth is the threshold voltage of the third transistor T3, Vdata is the data voltage output by the data line DL, and VDD is the first voltage signal output by the first power line PL1.

[0098] It can be seen from the above formula that the current flowing through the light-emitting element has nothing to do with the threshold voltage of the third transistor T3. Therefore, the pixel circuit of this embodiment can better compensate for the threshold voltage of the third transistor T3. Moreover, the pixel circuit provided by this embodiment can improve the poor display caused by low frequency and improve the display effect of the light-emitting element.

[0099] Figure 4 It is a partial cross-sectional schematic diagram of a display area of ​​at least one embodiment of the utility model. Figure 4 In the example, the structure of a sub-pixel in the display area is used as an example to illustrate. Figure 2 The pixel circuit shown includes a low-temperature polysilicon thin film transistor and an oxide thin film transistor as an example for explanation.

[0100] In some examples, such as Figure 4 As shown, in the direction perpendicular to the display panel, the display area of ​​the display panel may include at least: a substrate 10, and a circuit structure layer 12, a light emitting structure layer 13, a packaging structure layer 14 and a touch structure layer 15 sequentially arranged on the substrate 10. Among them, the display structure layer may include at least a circuit structure layer 12 and a light emitting structure layer 13. The circuit structure layer 12 may include at least: a pixel circuit of a plurality of sub-pixels, and the pixel circuit of each sub-pixel may include a plurality of transistors and at least one capacitor. The light emitting structure layer 13 may include at least: a light emitting element of a plurality of sub-pixels.

[0101] In some examples, Figure 4 In the figure, each sub-pixel includes a first-type transistor 21, a second-type transistor 22, and a capacitor 23. The first-type transistor 21 may be a low-temperature polysilicon thin-film transistor, and the second-type transistor 22 may be an oxide thin-film transistor.

[0102] In some examples, the circuit structure layer 12 of the display area may include: a first semiconductor layer, a first gate metal layer, a second gate metal layer, a second semiconductor layer, a third gate metal layer, a first source-drain metal layer, and a second source-drain metal layer, which are arranged on the substrate 10. A first gate insulating (GI) layer 101 may be arranged between the first semiconductor layer and the first gate metal layer, a second gate insulating layer 102 may be arranged between the first gate metal layer and the second gate metal layer; a third gate insulating layer 103 may be arranged between the second gate metal layer and the second semiconductor layer; a fourth gate insulating layer 104 may be arranged between the second semiconductor layer and the third gate metal layer; an interlayer insulating layer 105 may be arranged between the third gate metal layer and the first source-drain metal layer; a passivation (PVX) layer 106 and a first flat (PLN) layer 107 may be arranged between the first source-drain metal layer and the second source-drain metal layer, and the first flat layer 107 may be located on a side of the passivation layer 106 away from the substrate 10; and a second flat layer 108 may be arranged on a side of the second source-drain metal layer away from the substrate 10. Among them, the first gate insulating layer 101, the second gate insulating layer 102, the third gate insulating layer 103, the fourth gate insulating layer 104, the interlayer insulating layer 105 and the passivation layer 106 can be inorganic insulating layers, and the first flat layer 107 and the second flat layer 108 can be organic insulating layers. However, this embodiment is not limited to this. In other examples, a buffer layer can also be provided on the side of the first semiconductor layer close to the substrate, and the buffer layer can prevent harmful substances in the substrate from invading the interior of the display panel, and can also increase the adhesion of the film layer in the display panel on the substrate. In other examples, a bottom shielding metal layer (BSM, Bottom Shielding Metal) can also be provided on the side of the buffer layer close to the substrate, and the bottom shielding metal layer can be configured to at least partially cover the active layer of the transistor of the pixel circuit to avoid external light from affecting the performance of the transistor. In other examples, the passivation layer can be omitted between the first source and drain metal layer and the second source and drain metal layer, and only the first flat layer can be provided between the first source and drain metal layer and the second source and drain metal layer.

[0103] In some examples, such as Figure 4As shown, the first semiconductor layer in the display area may include at least: a first active layer 210 of a first type transistor 21. The first active layer 210 of the first type transistor 21 may include: a first region 2101, a second region 2102, and a channel region 2100 located between the first region 2101 and the second region 2102. The first gate metal layer may include at least: a first gate 213 of the first type transistor 21, and a first plate 231 of the capacitor 23. The orthographic projection of the first gate 213 of the first type transistor 21 on the substrate 10 may cover the orthographic projection of the channel region 2100 of the first active layer 210 on the substrate 10. The second gate metal layer may include at least: a second plate 232 of the capacitor 23, and a third gate 224 of the second type transistor 22. The orthographic projections of the second plate 232 and the first plate 231 of the capacitor 23 on the substrate 10 may at least partially overlap, for example, the two may overlap. The second semiconductor layer may include at least: a second active layer 220 of the second type transistor 22. The third gate metal layer may include at least: a second gate 223 of the second type transistor 22. The orthographic projection of the second gate 223 of the second type transistor 22 on the substrate 10 may partially overlap with the orthographic projection of the second active layer 220 on the substrate 10. The orthographic projection of the third gate 224 of the second type transistor 22 on the substrate 10 may partially overlap with the orthographic projection of the second active layer 220 on the substrate 10. The third gate 224 may be the bottom gate of the second type transistor 22, and the second gate 223 may be the top gate of the second type transistor 22.

[0104] In some examples, such as Figure 4As shown, the first source-drain metal layer in the display area may at least include: a first source 211 and a first drain 212 of the first type transistor 21, a second source 221 and a second drain 222 of the second type transistor 22. The interlayer insulating layer 105 may be provided with a plurality of pixel vias (for example, including a first pixel via, a second pixel via, a third pixel via, and a fourth pixel via) in the display area. The interlayer insulating layer 105, the fourth gate insulating layer 104, the third gate insulating layer 103, the second gate insulating layer 102, and the first gate insulating layer 101 in the first pixel via may be removed to expose at least a portion of the surface of the first region 2101 of the first active layer 210; the interlayer insulating layer 105, the third gate insulating layer 104, the third gate insulating layer 103, the second gate insulating layer 102, and the first gate insulating layer 101 in the second pixel via may be removed to expose at least a portion of the surface of the second region 2102 of the first active layer 210. The interlayer insulating layer 105, the fourth gate insulating layer 104 and the third gate insulating layer 103 in the third pixel via hole and the fourth pixel via hole can be removed to expose at least part of the surface of the two ends of the second active layer 220. The first source 211 of the first type transistor 21 can be electrically connected to the first area 2101 of the first active layer 210 through the first pixel via hole, and the first drain 212 can be electrically connected to the second area 2102 of the first active layer 210 through the second pixel via hole. The second source 221 of the second type transistor 22 can be electrically connected to one end of the second active layer 220 through the third pixel via hole, and the second drain 222 of the second type transistor 22 can be electrically connected to the other end of the second active layer 220 through the fourth pixel via hole. The second source-drain metal layer can include at least: a first switching electrode 241. The first switching electrode 241 can be electrically connected to the first drain 212 of the first type transistor 21 of the pixel circuit through the fifth pixel via hole opened in the passivation layer 106 and the first flat layer 107. In this example, the electrical connection between the pixel circuit and the light emitting element can be achieved through the first switching electrode 241 .

[0105] In some examples, the gate lines of the display area may be located in the first gate metal layer and the third gate metal layer, the data lines of the display area may be located in the second source-drain metal layer, and the high potential power lines of the display area may be located in the second source-drain metal layer. This embodiment is not limited to this.

[0106] In some examples, such as Figure 4As shown, the light emitting structure layer 13 may include: a pixel definition layer 134 and a plurality of light emitting elements. For example, each light emitting element may include: a stacked first electrode 131, an organic light emitting layer 132 and a second electrode 133. The first electrode 131 of the light emitting element may be an anode, and the first electrode 131 may be disposed on the second flat layer 108, and electrically connected to the first transfer electrode 241 through the sixth pixel via hole provided in the second flat layer 108. The pixel definition layer 134 is disposed on the first electrode 131 and the second flat layer 108, and the pixel definition layer 134 may be provided with a plurality of pixel openings, and one pixel opening may expose at least part of the surface of a corresponding first electrode 131. At least part of the organic light emitting layer 132 may be disposed in one pixel opening and connected to the corresponding first electrode 131. The second electrode 133 may be disposed on the organic light emitting layer 132 and connected to the organic light emitting layer 132. The organic light emitting layer 132 may emit light of corresponding colors under the drive of the first electrode 131 and the second electrode 133.

[0107] In some examples, the organic light-emitting layer 132 of the light-emitting element may include a light-emitting layer (EML, Emitting Layer), and at least one of the following film layers: a hole injection layer (HIL, Hole Injection Layer), a hole transport layer (HTL, Hole Transport Layer), a hole blocking layer (HBL, Hole Block Layer), an electron blocking layer (EBL, Electron Block Layer), an electron injection layer (EIL, Electron Injection Layer), and an electron transport layer (ETL, Electron Transport Layer). Under the voltage drive of the first electrode 131 and the second electrode 133, the light-emitting characteristics of the organic material can be used to emit light according to the required grayscale.

[0108] In some examples, the light-emitting layers of light-emitting elements of different colors may be different. For example, the red light-emitting element includes a red light-emitting layer, the green light-emitting element includes a green light-emitting layer, and the blue light-emitting element includes a blue light-emitting layer. In order to reduce the process difficulty and improve the yield, the hole injection layer and the hole transport layer on one side of the light-emitting layer may use a common layer, and the electron injection layer and the electron transport layer on the other side of the light-emitting layer may use a common layer. In some examples, any one or more of the hole injection layer, the hole transport layer, the electron injection layer, and the electron transport layer can be made by a single process (a single evaporation process or a single inkjet printing process), and isolation is achieved by means of a surface step difference of the formed film layer or by surface treatment. For example, any one or more of the hole injection layer, the hole transport layer, the electron injection layer, and the electron transport layer corresponding to adjacent sub-pixels may be isolated. In some examples, the organic light-emitting layer can be formed by evaporation using a fine metal mask (FMM, FineMetal Mask) or an open mask (Open Mask), or by inkjet technology.

[0109] In some examples, such as Figure 4 As shown, the encapsulation structure layer 14 may include a first encapsulation layer 141, a second encapsulation layer 142, and a third encapsulation layer 143 stacked. Among them, the first encapsulation layer 141 and the third encapsulation layer 143 may be made of inorganic materials, such as silicon nitride, silicon oxide, silicon oxynitride, etc. The inorganic material has high density and can prevent the intrusion of water, oxygen, etc. The second encapsulation layer 142 may be arranged between the first encapsulation layer 141 and the third encapsulation layer 143 to ensure that external water vapor cannot enter the light-emitting element. The second encapsulation layer 142 may be made of organic materials, for example, it may be a polymer material containing a desiccant or a polymer material that can block water vapor, or it may be a polymer resin, etc. to flatten the surface of the display panel, and it may relieve the stress of the first encapsulation layer 141 and the third encapsulation layer 143, and it may also include a desiccant and other water-absorbing materials to absorb water, oxygen, and other substances that invade the interior. However, this embodiment is not limited to this. For example, the encapsulation structure layer may adopt a five-layer stacked structure of inorganic / organic / inorganic / organic / inorganic.

[0110] In some examples, the touch structure layer of the display area may include: a plurality of first touch electrodes, a plurality of first connecting portions, a plurality of second touch electrodes, and a plurality of second connecting portions. The plurality of first touch electrodes may be arranged in the same layer, and adjacent first touch electrodes may be connected via the first connecting portions. The plurality of second touch electrodes may be arranged in the same layer, and adjacent second touch electrodes may be connected via the second connecting portions.

[0111] In some examples, such as Figure 4As shown, in a direction perpendicular to the display panel, the touch structure layer 15 of the display area may include: a touch buffer layer (TBL) 150, a first touch conductive layer 151, a touch interlayer insulating layer (TLD) 153, a second touch conductive layer 152, and a protective layer 154 arranged in sequence. Among them, the touch buffer layer 150 and the touch interlayer insulating layer 153 may be inorganic insulating layers, and the protective layer 154 may be an organic insulating layer. For example, the first touch conductive layer 151 may include a plurality of first touch electrodes, a plurality of second touch electrodes, and a plurality of first connecting portions. The first touch electrodes and the first connecting portions may be an integral structure connected to each other. The second touch conductive layer 152 may include a plurality of second connecting portions. The second connecting portion may be interconnected with the adjacent second touch electrodes through a via provided in the touch interlayer insulating layer. However, this embodiment is not limited to this. In other examples, the first touch conductive layer may include: a plurality of first touch electrodes, a plurality of second touch electrodes and a plurality of second connecting portions, and the second touch electrodes and the second connecting portions may be an integrated structure connected to each other; the second touch conductive layer may include a plurality of first connecting portions, and the first connecting portions may be connected to adjacent first touch electrodes through vias provided in the touch interlayer insulating layer. In some examples, the first touch electrode may be a drive (Tx) electrode, and the second touch electrode may be a sense (Rx) electrode. Alternatively, the first touch electrode may be a sense (Rx) electrode, and the second touch electrode may be a drive (Tx) electrode. This embodiment is not limited to this.

[0112] In some examples, the first touch electrode and the second touch electrode may have a rhombus shape, such as a regular rhombus, a horizontally long rhombus, or a vertically long rhombus. In other examples, the first touch electrode and the second touch electrode may have any one or more of a triangle, a square, a trapezoid, a parallelogram, a pentagon, a hexagon, and other polygons, which is not limited in the embodiments of the present utility model.

[0113] In some examples, the first touch electrode and the second touch electrode may be in the form of transparent conductive electrodes. In other examples, the first touch electrode and the second touch electrode may be in the form of a metal grid, the metal grid may be formed by interweaving a plurality of metal wires, the metal grid may include a plurality of grid patterns, and the grid pattern may be a polygon formed by a plurality of metal wires. The first touch electrode and the second touch electrode in the metal grid format have the advantages of low resistance, small thickness, and fast response speed.

[0114] Figure 5 Schematic diagram of the gate drive circuit of at least one embodiment of the present utility model. In some examples, such as Figure 5As shown, a plurality of gate drive circuits may be provided in the peripheral frame area, and the plurality of gate drive circuits may include: a first scan drive circuit 31, a second scan drive circuit 32, a light emitting drive circuit 33, a first reset drive circuit 34, and a second reset drive circuit 35. The first scan drive circuit 31 may be configured to provide a first scan signal to a plurality of rows of pixel circuits in the display area AA. The second scan drive circuit 32 may be configured to provide a second scan signal to a plurality of rows of pixel circuits in the display area AA. The light emitting drive circuit 33 may be configured to provide a light emitting control signal to a plurality of rows of pixel circuits in the display area AA. The first reset drive circuit 34 may be configured to provide a first reset control signal to a plurality of rows of pixel circuits in the display area AA. The second reset drive circuit 35 may be configured to provide a second reset control signal to a plurality of rows of pixel circuits in the display area AA.

[0115] In some examples, the display area AA includes M rows of pixel circuits as an example, where M is a positive integer. The multiple rows of pixel circuits in the display area can be marked as the 1st row to the Mth row in sequence along the direction close to the first frame area B1. The multiple gate drive circuits may include: a first group of gate drive circuits located in the second frame area and a second group of gate drive circuits located in the third frame area. The first group of gate drive circuits may include the following three gate drive circuits: a light-emitting drive circuit 33, a first reset drive circuit 34, and a second reset drive circuit 35. For example, in the second frame area, the second reset drive circuit 35, the light-emitting drive circuit 33, and the first reset drive circuit 34 may be sequentially arranged in the first direction X along the direction close to the display area AA. The second group of gate drive circuits may include the following two gate drive circuits: a first scan drive circuit 31 and a second scan drive circuit 32. For example, in the third frame area, the first scan drive circuit 31 and the second scan drive circuit 32 may be sequentially arranged in the first direction X along the direction away from the display area AA. In other examples, three gate drive circuits may be arranged in the peripheral frame area, one gate drive circuit may be arranged in the second frame area, and two gate drive circuits may be arranged in the third frame area. This embodiment is not limited to this.

[0116] In some examples, the first scan driving circuit 31 may include a plurality of cascaded first scan driving units (e.g., including GP(1) to GP(M)). Each level of the first scan driving unit may be configured to provide a first scan signal to a row of pixel circuits in the display area AA. For example, the first level of the first scan driving unit GP(1) may be configured to provide a first scan signal to the first row of pixel circuits in the display area AA; the Mth level of the first scan driving unit GP(M) may be configured to provide a first scan signal to the Mth row of pixel circuits in the display area AA.

[0117] In some examples, the second scan driving circuit 32 may include a plurality of cascaded second scan driving units (e.g., GN(1) to GN(M / 2)). Each level of the second scan driving unit may be configured to provide a second scan signal to two adjacent rows of pixel circuits in the display area AA. For example, the first level second scan driving unit GN(1) may be configured to provide a second scan signal to the 1st row and the 2nd row of pixel circuits in the display area AA; the M / 2 level second scan driving unit GP(M / 2) may be configured to provide a second scan signal to the M-1th row and the Mth row of pixel circuits in the display area AA.

[0118] In some examples, the light-emitting driving circuit 33 may include a plurality of cascaded light-emitting driving units (e.g., EM(1) to EM(M / 2)). Each level of light-emitting driving units may be configured to provide a light-emitting control signal to two adjacent rows of pixel circuits in the display area AA. For example, the first level of light-emitting driving unit EM(1) may be configured to provide a light-emitting control signal to the 1st row and the 2nd row of pixel circuits in the display area AA; the M / 2th level of light-emitting driving unit EM(M / 2) may be configured to provide a light-emitting control signal to the M-1th row and the Mth row of pixel circuits in the display area AA.

[0119] In some examples, the first reset driving circuit 34 may include a plurality of cascaded first reset driving units (e.g., RP(1) to RP(M / 2)). Each level of the first reset driving unit may be configured to provide a first reset control signal to two adjacent rows of pixel circuits in the display area AA. For example, the first level first reset driving unit RP(1) may be configured to provide a first reset control signal to the 1st and 2nd rows of pixel circuits in the display area AA; the M / 2th level first reset driving unit RP(M / 2) may be configured to provide a first reset control signal to the M-1th and Mth rows of pixel circuits in the display area AA.

[0120] In some examples, the second reset driving circuit 35 may include a plurality of cascaded second reset driving units (e.g., RH(1) to RH(M / 2)). Each level of the second reset driving unit may be configured to provide a second reset control signal to two adjacent rows of pixel circuits in the display area AA. For example, the first level second reset driving unit RH(1) may be configured to provide a second reset control signal to the 1st and 2nd rows of pixel circuits in the display area AA; the M / 2nd level second reset driving unit RH(M / 2) may be configured to provide a second reset control signal to the M-1th and Mth rows of pixel circuits in the display area AA.

[0121] In some examples, such as Figure 1As shown, the first frame area B1 may include: a bending area B12, a fan-out area B13, a first signal access area B14, and a second signal access area B15, which are sequentially arranged along a direction away from the display area AA. The bending area B12 may be connected to the peripheral frame area B2 and the fan-out area B13, and is located on a side of the peripheral frame area B2 away from the display area AA. The fan-out area B13 may be located on a side of the bending area B12 away from the display area AA. The first signal access area B14 may be located on a side of the fan-out area B13 away from the display area AA. The second signal access area B15 may be located on a side of the first signal access area B14 away from the display area AA.

[0122] In some examples, the peripheral frame area B2 may be provided with a first peripheral power line, a second peripheral power line, and a plurality of gate drive circuits. The first peripheral power line may be connected to a first power line electrically connected to a pixel circuit of a plurality of sub-pixels PX of the display area AA, and configured to transmit a first voltage signal. The second peripheral power line may extend from the left side along the edge of the display panel to the second frame area, and from the right side along the edge of the display panel to the third frame area. The second peripheral power line may be connected to the second power line, and configured to transmit a second voltage signal to a plurality of sub-pixels of the display area AA. A plurality of gate drive circuits may be arranged in the second frame area B21 and the third frame area B22.

[0123] In some examples, the peripheral frame area B2 between the display area AA and the first frame area B1 may be provided with a plurality of multiplexing circuits. For example, a multiplexing circuit may be connected to a multiplexing data line and a plurality of data lines, and configured to provide a data signal transmitted by a multiplexing data line to a plurality of data lines.

[0124] In some examples, the peripheral border area B2 may also be provided with a plurality of peripheral control lines. The plurality of peripheral control lines may include: a first group of peripheral control lines and a second group of peripheral control lines. For example, the first group of peripheral control lines may include: a plurality of peripheral drive control lines that provide drive control signals (such as start signals, clock signals, power signals, etc.) to the first group of gate drive circuits in the second border area B21; the second group of peripheral control lines may include: a plurality of peripheral drive control lines that provide drive control signals to the second group of gate drive circuits in the third border area B22. In other examples, each group of peripheral control lines may include: a plurality of peripheral drive control lines and a plurality of peripheral multiplexing control lines, and the plurality of peripheral multiplexing control lines may be connected to a plurality of multiplexing circuits, configured to provide a multiplexing control signal to the multiplexing circuit, so that the multiplexing circuit provides the data signal transmitted by the multiplexed data line to the plurality of data lines under the control of the multiplexing control signal.

[0125] In some examples, the peripheral frame area B2 may also be provided with a plurality of peripheral touch lines. The plurality of peripheral touch lines may be located in the touch structure layer and connected to the first touch electrode or the second touch electrode of the display area AA.

[0126] In some examples, the bending area B12 can be configured to bend the fan-out area B13, the first signal access area B14, and the second signal access area B15 to the back of the display area AA. The bending area B12 can be provided with a plurality of bending connection lines to connect the peripheral frame area B2 and the routing lines transmitting the same signal in the fan-out area B13. The plurality of bending connection lines in the bending area B12 can be of the same layer structure, for example, they can all be located in the second source and drain metal layer.

[0127] Figure 6 It is a partial plan view of the first frame area of ​​at least one embodiment of the utility model. Figure 6 The partial structures of the bending area B12, the fan-out area B13, the first signal access area B14 and the second signal access area B15 are illustrated. Figure 6 The data bending connection lines, touch bending connection lines, control bending connection lines, control connection lines and data fan-out lines in the first border area are generally illustrated, and the control signal lines are only illustrated using several lines as an example. This example does not limit the number of multiple lines in the first border area.

[0128] In some examples, such as Figure 6 As shown, the plurality of bending connection lines in the bending area B12 may include: first power bending connection lines 53a, 53b, 53c and 53d, second power bending connection lines 54a and 54b, a first group of data bending connection lines 51a, a second group of data bending connection lines 51b, a group of control bending connection lines 52, a first group of touch bending connection lines 55a and a second group of touch bending connection lines 55b. The second power bending connection line 54a, the first group of data bending connection lines 51a, the first power bending connection line 53a, the first group of touch bending connection lines 55a, the first power bending connection line 53b, a group of control bending connection lines 52, the first power bending connection line 53c, the second group of touch bending connection lines 55b, the first power bending connection line 53d, the first group of data bending connection lines 51b and the second power bending connection line 54b may be arranged in sequence along the first direction X.

[0129] In some examples, such as Figure 6As shown, the fan-out area B13 may be provided with at least a first power lead-out line 43, second power lead-out lines 44a and 44b, multiple data fan-out lines (for example, including a first group of data fan-out lines 41a and a second group of data fan-out lines 41b), multiple control connection lines (for example, including a first group of control connection lines 56a and a second group of control connection lines 56b), multiple control signal lines (for example, including a first group of control signal lines 42a and a second group of control signal lines 42b), and multiple touch lead-out lines (for example, including a first group of touch lead-out lines 45a and a second group of touch lead-out lines 45b).

[0130] In some examples, such as Figure 6 As shown, the first power lead 43 can be connected to the first peripheral power line of the peripheral frame area through the first power connection lines 53a, 53b, 53c and 53d of the bending area B12. The first power lead 43 can be located at the first source and drain metal layer, or can be located at the second source and drain metal layer, or can adopt a double-layer routing structure arranged at the first source and drain metal layer and the second source and drain metal layer. The first power lead 43 can at least include: a first main body extending along the first direction X, four connecting parts extending along the second direction Y to the side close to the bending area B12, a first power extension part extending along the third direction F3, and a second power extension part extending along the fourth direction F4. The third direction F3 can intersect with both the first direction X and the second direction Y, the fourth direction F4 can intersect with both the first direction X and the second direction Y, and the third direction F3 can intersect with the fourth direction F4. The four connecting parts of the first power lead 43 can be electrically connected to the four first power connection lines 53a, 53b, 53c and 53d of the bending area B12 in a one-to-one correspondence. The first power extension portion may bypass the first signal access area B14 from the left to extend to connect with the contact pad in the second signal access area B15, and the second power extension portion may bypass the first signal access area B14 from the right to extend to connect with the contact pad in the second signal access area B15.

[0131] In some examples, such as Figure 6As shown, the second power lead 44a can be connected to the second peripheral power line of the peripheral frame area through the second power connection line 54a of the bending area B12, and the second power lead 44b can be connected to the second peripheral power line of the peripheral frame area through the second power connection line 54b of the bending area B12. The second power lead 44a can be located on the side of the first power lead 43 in the opposite direction of the first direction X, and the second power lead 44b can be located on the side of the first power lead 43 along the first direction X. The second power lead 44a and 44b can both be located in the first source and drain metal layer, or can both be located in the second source and drain metal layer, or can adopt a double-layer routing structure arranged in the first source and drain metal layer and the second source and drain metal layer. The second power lead 44a can bypass the first signal access area B14 from the left to extend to connect to the contact pad in the second signal access area B15. The second power lead 44b can bypass the first signal access area B14 from the right to extend to connect to the contact pad in the second signal access area B15.

[0132] In some examples, such as Figure 6 As shown, the plurality of data fan-out lines of the fan-out area B13 may extend substantially along the second direction Y toward the first signal access area B14. The plurality of data fan-out lines may include a first group of data fan-out lines 41a and a second group of data fan-out lines 41b. The first group of data fan-out lines 41a may be located between the second power lead-out lines 44a and the first group of control connection lines 56a, and the second group of data fan-out lines 41b may be located between the second power lead-out lines 44b and the second group of control connection lines 56b. Multiple data fan-out lines in the first group of data fan-out lines 41a can be connected to multiple multiplexed data lines in the peripheral frame area through multiple data bend connection lines in the first group of data bend connection lines 51a in the bend area B12, so as to provide data signals to multiple data lines through multiple multiplexing circuits; multiple data fan-out lines in the second group of data fan-out lines 41b can be connected to multiple multiplexed data lines in the peripheral frame area through multiple data bend connection lines in the second group of data bend connection lines 51b in the bend area B12, so as to provide data signals to multiple data lines through multiple multiplexing circuits. For example, the first group of data fan-out lines 41a can be configured to provide data signals to sub-pixels in the left half area of ​​the display area, and the second group of data fan-out lines 41b can be configured to provide data signals to sub-pixels in the right half area of ​​the display area. The number of data fan-out lines in the first group of data fan-out lines 41a can be the same as the number of data fan-out lines in the second group of data fan-out lines 41b. For example, the plurality of data fan-out lines may be located in the first gate metal layer, or may be located in the second gate metal layer, or may be alternately arranged in the first gate metal layer and the second gate metal layer.

[0133] In some examples, such as Figure 6As shown, the plurality of control connection lines may include: a first group of control connection lines 56a and a second group of control connection lines 56b. The first group of control connection lines 56a and the second group of control connection lines 56b may be located between the first group of data fan-out lines 41a and the second group of data fan-out lines 41b. The plurality of control connection lines may be connected to the plurality of peripheral control lines in the peripheral border area through a group of control bending connection lines 52 in the bending area B12. The first group of control connection lines 56a and the second group of control connection lines 56b may be arranged in a shape of an inverted Y. For example, the plurality of control connection lines may be located in the first gate metal layer, or may be located in the second gate metal layer, or may adopt a double-layer wiring structure arranged in the first gate metal layer and the second gate metal layer.

[0134] In some examples, such as Figure 6 As shown, the multiple control signal lines of the fan-out area B13 may include: a first group of control signal lines 42a and a second group of control signal lines 42b. The first group of control signal lines 42a may be connected to the first group of control connection lines 56a, and the second group of control signal lines 42b may be connected to the second group of control connection lines 56b. The orthographic projection of the first group of control signal lines 42a on the substrate overlaps with the orthographic projection of the first group of data fan-out lines 41a on the substrate, and the orthographic projection of the second group of control signal lines 42b on the substrate overlaps with the orthographic projection of the second group of data fan-out lines 41b on the substrate. The first group of control signal lines 42a and the second group of control signal lines 42b may be located on the side of the first main body of the first power lead 43 away from the bending area B12.

[0135] In some examples, each group of control signal lines may include at least a plurality of drive control lines, and the drive control lines may be configured to provide drive control signals to the gate drive circuit. The plurality of drive control lines included in the first group of control signal lines may be configured to provide drive control signals to the first group of gate drive circuits located in the second border area, and the plurality of drive control lines included in the second group of control signal lines may be configured to provide drive control signals to the second group of gate drive circuits located in the third border area. In other examples, each group of control signal lines may include at least: a plurality of drive control lines and a plurality of multiplexing control lines, and the plurality of multiplexing control lines may be configured to provide multiplexing control signals to a plurality of multiplexing circuits in the peripheral border area.

[0136] In some examples, the first group of control signal lines 42a can bypass the first signal access area B14 from the left to extend to connect with the contact pads in the second signal access area B15; the second group of control signal lines 42b can bypass the first signal access area B14 from the right to extend to connect with the contact pads in the second signal access area B15.

[0137] In some examples, the fan-out area B13 may also be provided with a first electrostatic discharge circuit 46 and a second electrostatic discharge circuit 47. The first group of control signal lines 42a may be connected to the first electrostatic discharge circuit 46, and the second group of control signal lines 42b may be connected to the second electrostatic discharge circuit 47. The first electrostatic discharge circuit 46 may be configured to provide an electrostatic discharge path for the first group of control signal lines 42a, and the second electrostatic discharge circuit 47 may be configured to provide an electrostatic discharge path for the second group of control signal lines 42b. The first electrostatic discharge circuit 46 may be located between the first group of data fan-out lines 41a and the first group of touch lead-out lines 45a, and the second electrostatic discharge circuit 47 may be located between the second group of data fan-out lines 41b and the second group of touch lead-out lines 45b.

[0138] In some examples, such as Figure 6 As shown, the plurality of touch lead lines of the fan-out area B12 may extend approximately along the second direction Y toward the first signal access area B14. The plurality of touch lead lines may include a first group of touch lead lines 45a and a second group of touch lead lines 45b. The first group of touch lead lines 45a may be connected to the peripheral touch lines of the peripheral frame area through the first group of touch bending connection lines 55a of the bending area B12, and the second group of touch lead lines 45b may be connected to the peripheral touch lines of the peripheral frame area through the second group of touch bending connection lines 55b of the bending area B12. The setting shape of the first group of touch lead lines 45a and the second group of touch lead lines 45b may be approximately Y-shaped. For example, the plurality of touch lead lines may be located in the first touch conductive layer or the second touch conductive layer of the touch structure layer. The orthographic projection of the first group of touch lead wires 45a on the substrate may overlap with the orthographic projection of the first group of control connection wires 56a on the substrate, and the orthographic projection of the second group of touch lead wires 45b on the substrate may overlap with the orthographic projection of the second group of control connection wires 56b on the substrate. The first group of touch lead wires 45a and the second group of touch lead wires 45b may be located between the first group of control signal wires 42a and the second group of control signal wires 42b.

[0139] In some examples, such as Figure 6 As shown, the first signal access area B14 can be configured to set a driver chip (IC, Integrated Circuit), for example, the driver chip set in the first signal access area B14 can be a display driver chip or a touch and display driver integrated chip (TDDI, Touch and Display Driver Integration). The first signal access area B14 can also be called a driver chip setting area. The driver chip can be configured to generate a data signal required for driving a sub-pixel and provide the data signal to the data line of the display area.

[0140] In some examples, the first signal access area B14 may be provided with a plurality of first contact pads, and the plurality of first contact pads may include: a first group of first contact pads 61 and a second group of first contact pads 62. The second group of first contact pads 62 may be located on a side of the first group of first contact pads 61 away from the bending area B12. The plurality of first contact pads in the first group of first contact pads 61 may be arranged in at least one row along the first direction X. A plurality of data fan-out lines may be connected to the plurality of first contact pads in the first group of first contact pads 61 in the first signal access area B14 to be configured to receive data signals from a driver chip; a plurality of touch lead-out lines may be connected to the plurality of first contact pads in the first group of first contact pads 61 in the first signal access area B14 to be configured to receive touch signals from a driver chip. The plurality of first contact pads in the second group of first contact pads 62 may be arranged in a row along the first direction X.

[0141] In some examples, the second signal access area B15 may be provided with a plurality of second contact pads 63. The plurality of second contact pads 63 may be configured to bind a flexible printed circuit (FPC) so that a plurality of signal lines (for example, including a plurality of control signal lines, a first power lead line and a second power lead line, etc.) are connected to an external control device through the plurality of second contact pads 63. The second signal access area B15 may also be referred to as a circuit binding area. The second group of first contact pads 62 in the first signal access area B14 may be electrically connected to the plurality of second contact pads 63 in the second signal access area B15 through a plurality of pin connection lines 64.

[0142] In some examples, since the number of gate drive circuits provided in the peripheral border area is odd (for example, five), the number of gate drive circuits provided in the second border area and the third border area cannot be evenly distributed (for example, three gate drive circuits are provided in the second border area, and two gate drive circuits are provided in the third border area), which will cause uneven overlap of the routing of the two groups of data fan-out lines and the two groups of control signal lines in the first border area. For example, the number of control signal lines in the first group of control signal lines that overlap with the first group of data fan-out lines is greater than the number of control signal lines in the second group of control signal lines that overlap with the second group of data fan-out lines, thereby making the parasitic capacitance generated between the multiple data fan-out lines and the overlapping routing lines inconsistent, which can easily cause display defects such as low grayscale dark stripes. In this example, the parasitic capacitance between the data fan-out lines and the overlapping control signal lines is reduced by increasing the distance between the data fan-out lines and the overlapping control signal lines, thereby improving the display defects such as low grayscale dark stripes caused by the uneven overlap of the data fan-out lines and the control signal lines.

[0143] Figure 7 for Figure 6 A partial enlarged schematic diagram of the middle area S1. Fig. 8A for Figure 7 An example of a local cross-section along the Q1-Q1' direction. Figure 8B for Figure 7 The following is an example of a partial cross-section diagram along the Q2-Q2' direction. The position relationship between the first group of data fan-out lines 41a and the first group of control signal lines 42a is used as an example for explanation.

[0144] In some examples, such as Figure 7 As shown, the first group of data fan-out lines 41a may include: a plurality of first data fan-out lines 411a located in the first gate metal layer and a plurality of second data fan-out lines 412a located in the second gate metal layer. The plurality of first data fan-out lines 411a and the plurality of second data fan-out lines 412a may be arranged one by one, and the orthographic projections of the first data fan-out lines 411a and the second data fan-out lines 412a on the substrate do not overlap. In other words, the spacing distance between the orthographic projections of the first data fan-out lines 411a and the adjacent second data fan-out lines 412a on the substrate may be greater than 0.

[0145] In some examples, such as Figure 6 and Figure 7 As shown, each control signal line in the first group of control signal lines 42a may include: a first control line segment 421a, a second control line segment 422a, and a third control line segment 423a. One end of the first control line segment 421a is connected to one end of the second control line segment 422a, and the other end of the first control line segment 421a is connected to one end of the third control line segment 423a. The other end of the third control line segment 423a may be connected to the control connection line 56. The other end of the second control line segment 422a may extend to connect to the contact pad of the second signal access area. The orthographic projection of the first control line segment 421a on the substrate overlaps with the orthographic projection of the first group of data fan-out lines 41a on the substrate, and the orthographic projections of the second control line segment 422a and the third control line segment 423a on the substrate do not overlap with the orthographic projection of the first group of data fan-out lines 41a on the substrate.

[0146] In some examples, the second control line segment 422a and the third control line segment 423a may be in the same layer structure, for example, they may be located in the first source-drain metal layer. The first control line segment 421a and the second control line segment 422a and the third control line segment 423a may be in different layer structures, for example, the first control line segment 421a may be located on the side of the second control line segment 422a and the third control line segment 423a away from the substrate, for example, the first control line segment 421a may be located in the second source-drain metal layer. However, this embodiment is not limited to this. In other examples, the first control line segment, the second control line segment and the third control line segment of the control signal line may be an integrated structure connected to each other, for example, they may be located in the second source-drain metal layer.

[0147] In some examples, such as Fig. 8A and Figure 8B As shown, the first data fan-out line 411a is located in the first gate metal layer, the second data fan-out line 412a is located in the second gate metal layer, and the first control line segment 421a of the control signal line in the first group of control signal lines 42a is located in the second source-drain metal layer. At least one organic insulating layer (including the first flat layer 107) and multiple inorganic insulating layers (for example, at least including the passivation layer 106, the interlayer insulating layer 105 and the second gate insulating layer 102) are arranged between the first control line segment 421a of the control signal line and the first data fan-out line 411a where the control signal line overlaps; at least one organic insulating layer (including the first flat layer 107) and multiple inorganic insulating layers (for example, at least including the passivation layer 106 and the interlayer insulating layer 105) are arranged between the first control line segment 421a of the control signal line and the second data fan-out line 412a where the control signal line overlaps.

[0148] In some examples, such as Figure 6 As shown, each control signal line in the second group of control signal lines 42b may include: a first control line segment 421b, a second control line segment 422b, and a third control line segment 423b. The orthographic projection of the first control line segment 421b on the substrate overlaps with the orthographic projection of the second group of data fan-out lines 41b on the substrate, and the orthographic projections of the second control line segment 422b and the third control line segment 423b on the substrate do not overlap with the orthographic projections of the second group of data fan-out lines 41b on the substrate. The film layer setting of the second group of data fan-out lines 41b is the same as the film layer setting of the first group of data fan-out lines 41a, and the film layer setting of the second group of control signal lines 42b is the same as the film layer setting of the second group of control signal lines 42a, so it will not be repeated here.

[0149] In this example, an organic insulating layer is set between the data fan-out line and the first control line segment of the overlapping control signal line, so that the data fan-out line and the first control line segment of the control signal line can be separated by a large distance, thereby reducing the parasitic capacitance between the data fan-out line and the control signal line, and improving display defects such as low grayscale dark stripes caused by uneven overlap of the data fan-out line and the control signal line.

[0150] Fig. 9 Another partial cross-sectional schematic diagram of a display panel according to at least one embodiment of the present invention. Fig. 10A for Figure 7 Another example of a local cross-section along the Q1-Q1' direction. Fig. 10B for Figure 7 Another example of a local cross-section along the Q2-Q2' direction.

[0151] In some examples, such as Fig. 9As shown, in the direction perpendicular to the display panel, the circuit structure layer 12 of the display area may include: a first semiconductor layer, a first gate metal layer, a second gate metal layer, a second semiconductor layer, a third gate metal layer, a first source-drain metal layer, a second source-drain metal layer and a third source-drain metal layer arranged on the substrate 10. A passivation layer 106 and a first flat layer 107 may be arranged between the first source-drain metal layer and the second source-drain metal layer, a second flat layer 108 may be arranged between the second source-drain metal layer and the third source-drain metal layer, and a third flat layer 109 may be arranged on the side of the third source-drain metal layer away from the substrate 10. The first flat layer 107, the second flat layer 108 and the third flat layer 109 may be organic insulating layers. The third source-drain metal layer may include at least: a second transfer electrode 242. The second transfer electrode 242 may be connected to the first transfer electrode 241 located in the second source-drain metal layer through a via hole opened in the second flat layer 108. In this example, the electrical connection between the pixel circuit and the light-emitting element may be realized through the second transfer electrode 242 and the first transfer electrode 241. For the remaining film layer structures of the display panel of this example, please refer to Figure 4 The description of the embodiment shown is therefore not repeated here.

[0152] In some examples, such as Fig. 10A and Fig. 10B As shown, the first data fan-out line 411a is located in the first gate metal layer, the second data fan-out line 412a is located in the second gate metal layer, and the first control line segment 421a of the control signal line in the first group of control signal lines 42a can be located in the third source-drain metal layer. At least two organic insulating layers (including the first flat layer 107 and the second flat layer 108) and multiple inorganic insulating layers (for example, at least including the passivation layer 106, the interlayer insulating layer 105 and the second gate insulating layer 102) are arranged between the first control line segment 421a of the control signal line and the first data fan-out line 411a where there is an overlap; at least two organic insulating layers (including the first flat layer 107 and the second flat layer 108) and multiple inorganic insulating layers (for example, at least including the passivation layer 106 and the interlayer insulating layer 105) are arranged between the first control line segment 421a of the control signal line and the second data fan-out line 412a where there is an overlap. The rest of the description of the first border area of ​​this example can refer to the description of the aforementioned embodiment, so it is not repeated here.

[0153] In this example, two organic insulating layers are set between the data fan-out line and the first control line segment of the overlapping control signal line, so that the data fan-out line and the first control line segment of the control signal line can be further apart, and the parasitic capacitance between the data fan-out line and the control signal line can be better isolated, thereby improving display defects such as low grayscale dark stripes caused by uneven overlap of the data fan-out line and the control signal line.

[0154] This example increases the distance between the data fan-out line and the first control line segment of the overlapping control signal line by adjusting the film layer where the first control line segment of the control signal line is located (for example, the first control line segment is located in the second source-drain metal layer or the third source-drain metal layer), and reduces the parasitic capacitance between the data fan-out line and the overlapping control signal line, thereby effectively improving display defects such as low grayscale dark stripes caused by uneven overlap of the data fan-out line and the control signal line.

[0155] Fig.11 Another partial plan view of the first border area of ​​at least one embodiment of the utility model. Fig.11 The partial structures of the bending area B12, the fan-out area B13, the first signal access area B14 and the second signal access area B15 are illustrated. Fig.11 The data bending connection lines, touch bending connection lines, control bending connection lines, control connection lines and data fan-out lines in the first border area are generally illustrated, and the control signal lines are only illustrated using several lines as an example. This example does not limit the number of multiple lines in the first border area.

[0156] In some examples, such as Fig.11 As shown, the number of control signal lines in the first group of control signal lines 42a is greater than the number of control signal lines in the second group of control signal lines 42b. Each control signal line in the first group of control signal lines 42a can be an integral structure located in the same film layer, and each control signal line in the second group of control signal lines 42b can be an integral structure located in the same film layer. For example, multiple control signal lines can be located in the first source-drain metal layer. However, this embodiment is not limited to this. In other examples, multiple control signal lines can be located in the second source-drain metal layer or the third source-drain metal layer.

[0157] Fig. 12A for Fig.11 A partial enlarged schematic diagram of the middle area S2. Fig. 12B for Fig. 12A A partial schematic diagram of the first set of data fan-out lines in FIG. Fig. 12A and Fig. 12B As shown, the first group of data fan-out lines 41a may include: a plurality of first data fan-out lines 411a located in the first gate metal layer and a plurality of second data fan-out lines 412a located in the second gate metal layer. The plurality of first data fan-out lines 411a and the plurality of second data fan-out lines 412a may be arranged one by one, and the orthographic projections of the first data fan-out lines 411a and the second data fan-out lines 412a on the substrate do not overlap. In other words, the spacing distance between the orthographic projections of the first data fan-out lines 411a and the adjacent second data fan-out lines 412a on the substrate may be greater than 0.

[0158] In some examples, such as Fig. 12A and Fig. 12B As shown, each data fan-out line in the first group of data fan-out lines 41a may include: a first sub-segment 41-1, a third sub-segment 41-3 and a fourth sub-segment 41-4. One end of the first sub-segment 41-1 is connected to one end of the third sub-segment 41-3, and the other end of the first sub-segment 41-1 is connected to one end of the fourth sub-segment 41-4. The other end of the third sub-segment 41-3 may extend to one side of the bending area, and the other end of the fourth sub-segment 41-4 may extend to one side of the first signal access area. The orthographic projection of the first sub-segment 41-1 on the substrate overlaps with the orthographic projection of the first group of control signal lines 42a on the substrate, and the orthographic projections of the third sub-segment 41-3 and the fourth sub-segment 41-4 on the substrate may not overlap with the orthographic projection of the first group of control signal lines 42a on the substrate. The first sub-segment 41-1, the third sub-segment 41-3 and the fourth sub-segment 41-4 of the data fan-out line in the first group of data fan-out lines 41a may be an integrated structure connected to each other. The orthographic projection of the data fan-out line in the first group of data fan-out lines 41a on the substrate may be a straight line, and the orthographic projection of the first sub-segment 41-1 on the substrate may be roughly a long strip. The line width of the first sub-segment 41-1 of the data fan-out line may be the first line width W1, and the line widths of the third sub-segment 41-3 and the fourth sub-segment 41-4 may be the same as the line width of the first sub-segment 41-1.

[0159] In some examples, such as Fig. 12A and Fig. 12B As shown, each control signal line in the first group of control signal lines 42a may include: a first control line segment 421a, and the orthographic projection of the first control line segment 421a on the substrate overlaps with the orthographic projection of the first sub-line segment 41-1 of the data fan-out line in the first group of data fan-out lines 41a on the substrate. For example, the first control line segment 421a of each control signal line may have a third line width K1.

[0160] In some examples, each data fan-out line in the first group of data fan-out lines 41a may have a first overlapping area with the orthographic projection of the first group of control signal lines 42a on the substrate. The first overlapping area may be the sum of the overlapping areas of one data fan-out line in the first group of data fan-out lines 41a and all control signal lines in the first group of control signal lines 42a. The first overlapping areas corresponding to the plurality of data fan-out lines in the first group of data fan-out lines 41a may be substantially the same.

[0161] Fig.13A for Fig.11 A partial enlarged schematic diagram of the middle area S3. Fig. 13B for Fig.13A A partial schematic diagram of the second set of data fan-out lines in FIG. Fig.13A and Fig. 13BAs shown, the second group of data fan-out lines 41b may include: a plurality of first data fan-out lines 411b located in the first gate metal layer and a plurality of second data fan-out lines 412b located in the second gate metal layer. The plurality of first data fan-out lines 411b and the plurality of second data fan-out lines 412b may be arranged one by one, and the orthographic projections of the first data fan-out lines 411b and the second data fan-out lines 412b on the substrate do not overlap. In other words, the spacing distance between the orthographic projections of the first data fan-out lines 411b and the adjacent second data fan-out lines 412b on the substrate may be greater than 0.

[0162] In some examples, such as Fig.13A and Fig. 13B As shown, each data fan-out line in the second group of data fan-out lines 41b may include: a second sub-segment 41-2, a fifth sub-segment 41-5, and a sixth sub-segment 41-6. One end of the second sub-segment 41-2 is connected to one end of the fifth sub-segment 41-5, and the other end of the second sub-segment 41-2 is connected to one end of the sixth sub-segment 41-6. The other end of the fifth sub-segment 41-5 may extend to one side of the bending area, and the other end of the sixth sub-segment 41-6 may extend to one side of the first signal access area. The orthographic projection of the second sub-segment 41-2 on the substrate overlaps with the orthographic projection of the second group of control signal lines 42b on the substrate, and the orthographic projections of the fifth sub-segment 41-5 and the sixth sub-segment 41-6 on the substrate may not overlap with the orthographic projection of the second group of control signal lines 42b on the substrate. The second sub-segment 41 - 2 , the fifth sub-segment 41 - 5 and the sixth sub-segment 41 - 6 of the data fan-out lines in the second group of data fan-out lines 41 b may be an integrated structure connected to each other.

[0163] In some examples, such as Fig.13A and Fig. 13B As shown, each control signal line in the second group of control signal lines 42b may include: a first control line segment 421b, and the orthographic projection of the first control line segment 421b on the substrate overlaps with the orthographic projection of the second sub-line segment 41-2 of the data fan-out line in the second group of data fan-out lines 41b on the substrate. For example, the first control line segment 421b of each control signal line may have a fourth line width K2. For example, the fourth line width K2 may be substantially the same as the third line width K1.

[0164] In some examples, each data fan-out line in the second group of data fan-out lines 41b may have a second overlapping area with the orthographic projection of the second group of control signal lines 42b on the substrate. The second overlapping area may be the sum of the overlapping areas of a data fan-out line in the second group of data fan-out lines 41b and all control signal lines in the second group of control signal lines 42b. The second overlapping areas corresponding to the plurality of data fan-out lines in the second group of data fan-out lines 41b may be substantially the same.

[0165] In some examples, the orthographic projection of the second sub-segment 41-2 of the data fan-out line in the second group of data fan-out lines 41b on the substrate may be a serpentine routing. Since the number of control signal lines in the second group of control signal lines is less than the number of control signal lines in the first group of control signal lines, the number of control signal lines overlapped by each data fan-out line in the second group of data fan-out lines 41b is less than the number of control signal lines overlapped by each data fan-out line in the first group of data fan-out lines 41a. In this example, by setting the second sub-segment 41-2 of the data fan-out line in the second group of data fan-out lines 41b as a serpentine routing, the second overlapping area corresponding to the data fan-out line in the second group of data fan-out lines can be increased, so that the second overlapping area can be substantially the same as the first overlapping area corresponding to the data fan-out line in the first group of data fan-out lines, so as to reduce the difference in parasitic capacitance between the two groups of data fan-out lines and the overlapping routing. In some examples, the ratio of the first overlapping area to the second overlapping area can range from 0.9 to 1.1, for example, it can be approximately 1.0.

[0166] In some examples, the orthographic projection of the fifth sub-segment 41-5 or the sixth sub-segment 41-6 of at least one data fan-out line in the second group of data fan-out lines 41b on the substrate may be a serpentine line. For example, the orthographic projection of the fifth sub-segment 41-5 or the sixth sub-segment 41-6 of the plurality of data fan-out lines close to the touch lead-out line in the second group of data fan-out lines 41b on the substrate may be a serpentine line. In some examples, since the number of pixel circuits electrically connected to each of the plurality of data lines in the display area is different, the loads of the plurality of data lines are different. For example, the display area is circular or elliptical, and the display area can be divided into a middle area and left and right side areas along the first direction X. The number of pixel circuits connected to the data lines in the middle area is greater than the number of pixel circuits connected to the data lines in the left area or the right area, so that the load of the data lines in the middle area is different from the load of the data lines in the left and right side areas. In order to ensure the display effect of the display area, it is necessary to perform load compensation on the data lines to ensure that the loads of the plurality of data lines in the display area are roughly the same. In this example, the load compensation for the data line in the display area is adjusted by setting the orthographic projection of the fifth sub-segment 41 - 5 or the sixth sub-segment 41 - 6 of at least one data fan-out line on the substrate to be a serpentine line.

[0167] In some examples, the line widths of the fifth and sixth sub-segments 41-5 and 41-6 in the second group of data fan-out lines 41b using a straight line design may be substantially the same as the first line width of the first sub-segment 41-1 of the data fan-out lines in the first group of data fan-out lines 41a.

[0168] This example utilizes a serpentine routing design for some segments of the second group of data fan-out lines, which can not only increase the overlapping area between the second group of data fan-out lines and the second group of control signal lines, thereby reducing the parasitic capacitance difference between the two groups of data fan-out lines and the overlapping control signal lines, but also perform load compensation on the data lines in the display area to ensure that the loads of multiple data lines in the display area are roughly the same.

[0169] Fig.14A for Fig.11 Another partial enlarged schematic diagram of the middle area S3. Fig. 14B for Fig.14A A partial schematic diagram of the second set of data fan-out lines in FIG. Fig.14A and Fig. 14B As shown, each data fan-out line in the second group of data fan-out lines 41b may include: a second sub-segment 41-2, a fifth sub-segment 41-5, and a sixth sub-segment 41-6. One end of the second sub-segment 41-2 is connected to one end of the fifth sub-segment 41-5, and the other end of the second sub-segment 41-2 is connected to one end of the sixth sub-segment 41-6. The other end of the fifth sub-segment 41-5 may extend to one side of the bending area, and the other end of the sixth sub-segment 41-6 may extend to one side of the first signal access area. The orthographic projection of the second sub-segment 41-2 on the substrate overlaps with the orthographic projection of the second group of control signal lines 42b on the substrate, and the orthographic projections of the fifth sub-segment 41-5 and the sixth sub-segment 41-6 on the substrate may not overlap with the orthographic projection of the second group of control signal lines 42b on the substrate. The second sub-segment 41 - 2 , the fifth sub-segment 41 - 5 and the sixth sub-segment 41 - 6 of the data fan-out lines in the second group of data fan-out lines 41 b may be an integrated structure connected to each other.

[0170] In some examples, such as Fig.14A and Fig. 14B As shown, the orthographic projection of the second sub-segment 41-2 of the data fan-out line of the second group of data fan-out lines 41b on the substrate can be a straight line. The second sub-segment 41-2 can have a second line width W2. The second line width W2 can be the maximum line width of the second sub-segment 41-2. The second line width W2 of the second sub-segment 41-2 can be greater than the first line width W1 of the first sub-segment 41-1 of the data fan-out line of the first group of data fan-out lines 41a.

[0171] In some examples, the orthographic projections of the fifth sub-segment 41-5 and the sixth sub-segment 41-6 of the data fan-out line of the second group of data fan-out lines 41b on the substrate may both be straight line lines. The line widths of the fifth sub-segment 41-5 and the sixth sub-segment 41-6 may be substantially the same, for example, both the same as the first line width W1. For example, the ratio of the second line width W2 to the first line width W1 may be greater than 1 and less than 2, for example, may be approximately 1.7. In some examples, the first line width W1 may be approximately 5.1 micrometers (um), and the second line width W2 may be approximately 8.7um.

[0172] In this example, by increasing the line width of the second sub-segment of the second group of data fan-out lines, the overlapping area between the second group of data fan-out lines and the second group of control signal lines can be increased, so that the second overlapping area corresponding to the data fan-out lines in the second group of data fan-out lines can be roughly the same as the first overlapping area corresponding to the data fan-out lines in the first group of data fan-out lines, and the parasitic capacitance between the second group of data fan-out lines and the overlapping wiring is increased, so that the parasitic capacitance between the two groups of data fan-out lines and the overlapping wiring is roughly the same, thereby improving display defects such as low grayscale dark stripes caused by uneven overlap of the data fan-out lines and the control signal lines.

[0173] Fig.15 for Fig.11 Another partial enlarged schematic diagram of the middle area S3. In some examples, such as Fig.15 As shown, the line shape and line width of the data fan-out lines in the second group of data fan-out lines 41b may be the same as the line shape and line width of the data fan-out lines in the first group of data fan-out lines 41a. The fourth line width K2 of the first control line segment 421b of at least one control signal line in the second group of control signal lines may be greater than the third line width K1 of the first control line segment 421a of the control signal line in the first group of control signal lines. For example, the fourth line width K2 of the first control line segment 421b of each control signal line in the second group of control signal lines may be the same and greater than the third line width K1.

[0174] In this example, by increasing the line width of the first control line segment of the second group of control signal lines, the overlapping area between the second group of data fan-out lines and the second group of control signal lines can be increased, so that the second overlapping area corresponding to the data fan-out lines in the second group of data fan-out lines can be roughly the same as the first overlapping area corresponding to the data fan-out lines in the first group of data fan-out lines, thereby increasing the parasitic capacitance between the second group of data fan-out lines and the overlapping control signal lines, so that the parasitic capacitance between the two groups of data fan-out lines and the overlapping control signal lines is roughly the same, thereby improving display defects such as low grayscale dark stripes caused by uneven overlap of the data fan-out lines and the control signal lines.

[0175] In some examples, FIG. 13A to FIG. 15In the illustrated embodiment, in order to ensure that the parasitic capacitance between the data fan-out lines in the first group of data fan-out lines and the first group of control signal lines is approximately the same as the parasitic capacitance between the data fan-out lines in the second group of data fan-out lines and the second group of control signal lines, the parasitic capacitance between the data fan-out lines in the second group of data fan-out lines and the second group of control signal lines can be increased by increasing the overlapping area between the data fan-out lines in the second group of data fan-out lines and the second group of control signal lines.

[0176] In other examples, the parasitic capacitance between the data fan-out lines in the first group of data fan-out lines and the first group of control signal lines can be reduced by reducing the overlapping area between the data fan-out lines in the first group of data fan-out lines and the first group of control signal lines, thereby ensuring that the parasitic capacitance between the data fan-out lines in the first group of data fan-out lines and the first group of control signal lines can be approximately the same as the parasitic capacitance between the data fan-out lines in the second group of data fan-out lines and the second group of control signal lines.

[0177] Fig.16A for Fig.11 Another partial enlarged schematic diagram of the middle area S2. Fig. 16B for Fig.16A A partial schematic diagram of the first set of data fan-out lines. Fig.17A for Fig.11 Another partial enlarged schematic diagram of the middle area S3. Fig. 17B for Fig.17A A partial schematic diagram of the second set of data fan-out lines.

[0178] In some examples, such as Fig.16A and Fig. 16B As shown, each data fan-out line in the first group of data fan-out lines 41a may include a third sub-segment 41-3, a first sub-segment 41-1, and a fourth sub-segment 41-4 connected in sequence. The orthographic projection of the first sub-segment 41-1 on the substrate may overlap with the orthographic projection of the first group of control signal lines 42a on the substrate. The orthographic projection of the data fan-out lines in the first group of data fan-out lines 41a on the substrate may be a straight line. The minimum line width of the first sub-segment 41-1 may be smaller than the line widths of the third sub-segment 41-3 and the fourth sub-segment 41-4. The line widths of the third sub-segment 41-3 and the fourth sub-segment 41-4 may be substantially the same.

[0179] In some examples, such as Fig.17A and Fig. 17BAs shown, each data fan-out line in the second group of data fan-out lines 41b may include a fifth sub-segment 41-5, a second sub-segment 41-2, and a sixth sub-segment 41-6 connected in sequence. The orthographic projection of the second sub-segment 41-2 on the substrate may overlap with the orthographic projection of the second group of control signal lines 42b on the substrate. The orthographic projection of the data fan-out lines in the second group of data fan-out lines 41b on the substrate may be a straight line. The line widths of the second sub-segment 41-2, the fifth sub-segment 41-5, and the sixth sub-segment 41-6 may be substantially the same. The line width of the second sub-segment 41-2 may be greater than the line width of the first sub-segment 41-1.

[0180] In this example, by reducing the line width of the first sub-segment of the first group of data fan-out lines, the overlapping area between the first group of data fan-out lines and the first group of control signal lines can be reduced, so that the first overlapping area corresponding to the data fan-out lines in the first group of data fan-out lines and the second overlapping area corresponding to the data fan-out lines in the second group of data fan-out lines can be roughly the same, and the parasitic capacitance between the first group of data fan-out lines and the overlapping wirings is reduced, so that the parasitic capacitance between the two groups of data fan-out lines and the overlapping wirings is roughly the same, thereby improving display defects such as low grayscale dark stripes caused by uneven overlap of the data fan-out lines and the control signal lines.

[0181] In other examples, by reducing the line width of the first control line segment of the first group of control signal lines, the overlapping area between the first group of data fan-out lines and the first group of control signal lines can be reduced, so that the first overlapping area corresponding to the data fan-out lines in the first group of data fan-out lines and the second overlapping area corresponding to the data fan-out lines in the second group of data fan-out lines can be approximately the same, thereby reducing the parasitic capacitance between the first group of data fan-out lines and the overlapping control signal lines, and making the parasitic capacitance between the two groups of data fan-out lines and the overlapping control signal lines approximately the same, thereby improving display defects such as low grayscale dark stripes caused by uneven overlap of the data fan-out lines and the control signal lines.

[0182] In other examples, the first overlap area corresponding to the data fan-out lines in the first group of data fan-out lines can be made substantially the same as the second overlap area corresponding to the data fan-out lines in the second group of data fan-out lines by reducing the line width of the first sub-line segment of the first group of data fan-out lines and increasing the line width of the second sub-line segment of the second group of data fan-out lines. Alternatively, in other examples, the first overlap area corresponding to the data fan-out lines in the first group of data fan-out lines can be made substantially the same as the second overlap area corresponding to the data fan-out lines in the second group of data fan-out lines by reducing the line width of the first control line segment of the first group of control signal lines and increasing the line width of the first control line segment of the second group of control signal lines. Alternatively, in other examples, the first overlapping area corresponding to the data fan-out lines in the first group of data fan-out lines and the second overlapping area corresponding to the data fan-out lines in the second group of data fan-out lines can be made approximately the same by reducing the line width of the first sub-line segment of the first group of data fan-out lines and increasing the line width of the second sub-line segment of the second group of data fan-out lines, and reducing the line width of the first control line segment of the first group of control signal lines and increasing the line width of the first control line segment of the second group of control signal lines.

[0183] Figures 11 to 17B In the illustrated embodiment, the parasitic capacitance between the data fan-out lines and the overlapping control signal lines is adjusted by adjusting the overlapping area between the data fan-out lines and the overlapping control signal lines, so that the parasitic capacitance between the first group of data fan-out lines and the second group of data fan-out lines and the overlapping control signal lines are substantially the same, thereby effectively improving display defects such as low grayscale dark stripes caused by uneven overlap of the data fan-out lines and the control signal lines.

[0184] In other examples, the parasitic capacitance between the data fan-out line and the overlapping control signal line can be adjusted by adjusting the film layer where the first control line segment of the control signal line is located and adjusting the overlapping area between the data fan-out line and the overlapping control signal line, so that the parasitic capacitance between the first group of data fan-out lines and the second group of data fan-out lines and the overlapping control signal line is approximately the same, thereby effectively improving the display defects such as low grayscale dark stripes caused by the uneven overlap of the data fan-out line and the control signal line. For example, the first control line segment of the plurality of control signal lines can be located in the second source-drain metal layer or the third source-drain metal layer; the line width of the second sub-line segment of the second group of data fan-out lines can be greater than the line width of the first sub-line segment of the first group of data fan-out lines; or, the line width of the first control line segment of the second group of control signal lines can be greater than the line width of the first control line segment of the first group of control signal lines.

[0185] This embodiment also provides a display panel, including: a substrate, a plurality of sub-pixels, a plurality of data lines, a plurality of data fan-out lines, and a plurality of control signal lines. The substrate includes: a display area, and a first frame area located on one side of the display area. The plurality of sub-pixels and the plurality of data lines are located in the display area, and the plurality of data lines are connected to the plurality of sub-pixels and are configured to provide data signals to the plurality of sub-pixels. The plurality of data fan-out lines and the plurality of control signal lines are located in the first frame area, and the plurality of data fan-out lines are configured to provide data signals to the plurality of data lines. The plurality of data fan-out lines include: a first group of data fan-out lines and a second group of data fan-out lines, and the plurality of control signal lines include: a first group of control signal lines and a second group of control signal lines. The number of control signal lines in the first group of control signal lines is greater than the number of control signal lines in the second group of control signal lines. Each data fan-out line in the first group of data fan-out lines overlaps with the first group of control signal lines in their orthographic projection on the substrate, and each data fan-out line in the second group of data fan-out lines overlaps with the second group of control signal lines in their orthographic projection on the substrate. Each data fan-out line in the first group of data fan-out lines has a first overlapping area with the first group of control signal lines in an orthographic projection on the substrate, and each data fan-out line in the second group of data fan-out lines has a second overlapping area with the second group of control signal lines in an orthographic projection on the substrate, and the ratio of the first overlapping area to the second overlapping area ranges from 0.9 to 1.1.

[0186] This embodiment adjusts the parasitic capacitance between the data fan-out lines and the overlapping control signal lines by adjusting the overlapping area between each data fan-out line and multiple control signal lines, so that the parasitic capacitance between the two groups of data fan-out lines and the control signal lines is roughly the same, thereby optimizing display defects such as low grayscale dark stripes caused by uneven overlapping of the data fan-out lines and the control signal lines transmitting AC signals.

[0187] In some exemplary embodiments, each data fan-out line in the first group of data fan-out lines includes: a first sub-line segment that overlaps with the orthographic projection of the first group of control signal lines on the substrate. Each data fan-out line in the second group of data fan-out lines includes: a second sub-line segment that overlaps with the orthographic projection of the second group of control signal lines on the substrate. The line width of the first sub-line segment may be smaller than the line width of the second sub-line segment. In this example, by increasing the line width of the second sub-line segment of the second group of data fan-out lines, the overlapping area between the second group of data fan-out lines and the second group of control signal lines can be increased, so that the second overlapping area corresponding to the data fan-out lines in the second group of data fan-out lines can be substantially the same as the first overlapping area corresponding to the data fan-out lines in the first group of data fan-out lines, and the parasitic capacitance between the second group of data fan-out lines and the overlapping wiring is increased, so that the parasitic capacitance between the two groups of data fan-out lines and the overlapping wiring is substantially the same, thereby improving the display defects such as low grayscale dark stripes caused by the uneven overlap of the data fan-out lines and the control signal lines.

[0188] In some exemplary embodiments, each data fan-out line in the first group of data fan-out lines includes: a first sub-line segment that overlaps with the orthographic projection of the first group of control signal lines on the substrate; each data fan-out line in the second group of data fan-out lines includes: a second sub-line segment that overlaps with the orthographic projection of the second group of control signal lines on the substrate; the orthographic projection of the first sub-line segment on the substrate may be a straight line, and the orthographic projection of the second sub-line segment on the substrate may be a serpentine line. In this example, by designing a serpentine line for some segments of the second group of data fan-out lines, the overlapping area between the second group of data fan-out lines and the second group of control signal lines can be increased, thereby reducing the parasitic capacitance difference between the two groups of data fan-out lines and the overlapping control signal lines.

[0189] In some exemplary embodiments, each control signal line in the first group of control signal lines includes: a first control line segment that overlaps with the orthographic projection of the first group of data fan-out lines on the substrate; each control signal line in the second group of control signal lines includes: a first control line segment that overlaps with the orthographic projection of the second group of data fan-out lines on the substrate. The line width of the first control line segment of at least one control signal line in the second group of control signal lines may be greater than the line width of the first control line segment of the control signal line in the first group of control signal lines. In this example, by increasing the line width of the first control line segment of the second group of control signal lines, the overlapping area between the second group of data fan-out lines and the second group of control signal lines can be increased, so that the parasitic capacitance between the two groups of data fan-out lines and the overlapping control signal lines is approximately the same, thereby improving display defects such as low grayscale dark stripes caused by uneven overlap of the data fan-out lines and the control signal lines.

[0190] The rest of the description about the display panel of this example can refer to the description of the aforementioned embodiment, so it will not be repeated here.

[0191] Fig.18 Schematic diagram of a display device according to at least one embodiment of the present invention. Fig.18 As shown, this embodiment provides a display device 91, including a display panel 910 of the above embodiment. In some examples, the display panel 910 may be an OLED display panel, such as an OLED display panel with an integrated touch structure. The display device 91 may be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, or a navigator, or may be a product or component with both touch and display functions.

[0192] In some examples, the display device 91 may be a wearable display device, for example, it may be worn on a human body in some manner. For example, the display device 91 may be a smart watch, a smart bracelet, etc. However, this embodiment is not limited to this.

[0193] The drawings in the utility model only relate to the structures involved in the utility model, and other structures can refer to the usual design. In the absence of conflict, the embodiments of the utility model, that is, the features in the embodiments, can be combined with each other to obtain new embodiments. It should be understood by those skilled in the art that the technical solution of the utility model can be modified or replaced by equivalents without departing from the spirit and scope of the technical solution of the utility model, and should be included in the scope of the claims of the utility model.

[0194] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", or "some examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the utility model. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification and the features of the different embodiments or examples, without contradiction.

[0195] Although the embodiments of the present invention have been shown and described above, it can be understood that the above embodiments are exemplary and cannot be understood as limitations of the present invention. Ordinary technicians in the field can change, modify, replace and modify the above embodiments within the scope of the present invention.

Claims

1. A display panel, characterized in that: include: A substrate, comprising: a display area, and a first frame area located on one side of the display area; A plurality of sub-pixels and a plurality of data lines are located in the display area, the plurality of data lines are connected to the plurality of sub-pixels and are configured to provide data signals to the plurality of sub-pixels; A plurality of data fan-out lines and a plurality of control signal lines are located in the first border area, the plurality of data fan-out lines are configured to provide data signals to the plurality of data lines; the plurality of data fan-out lines include: a first group of data fan-out lines and a second group of data fan-out lines, the plurality of control signal lines include: a first group of control signal lines and a second group of control signal lines; the number of control signal lines in the first group of control signal lines is greater than the number of control signal lines in the second group of control signal lines; Each data fan-out line in the first group of data fan-out lines overlaps with an orthographic projection of the first group of control signal lines on the substrate, and each data fan-out line in the second group of data fan-out lines overlaps with an orthographic projection of the second group of control signal lines on the substrate; At least one organic insulating layer is disposed between the data fan-out line and the control signal line whose orthographic projection overlaps with the substrate.

2. The display panel according to claim 1, characterized in that: The control signal line includes: a first control line segment, the orthographic projection of the first control line segment on the substrate overlaps with the orthographic projection of the first group of data fan-out lines or the second group of data fan-out lines on the substrate, the first control line segment is located on a side of the first group of data fan-out lines or the second group of data fan-out lines away from the substrate, and the first control line segment intersects with an extension direction of the multiple data fan-out lines.

3. The display panel according to claim 2, characterized in that: In a direction perpendicular to the display panel, the display panel at least comprises: a first gate metal layer, a second gate metal layer, a first source-drain metal layer, and a second source-drain metal layer arranged in a direction away from the substrate; at least a first planarization layer is arranged between the first source-drain metal layer and the second source-drain metal layer; The plurality of data fan-out lines are located in at least one of the first gate metal layer and the second gate metal layer, and the first control line segments of the plurality of control signal lines are located in the second source-drain metal layer.

4. The display panel according to claim 2, characterized in that: In a direction perpendicular to the display panel, the display panel at least comprises: a first gate metal layer, a second gate metal layer, a first source-drain metal layer, a second source-drain metal layer, and a third source-drain metal layer arranged in a direction away from the substrate; at least a first flat layer is arranged between the first source-drain metal layer and the second source-drain metal layer, and at least a second flat layer is arranged between the second source-drain metal layer and the third source-drain metal layer; The plurality of data fan-out lines are located in at least one of the first gate metal layer and the second gate metal layer, and the first control line segments of the plurality of control signal lines are located in the third source-drain metal layer.

5. The display panel according to claim 3 or 4, characterized in that: The plurality of data fan-out lines include: a plurality of first data fan-out lines located in the first gate metal layer and a plurality of second data fan-out lines located in the second gate metal layer; The plurality of first data fan-out lines and the plurality of second data fan-out lines are arranged one by one in an alternating manner, and the orthographic projections of the plurality of first data fan-out lines and the plurality of second data fan-out lines on the substrate do not overlap.

6. The display panel according to claim 2, characterized in that: The control signal line also includes: a second control line segment and a third control line segment, the second control line segment is connected to one end of the first control line segment, the third control line segment is connected to the other end of the first control line segment, and the orthographic projections of the second control line segment and the third control line segment on the substrate do not overlap with the orthographic projections of the multiple data fan-out lines on the substrate; the second control line segment and the third control line segment are in the same layer structure and are located on a side of the first control line segment close to the substrate.

7. The display panel according to claim 1, characterized in that: Each data fan-out line in the first group of data fan-out lines has a first overlapping area with the first group of control signal lines on the orthographic projection of the substrate, each data fan-out line in the second group of data fan-out lines has a second overlapping area with the second group of control signal lines on the orthographic projection of the substrate, and the ratio of the first overlapping area to the second overlapping area ranges from 0.9 to 1.

1.

8. The display panel according to claim 7, characterized in that: Each data fan-out line in the first group of data fan-out lines comprises: a first sub-line segment overlapping with the orthographic projection of the first group of control signal lines on the substrate; Each data fan-out line in the second group of data fan-out lines comprises: a second sub-line segment overlapping with the orthographic projection of the second group of control signal lines on the substrate; The line width of the first sub-line segment is smaller than the line width of the second sub-line segment.

9. The display panel according to claim 8, characterized in that: A ratio of a line width of the second sub-line segment to a line width of the first sub-line segment is greater than 1 and less than 2.

10. The display panel according to claim 8, characterized in that: Each data fan-out line in the first group of data fan-out lines further includes: a third sub-line segment connected to one end of the first sub-line segment, and a fourth sub-line segment connected to the other end of the first sub-line segment; the orthographic projections of the third sub-line segment and the fourth sub-line segment on the substrate do not overlap with the orthographic projections of the first group of control signal lines on the substrate; the first sub-line segment, the third sub-line segment and the fourth sub-line segment of each data fan-out line in the first group of data fan-out lines are an integrated structure connected to each other; Each data fan-out line in the second group of data fan-out lines further includes: a fifth sub-line segment connected to one end of the second sub-line segment, and a sixth sub-line segment connected to the other end of the second sub-line segment; the orthographic projections of the fifth sub-line segment and the sixth sub-line segment on the substrate do not overlap with the orthographic projections of the second group of control signal lines on the substrate; The second sub-segment, the fifth sub-segment and the sixth sub-segment of each data fan-out line in the second group of data fan-out lines are an integrated structure connected to each other; The first sub-line segment, the third sub-line segment, the fourth sub-line segment, the fifth sub-line segment, and the sixth sub-line segment have the same line width.

11. The display panel according to claim 7, characterized in that: Each data fan-out line in the first group of data fan-out lines comprises: a first sub-line segment overlapping with the orthographic projection of the first group of control signal lines on the substrate; Each data fan-out line in the second group of data fan-out lines comprises: a second sub-line segment overlapping with the orthographic projection of the second group of control signal lines on the substrate; The orthographic projection of the first sub-line segment on the substrate is a straight line, and the orthographic projection of the second sub-line segment on the substrate is a serpentine line.

12. The display panel according to claim 11, characterized in that: Each data fan-out line in the second group of data fan-out lines further includes: a fifth sub-line segment connected to one end of the second sub-line segment, and a sixth sub-line segment connected to the other end of the second sub-line segment; the orthographic projections of the fifth sub-line segment and the sixth sub-line segment on the substrate do not overlap with the orthographic projections of the second group of control signal lines on the substrate; The second sub-segment, the fifth sub-segment and the sixth sub-segment of each data fan-out line in the second group of data fan-out lines are an integrated structure connected to each other; The fifth sub-segment or the sixth sub-segment of at least one data fan-out line in the second group of data fan-out lines has an orthographic projection on the substrate that is a serpentine line.

13. The display panel according to claim 7, characterized in that: Each control signal line in the first group of control signal lines comprises: a first control line segment overlapping with an orthographic projection of the first group of data fan-out lines on the substrate; Each control signal line in the second group of control signal lines comprises: a first control line segment overlapping with an orthographic projection of the second group of data fan-out lines on the substrate; A line width of a first control line segment of at least one control signal line in the second group of control signal lines is greater than a line width of a first control line segment of a control signal line in the first group of control signal lines.

14. The display panel according to claim 1, characterized in that: The substrate further includes: a second frame region and a third frame region located at two sides of the display region along the first direction, wherein the second frame region and the third frame region are both connected to the first frame region; The display panel further includes: a first group of gate driving circuits located in the second frame area and a second group of gate driving circuits located in the third frame area, wherein the number of gate driving circuits included in the first group of gate driving circuits is greater than the number of gate driving circuits included in the second group of gate driving circuits; The first group of control signal lines includes: a plurality of first drive control lines, the plurality of first drive control lines being configured to provide drive control signals to the first group of gate drive circuits; The second group of control signal lines includes: a plurality of second drive control lines, and the plurality of second drive control lines are configured to provide drive control signals to the second group of gate drive circuits.

15. The display panel according to claim 14, characterized in that: At least one sub-pixel of the plurality of sub-pixels comprises: a pixel circuit; The first group of gate driving circuits includes: a light-emitting driving circuit, a first reset driving circuit and a second reset driving circuit; the light-emitting driving circuit is configured to provide a light-emitting control signal to the pixel circuit, the first reset driving circuit is configured to provide a first reset control signal to the pixel circuit, and the second reset driving circuit is configured to provide a second reset control signal to the pixel circuit; The second group of gate driving circuits includes: a first scanning driving circuit and a second scanning driving circuit; the first scanning driving circuit is configured to provide a first scanning signal to the pixel circuit, and the second scanning driving circuit is configured to provide a second scanning signal to the pixel circuit.

16. A display device, characterized in that: The invention comprises the display panel as claimed in any one of claims 1 to 15.

17. A display panel, characterized in that: include: A substrate, comprising: a display area, and a first frame area located on one side of the display area; A plurality of sub-pixels and a plurality of data lines are located in the display area, the plurality of data lines are connected to the plurality of sub-pixels and are configured to provide data signals to the plurality of sub-pixels; A plurality of data fan-out lines and a plurality of control signal lines are located in the first border area, the plurality of data fan-out lines are configured to provide data signals to the plurality of data lines; the plurality of data fan-out lines include: a first group of data fan-out lines and a second group of data fan-out lines, the plurality of control signal lines include: a first group of control signal lines and a second group of control signal lines; the number of control signal lines in the first group of control signal lines is greater than the number of control signal lines in the second group of control signal lines; Each data fan-out line in the first group of data fan-out lines overlaps with an orthographic projection of the first group of control signal lines on the substrate, and each data fan-out line in the second group of data fan-out lines overlaps with an orthographic projection of the second group of control signal lines on the substrate; Each data fan-out line in the first group of data fan-out lines has a first overlapping area with the orthographic projection of the first group of control signal lines on the substrate, each data fan-out line in the second group of data fan-out lines has a second overlapping area with the orthographic projection of the second group of control signal lines on the substrate, and the ratio of the first overlapping area to the second overlapping area ranges from 0.9 to 1.

1.

18. The display panel according to claim 17, characterized in that: Each data fan-out line in the first group of data fan-out lines comprises: a first sub-line segment overlapping with the orthographic projection of the first group of control signal lines on the substrate; Each data fan-out line in the second group of data fan-out lines comprises: a second sub-line segment overlapping with the orthographic projection of the second group of control signal lines on the substrate; The line width of the first sub-line segment is smaller than the line width of the second sub-line segment.

19. The display panel according to claim 17, characterized in that: Each data fan-out line in the first group of data fan-out lines comprises: a first sub-line segment overlapping with the orthographic projection of the first group of control signal lines on the substrate; Each data fan-out line in the second group of data fan-out lines comprises: a second sub-line segment overlapping with the orthographic projection of the second group of control signal lines on the substrate; The orthographic projection of the first sub-line segment on the substrate is a straight line, and the orthographic projection of the second sub-line segment on the substrate is a serpentine line.

20. The display panel according to claim 17, characterized in that: Each control signal line in the first group of control signal lines comprises: a first control line segment overlapping with an orthographic projection of the first group of data fan-out lines on the substrate; Each control signal line in the second group of control signal lines comprises: a first control line segment overlapping with an orthographic projection of the second group of data fan-out lines on the substrate; A line width of a first control line segment of at least one control signal line in the second group of control signal lines is greater than a line width of a first control line segment of a control signal line in the first group of control signal lines.

Images