Quantization circuit and image sensor

Abstract

The utility model provides a quantization circuit and an image sensor, the quantization circuit comprises N quantization units, each quantization unit at least comprises a counting storage multiplexing unit, the counting storage multiplexing unit comprises a counting main module, a storage main module and a storage control module which are sequentially coupled, the quantization circuit realizes counting and obtains a counting result based on the counting main module and the storage main module, and realizes storage of the counting result based on the storage main module and the storage control module; according to the invention, the counting in the quantization process and the storage of the obtained counting result are multiplexed, so that the area occupied by the quantization circuit on the layout can be reduced, and the power consumption is reduced.

Description

Technical Field

[0001] The utility model belongs to the technical field of image acquisition, and particularly relates to a quantization circuit and an image sensor. Background Art

[0002] CMOS image sensors have the advantages of low voltage, low power consumption, low cost and high integration, and have important application value in the fields of machine vision, consumer electronics, high-definition monitoring and medical imaging. The analog-to-digital converter (ADC) is an important component of the readout circuit of the CMOS image sensor, which is responsible for converting the analog signal output by the pixel into a digital signal.

[0003] Column-level ADCs are generally used in CMOS image sensors. Common ones include single slope ADC (SSSDC), successive approximation register ADC (SAR ADC) and cyclic ADC (Cyclic ADC). Among them, the circuit of SS ADC is simple. Generally, each column only needs one comparator and one counter, and all columns share the ramp signal, so the column consistency is better. Therefore, SS ADC is the most widely used column-level ADC in CMOS image sensors.

[0004] However, the traditional counting method generally requires the configuration of corresponding storage units for data storage, and reads it out through the readout circuit under the control of the readout signal, and the circuit structure is complex. In an image sensor using column-level SS ADC, each column of pixels generally corresponds to at least one column of ADC, and each column of ADC contains a multi-bit counter (generally ranging from 10 to 15 bits), which means that the SS ADC occupies a large area on the entire image sensor chip layout and consumes a lot of power. At the same time, the more ADC bits, the higher the resolution, the higher the quantization accuracy, and the better the quality of the generated image, but the area and power consumption will limit the expansion of the ADC bits.

[0005] Therefore, it is necessary to provide a quantization circuit, an image sensor, an image data acquisition method, and an electronic device to solve the problems of complex circuit structure, large occupied area, and high power consumption in the prior art.

[0006] It should be noted that the above introduction to the technical background is only for the convenience of providing a clear and complete description of the technical solutions of this application and for the convenience of understanding by those skilled in the art. It cannot be considered that the above technical solutions are well known to those skilled in the art simply because they are described in the background technology section. Utility Model Content

[0007] In view of the shortcomings of the prior art described above, the purpose of the present invention is to provide a quantization circuit, an image sensor and an image data acquisition method, which are used to solve the problems of complex quantization circuit structure of image sensors in the prior art, large layout area occupied by the quantization circuit and high power consumption.

[0008] To achieve the above-mentioned object and other related objects, the utility model provides a quantization circuit, the quantization circuit includes N quantization units, the quantization unit includes at least a counting storage multiplexing unit, N is an integer greater than or equal to 1; wherein:

[0009] The counting and storage multiplexing unit includes a counting main module, a storage main module and a storage control module coupled in sequence, wherein each of the counting and storage multiplexing units is cascaded, and the quantization circuit implements counting and obtains counting results based on the counting main module and the storage main module in each of the quantization units, and implements storage of the counting results based on the storage main module and the storage control module in each of the quantization units.

[0010] Optionally, the counting main module includes an input stage module and a first transmission module, the storage main module includes a receiving stage module, a second transmission module, and a storage stage module, and the receiving stage module receives output data of the counting main module, wherein:

[0011] The input stage module comprises a first clock connection terminal and a data terminal, and is used to transmit a first data signal input from the data terminal and generate a second data signal under the control of an input clock from the first clock connection terminal;

[0012] The first transmission module is connected to the output end of the input stage module, and is used to transmit the second data signal and generate a third data signal, and its output end serves as the output end of the counting main module;

[0013] The receiving stage module comprises a second clock connection end and a data receiving end, wherein the data receiving end is connected to the output end of the counting main module, and is used for transmitting the third data signal received by the data receiving end and generating a fourth data signal under the control of the input clock of the second clock connection end;

[0014] The second transmission module is connected to the output end of the receiving stage module, and is used to transmit the fourth data signal and generate a fifth data signal;

[0015] The storage level module is connected in parallel at both ends of the second transmission module, and the storage level module includes a third clock connection end, which is used to store the fourth data signal and the fifth data signal under the input clock control of the third clock connection end to realize the storage of the counting result.

[0016] Optionally, the storage control module is connected to the output end of the second transmission module and the input end of the storage level module, and includes a data control end, which is used to output a signal corresponding to the fifth data signal under the control of a read control signal of the data control end.

[0017] Optionally, the storage control module includes a readout control module, which is used to cut off when the readout control signal received by the readout control end is at a first level, and to turn on when the readout control signal is at a second level different from the first level, so as to realize data output.

[0018] Optionally, the storage control module includes a storage signal control module, which is used to process the fifth data signal and output a signal corresponding to the processed fifth data signal through the storage control module.

[0019] Optionally, the readout control module includes a second transmission control gate.

[0020] Optionally, the storage signal control module includes a third inversion logic gate to achieve output after inverting the fifth data signal.

[0021] Optionally, the counting main module further includes a latch module connected in parallel at both ends of the first transmission module, including a fourth clock connection end for latching the second data signal and the third data signal under the control of an input clock of the fourth clock connection end.

[0022] Optionally, the quantization unit further includes a reset module, which is arranged in the second transmission module.

[0023] Optionally, the input stage module includes a first three-state inverter, which is in a working state when the received input clock is a first level, and is in a high-impedance state when the received input clock is a second level different from the first level; the first transmission module includes a first reverse logic gate; the receiving stage module includes a first transmission control gate, which is turned on when the received input clock is a first level, and is turned off when the received input clock is a second level; the second transmission module includes a second reverse logic gate; the storage stage module includes a second three-state inverter, which is in a working state when the received input clock is a first level, and is in a high-impedance state when the received input clock is a second level.

[0024] Optionally, the reset module comprises a first reset transistor and a second reset transistor, and is configured to implement reset under the control of a reset signal inverse signal received by gates of the first reset transistor and the second reset transistor.

[0025] Optionally, the quantization unit also includes a selection element, the selection element includes a first selection input terminal, a second selection input terminal and an output terminal, the output terminal is connected to the corresponding clock input terminal of the quantization unit, the first selection input terminal is connected to the positive output terminal of the quantization unit of the previous stage, and the second selection input terminal is connected to the negative output terminal of the quantization unit of the previous stage, wherein the first selection input terminal of the selection element of the first-stage quantization unit receives an initial logic signal, and the second selection input terminal receives the initial logic signal through reverse logic.

[0026] Optionally, the quantization unit also includes a holding element, which includes a first selection input terminal, a second selection input terminal and an output terminal, the first selection input terminal of the holding element is connected to the corresponding forward output terminal of the quantization unit, the second selection input terminal is connected to the corresponding reverse output terminal of the quantization unit, and the output terminal of the holding element is connected to the corresponding data terminal of the quantization unit.

[0027] Optionally, the quantization unit also includes a control logic gate, wherein a first input end of the control logic gate is connected to a data output end of the quantization unit of the previous level, a second input end of the control logic gate is connected to a read enable signal, and an output end of the control logic gate is connected to a corresponding clock input end of the quantization unit.

[0028] Optionally, the control logic gate comprises an NOR gate, a first input of the NOR gate is connected to a data output of the quantization unit of the previous stage, a second input is connected to a readout enable signal, and an output of the NOR gate is connected to a clock input of the corresponding quantization unit.

[0029] The utility model also provides an image sensor, comprising a data readout circuit and a quantization circuit as described in any one of the above schemes, wherein the data readout circuit is coupled to the output end of the quantization circuit, and the data readout circuit comprises a plurality of cascaded shift units, and the shift units correspond to the quantization units.

[0030] Optionally, the shift unit includes a shift selection switch and a D flip-flop. The shift selection switch couples the shift unit to the output end of the quantization unit in a first state to receive a corresponding counting storage result. In a second state, the shift unit is coupled to the output end of the shift unit of the previous stage to realize shift reading of the counting storage result. The output end of the D flip-flop serves as the output end of the shift unit.

[0031] The utility model further provides an image data acquisition method, which is implemented based on the quantization circuit as described in any one of the above solutions, or the utility model further provides an image data acquisition method, which is implemented based on the image sensor as described in any one of the above solutions, and the image data acquisition method includes:

[0032] resetting the quantization circuit;

[0033] Based on the counting enable signal and the clock control signal, counting is performed by the counting storage multiplexing unit to obtain the counting result;

[0034] Storing the counting result by the counting storage multiplexing unit; and

[0035] Based on the readout control signal, the stored counting result is read from the quantization circuit to achieve acquisition of image data.

[0036] Optionally, the image data includes first data and second data, and target data is acquired based on a difference between the first data and the second data, wherein the method for acquiring the target data specifically includes the following steps:

[0037] resetting the quantization circuit;

[0038] Acquire a reference signal based on a pixel circuit, and quantize the reference signal to obtain the first data;

[0039] Acquire an image signal based on a pixel circuit, and adjust the quantization circuit to count based on the first data, and quantize the image signal to obtain target data;

[0040] Wherein, the image signal is quantized based on the first data, and the target data is obtained based on the first data corresponding to the reference signal and the second data corresponding to the image signal;

[0041] storing the target data based on the quantization circuit; and

[0042] The target data is read out based on a data readout circuit.

[0043] Optionally, the pixel circuit provides the first data and the second data at different gains, or the pixel circuit provides the first data and the second data at different phases, and the target data at the corresponding gain or phase is acquired based on the quantization circuit.

[0044] Optionally, when the quantization circuit includes the holding element and the control logic gate, the method further includes:

[0045] When counting is finished, the holding element is turned on to hold data;

[0046] During the data retention process, the control logic gate is turned on to perform mode switching.

[0047] As described above, the quantization circuit and image sensor of the utility model reuse the counting in the quantization process and the storage of the obtained counting results, which can reduce the number of circuit transistors, reduce the area occupied on the quantization circuit layout, and further reduce the power consumption of the image sensor. At the same time, it is conducive to the improvement of the quantization data bit width, thereby improving the image quality. In addition, since the layout of the quantization circuit is reduced, the corresponding routing will also be shortened, the capacitance of the metal line will be reduced, and the charging and discharging current of the metal line capacitance will be reduced when the quantization circuit is working, which can further achieve power consumption reduction. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] Figure 1 Shown is a basic structural block diagram of an image sensor system.

[0049] Figure 2 Shown is a schematic diagram of a pixel circuit of an image sensor.

[0050] Figure 3 Shown is a schematic diagram of a quantization circuit provided in an embodiment of the prior art.

[0051] Figure 4 Display as Figure 3 The schematic diagram of the working principle of the quantization circuit for data quantization shown.

[0052] Figure 5 Shown is a schematic diagram of a quantization circuit provided in an embodiment of the present application.

[0053] Figure 6 Display as Figure 5 A circuit diagram corresponding to a specific implementation of the quantization circuit.

[0054] Figure 7 Display as Figure 5 A circuit diagram corresponding to another specific implementation of the quantization circuit.

[0055] Figure 8 Display as Figure 5 A circuit diagram corresponding to another specific implementation of the quantization circuit.

[0056] Fig. 9 Shown is a schematic diagram corresponding to an example of a quantization circuit and a data readout circuit in an embodiment of the present application.

[0057] Fig.10 Shown is another example diagram corresponding to the quantization circuit and the data readout circuit in the embodiment of the present application.

[0058] Fig.11 Shown is a schematic diagram of an implementation method of a data readout circuit in an embodiment.

[0059] Fig.12Shown is a schematic diagram of the image data acquisition process in one embodiment of the present application.

[0060] Fig.13 Shown is a timing diagram of an operation of acquiring image data in one embodiment of the present application.

[0061] Fig.14 Shown is another operation timing diagram of image data acquisition in one embodiment of the present application.

[0062] Component number description

[0063] 1 Quantization circuit

[0064] 2 Data readout circuit

[0065] 10 Quantization Unit

[0066] 20 Counting storage multiplexing unit

[0067] 21 Counting main module

[0068] 211 Input Stage Module

[0069] 212 First transmission module

[0070] 213 Latch Module

[0071] 22 Storage main module

[0072] 221 Receiving module

[0073] 222 Second transmission module

[0074] 223 Storage Class Module

[0075] 23 Storage and Control Module

[0076] 231 Storage signal control module

[0077] 232 Readout Control Module

[0078] 30 Select Components

[0079] 401 NAND Gate

[0080] 402 Reverse Logic

[0081] 50 Holding element

[0082] 60 Control Logic Gates

[0083] 70 Shift Unit

[0084] 70a Shift selector switch

[0085] 70b D Flip Flop DETAILED DESCRIPTION

[0086] The following is an explanation of the implementation of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific implementations, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0087] It should be emphasized that the term “include / comprises” when used herein refers to the presence of features, integers, steps or components, but does not exclude the presence or addition of one or more other features, integers, steps or components.

[0088] Features described and / or illustrated with respect to one embodiment may be used in the same or similar manner in one or more other embodiments, combined with features in other embodiments, or substituted for features in other embodiments.

[0089] For example, when describing the embodiments of the present invention in detail, for the sake of convenience, the cross-sectional diagrams showing the device structure will not be partially enlarged according to the general scale, and the schematic diagrams are only examples, which should not limit the scope of protection of the present invention. In addition, in actual production, the three-dimensional dimensions of length, width and depth should be included.

[0090] For ease of description, spatially relative terms such as "under", "below", "below", "below", "above", "on", etc. may be used herein to describe the relationship of one element or feature shown in the drawings to other elements or features. It will be understood that these spatially relative terms are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the drawings. In addition, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present.

[0091] In the context of the present application, a structure in which a first feature is described as being "above" a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features are formed between the first and second features, such that the first and second features may not be in direct contact.

[0092] It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner, and therefore the illustrations only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed at will, and the component layout may also be more complicated.

[0093] The contents proposed in the present invention are described in detail below in conjunction with the accompanying drawings provided in the present invention.

[0094] Figure 1 The basic structure block diagram of an image sensor system is shown. The image sensor includes a readout circuit and a control circuit connected to a pixel array, a functional logic unit is connected to the readout circuit, and the readout circuit and the control circuit are connected to a status register to realize control of the pixel array. The pixel array includes a plurality of pixels (P1, P2, P3) arranged in rows (R1, R2, R3...Ry) and columns (C1, C2, C3...Cx), and the pixel signal output by the pixel array is output to the readout circuit via a column line. In one embodiment, after the pixel acquires the image data, the image data is read out using the readout mode specified by the status register and then transmitted to the functional logic unit. In a specific application, the readout circuit may include an analog-to-digital conversion (ADC) circuit and others.

[0095] In some applications, the status register may include a programmable selection system to determine whether the readout system reads out through a rolling shutter mode or a global shutter mode. The functional logic unit may store image data or image data applied or processed by image effects. In one embodiment, the readout circuit can read out a row of image data at a time along the readout column line. Of course, other methods can also be used to read out image data. The operation of the control circuit can be determined by the current setting of the status register. For example, the control circuit generates a shutter signal for controlling image acquisition. In some applications, this shutter signal can be a global exposure signal so that all pixels of the pixel array simultaneously acquire their image data through a single acquisition window. In other applications, this shutter signal can also be a rolling exposure signal so that the pixels of each pixel row of the pixel array are continuously read through the acquisition window.

[0096] Figure 2 The following is a connection diagram of a pixel circuit in an image sensor. Figure 2As shown, each pixel circuit includes a photoelectric conversion element (e.g., a photodiode) and a pixel circuit (as shown in the transistor in the dotted box in the figure). The photodiode may be a buried photodiode (PPD) used in the current image sensor. In one application example, the pixel circuit includes a reset transistor (RST), a source follower transistor (SF), and a pixel selection transistor (RS), which are connected to the transfer transistor (TX) and the photodiode as shown in the figure. In a stacked structure application example, the pixel circuit includes a reset transistor, a source follower transistor, a pixel selection transistor disposed on a circuit chip, and a photodiode connected to another chip based on a transfer transistor. In a further application example, the pixel circuit may also include a gain control transistor (DCG) connected between the floating diffusion region (FD) and the reset transistor. During operation, the photoelectric conversion element generates photocharges in response to incident light during exposure, the transfer transistor is connected to a transfer signal, which controls the transfer transistor to transfer the charge accumulated in the photoelectric conversion element to the floating diffusion region, the reset transistor is connected between VDD and the floating diffusion region, responds to the reset signal to reset the sensor pixel circuit (for example, discharges or charges the floating diffusion region and the photodiode to the current voltage), the floating diffusion region is connected to the gate of the source follower transistor, the source follower transistor is connected between VDD and the pixel selection transistor to respond to the potential of the floating diffusion region and output it, the pixel selection transistor connects the source follower transistor and the pixel circuit bit line, responds to the pixel selection control signal to implement pixel selection readout and output it to the readout column.

[0097] like Figure 3 and Figure 4 As shown, a working schematic diagram of SS ADC is provided, and the circuit structure is as follows Figure 3 As shown, the working principle is as follows Figure 4 As shown. The ramp generator generates a ramp signal and samples it through the capacitor to the positive input of each column comparator. The negative input of the comparator samples the pixel signal of each column. Taking the first column as an example, the ramp signal Vramp will traverse the entire quantization voltage range and compare it with the pixel signal Vin1. At the same time, the counter starts counting. When the ramp signal Vramp is greater than the pixel signal Vin1, the comparator flips and the counter stops counting. The counting result at this time is the digital code value of the pixel signal Vin1 after quantization.

[0098] However, in the above-mentioned SS ADC, after the counter counts, the current count value is generally written into the corresponding storage unit mem, and then the value stored in mem is read out through the readout circuit. The circuit is complex as a whole, occupies a large area on the entire image sensor chip layout, and consumes a large amount of power. In addition, the area and power consumption will limit the expansion of the ADC bit number, thereby limiting the quantization accuracy and the improvement of image quality. The quantization circuit of the present application can effectively solve the above problems, which will be explained in conjunction with the specific implementation methods below.

[0099] Embodiment 1:

[0100] See also Figure 5 As shown, this embodiment provides a quantization circuit 1, which includes N quantization units 10, N is an integer greater than or equal to 1, and each quantization unit 10 includes at least a counting storage multiplexing unit 20, and the counting storage multiplexing unit 20 includes a counting main module 21, a storage main module 22 and a storage control module 23 coupled in sequence; wherein, the counting storage multiplexing units 20 corresponding to each quantization unit 10 are cascaded, and the quantization circuit 1 implements counting based on the counting main module 21 and the storage main module 22 in each counting storage multiplexing unit 20 corresponding to each quantization unit 10 to obtain the counting result, and the quantization circuit 1 implements storage of the counting result based on the storage main module 22 and the storage control module 23 in each counting storage multiplexing unit 20 corresponding to each quantization unit 10.

[0101] In one embodiment, the quantization circuit 1 corresponds to a pixel column in the pixel array one by one to realize quantization of the pixel column. Of course, in other embodiments, at least two pixel columns may correspond to one quantization circuit 1, or at least two quantization circuits 1 may be set for one pixel column, depending on actual needs. In addition, the number N of quantization units 10 in each quantization circuit 1 may be set according to the bit width of the data to be quantized. For example, for 12-bit data, N is 12, and 12 quantization units 10 are set, and N may be 8-20 bits.

[0102] Based on the above design, the counting in the quantization process and the storage of the obtained counting results are reused, which can reduce the number of circuit transistors and the area occupied by the quantization circuit layout, further reduce the power consumption of the image sensor, and at the same time, it is conducive to the improvement of the quantization data bit width, thereby improving the image quality. In addition, since the layout of the quantization circuit is reduced, the corresponding routing will also be shortened, the capacitance of the metal line will be reduced, and the charging and discharging current of the metal line capacitance when the quantization circuit is working will be reduced, which can further achieve power consumption reduction.

[0103] See also Figure 6As shown, an implementation method of a counting storage multiplexing unit 20 is provided. In this implementation method, for the counting storage multiplexing unit 20, the counting main module 21 includes an input level module 211 and a first transmission module 212, and the storage main module 22 includes a receiving level module 221, a second transmission module 222 and a storage level module 223; wherein the receiving level module 221 receives the output data of the counting main module 21.

[0104] In this implementation, the input stage module 211 includes a first clock connection terminal CK and a data terminal D, and is used to transmit a first data signal input from the data terminal D and generate a second data signal under the control of an input clock from the first clock connection terminal CK;

[0105] The first transmission module 212 is connected to the output end of the input stage module 211, and is used to transmit the second data signal and generate a third data signal, and its output end serves as the output end of the counting main module 21;

[0106] The receiving stage module 221 includes a second clock connection terminal CK and a data receiving terminal, the data receiving terminal is connected to the output terminal of the counting main module 21, and is used to transmit the third data signal received by the data receiving terminal and generate a fourth data signal under the input clock control of the second clock connection terminal CK;

[0107] The second transmission module 222 is connected to the output end of the receiving stage module 221, and is used to transmit the fourth data signal and generate a fifth data signal;

[0108] The storage level module 223 is connected in parallel at both ends of the second transmission module 222, and the storage level module 223 includes a third clock connection terminal CK. The storage level module 223 is used to store the fourth data signal and the fifth data signal under the input clock control of the third clock connection terminal CK to realize the storage of the counting result.

[0109] It should be noted that the first clock connection terminal CK, the second clock connection terminal CK and the third clock connection terminal CK described in this embodiment are all clock connection terminals of the corresponding quantization unit 10, receiving the same input clock, and different names are used to distinguish between different modules, which can be understood by those skilled in the art.

[0110] Continue to see Figure 6 As shown, in a specific implementation, the input stage module 211 includes a first three-state inverter TSINV1, which is in a working state when the received input clock is a first level (such as a low level), and is in a high-impedance state when the received input clock is a second level (such as a high level), that is, when the input clock is a low level, the first data signal is inverted to generate a second data signal.

[0111] In a specific example, the first tri-state inverter TSINV1 includes a first MOS tube M1, a second MOS tube M2, a third MOS tube M3 and a fourth MOS tube M4; the gate of the first MOS tube M1 is connected to the gate of the fourth MOS tube M4 and serves as the input end of the first tri-state inverter TSINV1 to connect the first data signal, the source is connected to the reference voltage, and the drain is connected to the source of the second MOS tube M2; the gate of the second MOS tube M2 is connected to the input clock, the drain is connected to the drain of the third MOS tube M3 and serves as the output end of the first tri-state inverter TSINV1 to generate the second data signal; the gate of the third MOS tube M3 is connected to the reverse signal of the input clock, and the source is connected to the drain of the fourth MOS tube M4; the source of the fourth MOS tube M4 is connected to the reference ground; wherein, the first MOS tube M1 and the second MOS tube M2 are PMOS tubes, and the third MOS tube M3 and the fourth MOS tube M4 are NMOS tubes.

[0112] The first transmission module 212 includes a first inversion logic gate MINV1 for inverting the second data signal to generate a third data signal.

[0113] In a specific example, the first reverse logic gate MINV1 includes a fifth MOS tube M5 and a sixth MOS tube M6; the gate of the fifth MOS tube M5 is connected to the gate of the sixth MOS tube M6 and serves as the input end of the first reverse logic gate MINV1, the source is connected to the reference voltage, the drain is connected to the drain of the sixth MOS tube M6 and serves as the output end of the first reverse logic gate MINV1; the source of the sixth MOS tube M6 is connected to the reference ground. The fifth MOS tube M5 is a PMOS tube, and the sixth MOS tube M6 is an NMOS tube.

[0114] The receiving stage module 221 includes a first transmission control gate TGK1, which is turned on when the input clock received at the second clock connection terminal CK is a first level (low level), transmits the received third data signal and generates a fourth data signal, and is cut off when the received input clock is a second level (high level) different from the first level.

[0115] In a specific example, the first transmission control gate TGK1 includes a seventh MOS tube M7 and an eighth MOS tube M8; a gate of the seventh MOS tube M7 is connected to the reverse signal of the input clock, a gate of the eighth MOS tube M8 is connected to the input clock, one end of the seventh MOS tube M7 and the eighth MOS tube M8 connected in parallel serves as an input end of the first transmission control gate TGK1 to connect the third data signal, and the other end serves as an output end of the first transmission control gate TGK1 to generate a fourth data signal; wherein the seventh MOS tube M7 is a PMOS tube, and the eighth MOS tube M8 is an NMOS tube.

[0116] The second transmission module 222 includes a second inversion logic gate MINV2, which is used to invert the fourth data signal to generate a fifth data signal.

[0117] In a specific example, the second reverse logic gate MINV2 includes a ninth MOS tube M9 and a tenth MOS tube M10; the gate of the ninth MOS tube M9 is connected to the gate of the tenth MOS tube M10 and serves as the input end of the second reverse logic gate MINV2, the source is connected to the reference voltage, the drain is connected to the drain of the tenth MOS tube M10 and serves as the output end of the second reverse logic gate MINV2; the source of the tenth MOS tube M10 is connected to the reference ground. The ninth MOS tube M9 is a PMOS tube, and the tenth MOS tube M10 is an NMOS tube.

[0118] The storage level module 223 includes a second three-state inverter TSINV2, which is in a working state when the input clock received by the third clock connection terminal CK is a first level (such as a low level), and is in a high-impedance state when the received input clock is a second level (such as a high level), that is, the fourth data signal and the fifth data signal can be stored under the control of the input clock to achieve the storage of the counting result, wherein the fourth data signal corresponds to the output end of the storage level module 223, and the fifth data signal corresponds to the input end of the storage level module 223. Of course, other clock control designs can also be used to achieve the storage of corresponding data signals.

[0119] In a specific example, the second three-state inverter TSINV2 includes an eleventh MOS tube M11, a twelfth MOS tube M12, a thirteenth MOS tube M13 and a fourteenth MOS tube M14; the gate of the eleventh MOS tube M11 is connected to the gate of the fourteenth MOS tube M14 and serves as the input end of the second three-state inverter TSINV2, the source of the eleventh MOS tube M11 is connected to the reference voltage, and the drain is connected to the source of the twelfth MOS tube M12; the gate of the twelfth MOS tube M12 is connected to the control clock, the drain is connected to the drain of the thirteenth MOS tube M13 and serves as the output end of the second three-state inverter TSINV2; the gate of the thirteenth MOS tube M13 is connected to the reverse signal of the control clock, and the source is connected to the drain of the fourteenth MOS tube M14; the source of the fourteenth MOS tube M14 is connected to the reference ground; wherein, the eleventh MOS tube M11 and the twelfth MOS tube M12 are PMOS tubes, and the thirteenth MOS tube M13 and the fourteenth MOS tube M14 are NMOS tubes. In addition, in this embodiment, the reference voltage may be the power supply voltage VDD.

[0120] See also Figure 7As shown, in a further implementation, the counting main module 21 further includes a latch module 213, the latch module 213 is connected in parallel at both ends of the first transmission module 212, and the latch module 213 includes a fourth clock connection terminal CK, which is used to latch the second data signal and the third data signal under the input clock control of the fourth clock connection terminal CK. Here, the fourth clock connection terminal CK is similar to the first three clock connection terminals CK in terms of the principle of description.

[0121] In this embodiment, the latch module 213 includes a third three-state inverter TSINV3, which is used to store the second data signal and the third data signal under the input clock control of the fourth clock connection terminal CK, wherein the second data signal corresponds to the output end of the latch module 213, and the third data signal corresponds to the input end of the latch module 213.

[0122] In a specific example, the third three-state inverter TSINV3 includes a nineteenth MOS tube M19, a twentieth MOS tube M20, a twenty-first MOS tube M21 and a twenty-second MOS tube M22; the gate of the nineteenth MOS tube M19 is connected to the gate of the twenty-second MOS tube M22 and serves as the input end of the third three-state inverter TSINV3, the source of the nineteenth MOS tube M19 is connected to the reference voltage, and the drain is connected to the source of the twentieth MOS tube M20; the gate of the twentieth MOS tube M20 is connected to the control clock, the drain is connected to the drain of the twenty-first MOS tube M21 and serves as the output end of the third three-state inverter TSINV3; the gate of the twenty-first MOS tube M21 is connected to the reverse signal of the control clock, and the source is connected to the drain of the twenty-second MOS tube M22; the source of the twenty-second MOS tube M22 is connected to the reference ground; wherein, the nineteenth MOS tube M19 and the twentieth MOS tube M20 are PMOS tubes, and the twenty-first MOS tube M21 and the twenty-second MOS tube M22 are NMOS tubes.

[0123] Continue to see Figure 6 and Figure 7 As shown, in one embodiment, the storage control module 23 is connected to the output end of the second transmission module 222 and the input end of the storage level module 223, and the storage control module 23 includes a read-out control end, which is used to output a signal corresponding to the fifth data signal under the control of the read-out control signal RD of the read-out control end.

[0124] In this implementation, the storage control module 23 includes a readout control module 232. The readout control module 232 is turned off when the readout control signal received by the readout control terminal RD is a first level (such as a low level), and is turned on when the readout control signal is a second level (such as a high level) different from the first level, and outputs corresponding data. In one implementation, the readout control module 232 includes a second transmission control gate TGK2.

[0125] In a specific example, the second transmission gate TGK2 includes a seventeenth MOS tube M17 and an eighteenth MOS tube M18; a gate of the seventeenth MOS tube M17 is connected to a reverse signal RDB of a readout control signal, a gate of the eighteenth MOS tube M18 is connected to a readout control signal RD, one end of the seventeenth MOS tube M17 and the eighteenth MOS tube M18 connected in parallel serves as an input end of the second transmission gate TGK2 to connect the fifth data signal or other signals corresponding to the fifth data signal, such as a negated signal of the fifth data signal, and the other end serves as an output end of the second transmission gate TGK2; wherein the seventeenth MOS tube M17 is a PMOS tube, and the eighteenth MOS tube M18 is an NMOS tube.

[0126] In one example, the storage control module 23 also includes a storage signal control module 231, which is used to process and output the fifth data signal. Further, the storage signal control module 231 is connected to the readout control module 232, which is used to output the processed data; for example, the storage signal control module 231 can be an inverting logic circuit, which is used to invert the fifth data signal to output data. In one implementation, the storage signal control module 231 includes a third inverting logic gate MINV3, which is used to invert the fifth data signal to output data, and output it through the readout control module 232.

[0127] In a specific example, the third reverse logic gate MI NV3 includes a fifteenth MOS tube M15 and a sixteenth MOS tube M16; the gate of the fifteenth MOS tube M15 is connected to the gate of the sixteenth MOS tube M16 and serves as the input end of the third reverse logic gate MI NV3, the source is connected to the reference voltage, the drain is connected to the drain of the sixteenth MOS tube M16 and serves as the output end of the third reverse logic gate MI NV3; the source of the sixteenth MOS tube M16 is connected to the reference ground. Among them, the fifteenth MOS tube M15 is a PMOS tube, and the sixteenth MOS tube M16 is an NMOS tube.

[0128] See also Figure 8 As shown, in one implementation, the quantization unit 10 further includes a reset module, and the reset module is arranged in the second transmission module 222 to achieve resetting of the quantization unit 10 .

[0129] In a specific example, the reset module includes a reset transistor, which is selected as a first reset transistor M23 and a second reset transistor M24 in this example, wherein further, the first reset transistor M23 is connected between a reference voltage (such as a power supply voltage VDD) and an output terminal of the second transmission module 222, and the second reset transistor M24 is connected between the second transmission module 222 and a reference ground. Figure 8In the example shown, the first reset transistor M23 is connected between the reference voltage and the output end of the second reverse logic gate MI NV2, and the second reset transistor M24 is connected between the source of the tenth MOS transistor M10 and the reference ground. In this example, the first reset transistor M23 is a PMOS transistor, the second reset transistor M24 is an NMOS transistor, and the gates of the first reset transistor M23 and the second reset transistor M24 both receive the reverse signal RSTB of the reset signal to achieve reset.

[0130] See also Fig. 9 As shown, in one embodiment, the counting storage multiplexing unit 20 in the corresponding quantization unit 10 can be implemented in a cascade-based manner based on DFF (D flip-flop). The D flip-flop can be regarded as composed of two levels of storage units. The storage unit can be an existing bistable structure, and its functions include a write switch, a read drive, and a read switch. In this embodiment, the D flip-flop is multiplexed with the storage unit, and the counting part is composed of a cascade of D flip-flops. In this embodiment, the output end of each level of D flip-flop is connected to the subsequent data read circuit through a CMOS switch (such as the second transmission control gate TGK2 of the read control module 232), and the CMOS switch is controlled by a pair of opposite signals mem_rd (read control signal RD) and mem_rdb (RDB) to achieve storage. The specific corresponding circuit connection structure can be seen in Figure 6-8 shown.

[0131] Please continue reading Fig. 9 As shown, in one embodiment, the quantization unit 10 also includes a selection element 30, the selection element 30 includes a first selection input terminal 0, a second selection input terminal 1 and an output terminal, the selection element 30 can be a selection switch MUX, and the output terminal of the selection element 30 is connected to the clock input terminal CK of the corresponding quantization unit 10. Based on the working principle of DFF, it can be understood that the clock input terminal CK here corresponds to the first four clock connection terminals CK to receive the corresponding input clock signal; the first selection input terminal 0 is connected to the forward output terminal Q of the previous stage quantization unit 10, and the second selection input terminal 1 is connected to the reverse output terminal QB of the previous stage quantization unit 10, wherein the first selection input terminal 0 of the selection element 30 of the first stage quantization unit 10 receives the initial logic signal, and the second selection input terminal 1 receives the initial logic signal through the reverse logic 402.

[0132] In one example, the quantization circuit 1 includes a NAND gate 401, a first input terminal of the NAND gate 401 receives an initial clock count_clk, a second input terminal of the NAND gate 401 receives a count enable signal count_en, and an output terminal of the NAND gate 401 generates an initial logic signal to be provided to a first selection input terminal 0 of a selection element 30 of the first-stage quantization unit 10. In addition, in an optional example, the reverse logic 402 is an inverter, which receives the initial logic signal and reversely provides the received initial logic signal to a second selection input terminal 1 of the selection element 30 of the first-stage quantization unit 10. In this example, the inverter is connected between the output terminal of the NAND gate 401 and the second selection input terminal 1 of the selection element 30 to perform signal inversion.

[0133] It should be noted that the selection element 30 also has a count control terminal, which receives a count control signal count_up and can switch between up-counting and down-counting of the counter. For example, Fig. 9 In the example shown, when the first selection input terminal 0 of the selection element 30 is connected to the clock input terminal CK of the DFF, it counts up, and when the second selection input terminal 1 is connected to the clock input terminal CK of the DFF, it counts down.

[0134] In addition, the DFF corresponding to the quantization unit 10 also has a reset terminal to receive a reset signal count_rst. In one embodiment, see Figure 8 In RSTB, the reset signal count_rst corresponds to the connection and control of the first reset transistor M23 and the second reset transistor M24, and reset is achieved through its reverse signal.

[0135] See also Fig.10 As shown, in one embodiment, the quantization unit 10 also includes a holding element 50, the holding element 50 includes a first selection input terminal 0, a second selection input terminal 1 and an output terminal, the holding element 50 can be a selection switch MUX, the first selection input terminal 0 of the holding element 50 is connected to the forward output terminal Q of the corresponding level quantization unit 10, the second selection input terminal 1 is connected to the reverse output terminal QB of the corresponding level quantization unit 10, and the output terminal of the holding element 50 is connected to the data terminal D of the corresponding quantization unit 10.

[0136] Specifically, in this embodiment, during the switching process of the selection element 30 for up counting and down counting, the clock signal of the DFF may jump, generating a rising edge or a falling edge. A holding element 50 is set between D and Q / QB of the DFF. Before the counting control signal (such as count_up) is switched, the quantization circuit can be switched to the keep mode, which is controlled by the holding signal count_keep. In the keep mode, the Q of the DFF is connected to the D terminal, that is, through count_keep, the first selection input terminal 0 of the holding element 50 connects the positive output terminal Q and the data terminal D of the DFF together. Even if there is a rising edge pulse at the clock input terminal of the DFF, it will not affect the result of the DFF latching, thereby preventing the DFF from counting an extra number. After the counting control signal is switched, the second selection input terminal 1 of the holding element 50 connects the reverse output terminal QB and the data terminal D of the DFF together through the count_keep signal to form a counter mode for normal counting.

[0137] Continue to see Fig.10 As shown, in one embodiment, the quantization unit 10 also includes a control logic gate 60, and the first input end of the control logic gate 60 is connected to the data output end of the previous stage quantization unit 10, which can be the forward output end Q or the reverse output end QB of the DFF. When there is a selection element 30, the first input end of the control logic gate 60 is connected to the output end of the selection element 30 to realize the control of upward counting or downward counting; in addition, the second input end of the control logic gate 60 is connected to the read enable signal read_en, and the output end of the control logic gate 60 is connected to the clock input end CK of the corresponding quantization unit 10.

[0138] In a specific example, the control logic gate 60 includes an NOR gate, that is, an NOR gate is added before each level of DFF clock signal, one input end of the NOR gate (the first input end of the control logic gate 60) is connected to the output end of the selection element 30 or the data output end of the previous level quantization unit 10, the other input end of the NOR gate (the second input end of the control logic gate 60) is connected to a read enable signal read_en, and the output end of the NOR gate is connected to the clock input end CK of the corresponding quantization unit 10.

[0139] In this example, the design of the control logic gate 60 can be used to facilitate the control of the counting and storage of the counting results based on the quantization circuit. For example, when counting, the read enable signal read_en is 0, and the output of the NOR gate is Q or QB of the previous DFF, that is, the normal counting mode; after the counting is completed, read_en is 1, and the output of the NOR gate is 0, which is independent of the previous DFF. At this time, the clock input of each DFF is 0, and the slave stage of the DFF is in a latched state, latching the current counting result. The design of the control logic gate 60 can be conducive to improving the accuracy of the storage of the counting result and improving the overall quantization effect.

[0140] See also Fig.11 As shown, and refer to Fig. 9 and Fig.10 In one embodiment, the data readout circuit 2 is coupled to the output terminal of the quantization circuit 1 to read out the counting result. In one example, one data readout circuit 2 corresponds to one quantization circuit 1, and each data readout circuit 2 corresponds to one column of pixels; wherein the data readout circuit 2 includes a plurality of cascaded shift units 70, and the shift units 70 correspond to the quantization units 10 one by one. In addition, the number of the shift units 70 can be designed according to the bit width of the quantization data.

[0141] As an example, the shift unit 70 includes a shift selection switch 70a and a D flip-flop 70b to realize shift readout. In the first state φ1, the shift selection switch 70a couples the shift unit 70 to the output end of the quantization unit 10 to receive the corresponding counting result, and in the second state φ2, the shift unit 70 is coupled to the output end of the previous stage shift unit 70, such as when the data end D of the current stage D flip-flop 70b receives the positive output end Q of the previous stage D flip-flop 70b, and the output end of the D flip-flop serves as the output end of the shift unit 70. In the above, the shift selection switch 70a can be any switch in the prior art that realizes the above function.

[0142] Embodiment 2:

[0143] The utility model also provides an image sensor, comprising the quantization circuit described in any one of the above schemes. The image sensor may be a CMOS image sensor. It can be understood that the image sensor in the second embodiment may include a quantization circuit and a data readout circuit, which have been described in the first embodiment and will not be repeated here.

[0144] The utility model also provides an electronic device, comprising an image sensor as described in any one of the above solutions. The electronic device can be a security monitoring, vehicle-mounted electronics, mobile phone camera, machine vision and other equipment, and the image sensor of the utility model can obtain high-quality image information.

[0145] Embodiment three:

[0146] like Fig.12 Shown and referenced Fig. 9 and 10 This embodiment provides an image data acquisition method. The image data acquisition method of this embodiment is implemented based on any one of the quantization circuits in the first embodiment, or is implemented based on any one of the image sensors in the second embodiment. The image data acquisition method includes:

[0147] S1: Reset quantization circuit 1;

[0148] S2: Based on the counting enable signal and the clock control signal (such as the initial clock signal), counting is performed through the counting storage multiplexing unit;

[0149] S3: After the counting is completed, the counting result is stored in the counting storage multiplexing unit;

[0150] S4: Based on the readout control signal, the counting result is read out from the quantization circuit.

[0151] Based on the above method, the counting in the quantization process and the storage of the obtained counting results are reused, which can reduce the number of circuit transistors and the area occupied by the quantization circuit layout, and further reduce the power consumption of the image sensor, which is conducive to the improvement of the quantization data bit width, thereby improving the image quality. In addition, since the layout of the quantization circuit is reduced, the corresponding routing will also be shortened, the capacitance of the metal line will be reduced, and the charging and discharging current of the metal line capacitance will be reduced when the quantization circuit is working, which can further reduce power consumption.

[0152] In a specific operation mode, the timing control is as follows Fig.13 As shown:

[0153] At time t0-t1, the reset signal count_rst enables resetting of all counters (quantization units);

[0154] At time t2, the count enable signal count_en becomes high level, and the high-speed clock signal initial clock signal count_clk starts to take effect. At this time, the counter counts in the normal quantization process;

[0155] At t3, the count enable signal count_en becomes low, the counting stops, and the counting result is latched;

[0156] During the time period t4-t5, the readout control signal RD (shown as mem_rd) is at a high level, and then the readout control signal RDB (shown as mem_rdb) is at a low level, so that the CMOS switch connecting each level of D flip-flop and the readout module is turned on, and the readout module reads the quantization result of this time to the subsequent digital processing module;

[0157] At this point, a complete quantification and readout process is completed.

[0158] In one embodiment, see Fig.10 As shown, when the quantization circuit has a control logic gate (NAND gate) 60, the image data acquisition process includes the following steps:

[0159] In the counting process of step S2, the read enable signal read_en received by the control logic gate (NAND gate) 60 is 0. At this time, the output of the control logic gate (NAND gate) 60 is QB of the previous stage DFF, that is, the normal counting mode; in the storage process of step S3, after the counting is completed, the read enable signal read_en received by the control logic gate (NAND gate) 60 is 1, and the output of the control logic gate (NAND gate) 60 is 0, which is independent of the previous stage DFF. At this time, the clock input terminal of each stage DFF is 0, and the slave stage of DFF is in a latched state, latching the result of the current counting.

[0160] In further embodiments, see Fig.10 As shown, when the quantization circuit has a holding element 50, the image data acquisition process includes the following steps:

[0161] In the switching process of the read enable signal read_en received by the control logic gate (NAND gate) 60, the clock signal of the DFF may jump, generating a rising edge or a falling edge. For example, in this embodiment, the DFF is triggered by the rising edge, and a holding element 50 is set between the D and Q / QB of the DFF. After the counting is completed and before the read enable signal read_en is switched, the quantization circuit can be switched to the keep mode, which is controlled by the hold signal count_keep. In the keep mode, the Q of the DFF is connected to the D terminal, and even if there is a rising edge pulse at the clock input end of the DFF, it will not affect the latching result of the DFF, preventing the DFF from counting an extra number. In addition, in this example, the holding element 50 can be used in the up / down counting mode switching process and the counting storage / data reading process, which can further save the circuit area and improve the overall performance.

[0162] In a specific operation mode, the timing control is as follows Fig.14 As shown:

[0163] Before quantization starts, at time t0-t1, the reset signal count_rst enables resetting all counters;

[0164] At time t2, the count enable signal count_en becomes high level, and the high-speed clock signal count_clk starts to take effect. At this time, the counter performs counting in the normal quantization process;

[0165] At time t3, the count enable signal count_en becomes low level and counting stops. At the same time, the hold signal count_keep becomes high level to achieve data retention.

[0166] Between t3 and t4, the read enable signal read_en becomes high, setting the clock input of all DFFs to 0, so that the current count value is latched in the slave stage of the DFF;

[0167] In the time period t4-t5, the readout control signal RD (shown as mem_rd) is at a high level, and the readout control signal RDB (shown as mem_rdb) is at a low level, so that the CMOS switch connecting each level of D flip-flop and the readout module is turned on, and the readout module reads the quantization result of this time to the subsequent digital processing module;

[0168] At this point, a complete quantification and readout process is completed.

[0169] In addition, after t5, the read enable signal read_en may be further changed to a low level, and the hold signal count_keep may be further changed to a low level, so as to perform the next quantization operation.

[0170] In one embodiment, the image data includes first data and second data, and the target data is obtained based on the difference between the first data and the second data. In a specific application, the first data is data obtained by quantization corresponding to a reset signal provided by a pixel circuit, and the second data is data obtained by quantization of an image signal provided by the pixel circuit. The target data is the difference between the two, that is, the result of noise reduction by performing correlated double sampling CDS. The method for obtaining the target data includes the following steps:

[0171] S21: reset quantization circuit;

[0172] S22: acquiring a reference signal based on the pixel circuit, and quantizing the reference signal to obtain first data (VRST);

[0173] S23: acquiring an image signal based on a pixel circuit, adjusting a quantization circuit, counting based on the first data, and quantizing the image signal to obtain target data (VCDS);

[0174] Wherein, the image signal is quantized based on the first data (VRST), and the target data is obtained based on the first data (VRST) corresponding to the reference signal and the second data (VSIG) corresponding to the image signal;

[0175] S24: storing target data (VCDS) based on the quantization circuit;

[0176] S25: Target data (VCDS) is read out based on the data readout circuit.

[0177] In one embodiment, the method of adjusting the quantization circuit in step S23 can be to switch the up and down counting mode of the counting circuit. For example, the reference signal is quantized based on the upward counting method to obtain the first data (VRST). In this step, the quantization circuit is switched to the downward counting mode and continues to count downward, that is, the image signal is quantized based on the downward counting method. At this time, the data corresponding to the image signal is the second data (VSIG), and the counting result is the total result of two counts (upward counting and downward counting), that is, the target data (VCDS), thereby obtaining the final quantization result, that is, the counting result that needs to be stored.

[0178] It should be noted that, in this implementation, the counting sequence corresponding to the prior art in steps S21 to S25 can be adjusted according to actual conditions without affecting the realization of the technical effects of the present application.

[0179] In other embodiments, the pixel circuit provides the first data and the second data at different gains, or the pixel circuit provides the first data and the second data at different phases, and the target data at the corresponding gain or the corresponding phase is acquired based on the quantization circuit.

[0180] In one example, different gains may be high gain (HCG) and low gain (LCG), and high gain and low gain may be achieved by controlling the gain control transistor DCG in the pixel circuit to be turned off and on. For example, the gain control transistor is turned on to quantize data under low gain, and the data under low gain includes first data (reset signal) and second data (image signal) under low gain. Similarly, the gain control transistor is turned off to quantize data under high gain, and the data under high gain includes first data (reset signal) and second data (image signal) under high gain, thereby achieving correlated double sampling under dual gain.

[0181] In one example, different phases may be left phase and right phase, and the left phase and right phase may be realized by controlling the transmission control transistor in the pixel circuit or directly physically blocking the corresponding pixel, so as to obtain different phase information to realize phase focusing. For example, the data of the left phase information includes the first data (reset signal) and the second data (image signal) under the left phase. Similarly, the data of the right phase information includes the first data (reset signal) and the second data (image signal) under the right phase, thereby realizing correlated double sampling under the left and right phase information. Of course, it can also be upper and lower phases or both groups.

[0182] In summary, the utility model simplifies the counter in the SS ADC, and can delete the storage unit mem of the traditional solution, so that the D flip-flop can realize the function of storing the quantization result after counting. The number of transistors in each level of counter can be reduced, and the layout area can be reduced, which is very significant for the reduction of the area of ​​the entire ADC array. At the same time, since the layout of each level of counter is reduced, the routing will also be shortened, the capacitance of the metal wire will be reduced, and the charging and discharging current of the metal wire capacitance when the counter is counting will be reduced, so that the power consumption of the counter is reduced, and the chip area and power consumption can be reduced when realizing the normal analog-to-digital conversion function. Therefore, the utility model effectively overcomes the various shortcomings of the prior art and has a high industrial utilization value.

[0183] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the technology may modify or change the above embodiments without violating the spirit and scope of the present invention. All equivalent modifications or changes made by those with ordinary knowledge in the relevant technical field without departing from the spirit and technical ideas disclosed in the present invention shall still be covered by the claims of the present invention.

Claims

1. A quantization circuit, characterized in that: The quantization circuit includes N quantization units, each of which includes at least a counting storage multiplexing unit, where N is an integer greater than or equal to 1; wherein: The counting and storage multiplexing unit includes a counting main module, a storage main module and a storage control module coupled in sequence, wherein each of the counting and storage multiplexing units is cascaded, and the quantization circuit implements counting and obtains counting results based on the counting main module and the storage main module in each of the quantization units, and implements storage of the counting results based on the storage main module and the storage control module in each of the quantization units.

2. The quantization circuit according to claim 1, characterized in that: The counting main module includes an input stage module and a first transmission module, and the storage main module includes a receiving stage module, a second transmission module, and a storage stage module. The receiving stage module receives the output data of the counting main module, wherein: The input stage module comprises a first clock connection terminal and a data terminal, and is used to transmit a first data signal input from the data terminal and generate a second data signal under the control of an input clock from the first clock connection terminal; The first transmission module is connected to the output end of the input stage module, and is used to transmit the second data signal and generate a third data signal, and its output end serves as the output end of the counting main module; The receiving stage module comprises a second clock connection end and a data receiving end, wherein the data receiving end is connected to the output end of the counting main module, and is used for transmitting the third data signal received by the data receiving end and generating a fourth data signal under the control of the input clock of the second clock connection end; The second transmission module is connected to the output end of the receiving stage module, and is used to transmit the fourth data signal and generate a fifth data signal; The storage level module is connected in parallel at both ends of the second transmission module, and the storage level module includes a third clock connection end, which is used to store the fourth data signal and the fifth data signal under the input clock control of the third clock connection end to realize the storage of the counting result.

3. The quantization circuit according to claim 2, characterized in that: The storage control module is connected to the output end of the second transmission module and the input end of the storage level module, and includes a readout control end for outputting a signal corresponding to the fifth data signal under the control of a readout control signal of the readout control end.

4. The quantization circuit according to claim 3, characterized in that: The storage control module includes a read control module, which is used to cut off when the read control signal received at the read control end is a first level, and turn on when the read control signal is a second level different from the first level, so as to realize data output; and / or, the storage control module includes a storage signal control module, which is used to process the fifth data signal and realize the output of the signal corresponding to the processed fifth data signal through the storage control module.

5. The quantization circuit according to claim 4, characterized in that: The readout control module includes a second transmission control gate; and / or the storage signal control module includes a third inversion logic gate, so as to output the fifth data signal after inverting it.

6. The quantization circuit according to claim 2, characterized in that: The counting main module also includes a latch module, which is connected in parallel at both ends of the first transmission module, and includes a fourth clock connection end, which is used to latch the second data signal and the third data signal under the control of the input clock of the fourth clock connection end; and / or, the quantization unit also includes a reset module, which is arranged in the second transmission module.

7. The quantization circuit according to claim 6, characterized in that: The input stage module includes a first tri-state inverter, which is in a working state when the received input clock is a first level, and is in a high-impedance state when the received input clock is a second level different from the first level; the first transmission module includes a first reverse logic gate; the receiving stage module includes a first transmission control gate, which is turned on when the received input clock is a first level, and is turned off when the received input clock is a second level; the second transmission module includes a second reverse logic gate; the storage stage module includes a second tri-state inverter, which is in a working state when the received input clock is a first level, and is in a high-impedance state when the received input clock is a second level; And / or, the reset module includes a first reset transistor and a second reset transistor, which are used to achieve reset under the control of a reset signal inverse signal received by gates of the first reset transistor and the second reset transistor.

8. The quantization circuit according to claim 1, characterized in that: The quantization unit also includes a selection element, the selection element includes a first selection input terminal, a second selection input terminal and an output terminal, the output terminal is connected to the corresponding clock input terminal of the quantization unit, the first selection input terminal is connected to the positive output terminal of the quantization unit of the previous stage, and the second selection input terminal is connected to the negative output terminal of the quantization unit of the previous stage, wherein the first selection input terminal of the selection element of the first stage quantization unit receives an initial logic signal, and the second selection input terminal receives the initial logic signal through reverse logic; and / or, the quantization unit also includes a holding element, the holding element includes a first selection input terminal, a second selection input terminal and an output terminal, the first selection input terminal of the holding element is connected to the corresponding positive output terminal of the quantization unit, the second selection input terminal of the holding element is connected to the corresponding negative output terminal of the quantization unit, and the output terminal of the holding element is connected to the corresponding data terminal of the quantization unit.

9. The quantization circuit according to any one of claims 1 to 8, characterized in that: The quantization unit also includes a control logic gate, wherein a first input end of the control logic gate is connected to a data output end of the quantization unit of the previous stage, a second input end of the control logic gate is connected to a readout enable signal, and an output end of the control logic gate is connected to a corresponding clock input end of the quantization unit.

10. The quantization circuit according to claim 9, characterized in that: The control logic gate comprises a NOR gate, a first input end of the NOR gate is connected to the data output end of the quantization unit of the previous stage, a second input end is connected to a readout enable signal, and an output end of the NOR gate is connected to the clock input end of the corresponding quantization unit.

11. An image sensor, characterized in that: It comprises a data readout circuit and a quantization circuit as described in any one of claims 1 to 10, wherein the data readout circuit is coupled to the output end of the quantization circuit, and the data readout circuit comprises a plurality of cascaded shift units, and the shift units correspond to the quantization units.

12. The image sensor according to claim 11, wherein: The shift unit includes a shift selection switch and a D flip-flop. The shift selection switch couples the shift unit to the output end of the quantization unit in a first state to receive the corresponding counting storage result. In a second state, the shift unit is coupled to the output end of the shift unit of the previous stage to realize the shift reading of the counting storage result. The output end of the D flip-flop serves as the output end of the shift unit.

Images