Silicon wafer front and back side detection mechanism

By designing a silicon wafer detection mechanism including front, reverse detection mechanism and thickness detection mechanism, the problems of missed detection, false detection and inefficiency in the prior art are solved, and efficient detection of front, back and thickness of the silicon wafer is achieved.

CN222672969UActive Publication Date: 2025-03-25SUZHOU SEMI PRECISION TECH CO LTD
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Patent Information

Application Number
CN202421341661.6
Authority / Receiving Office
CN · China
Patent Type
Utility models(China)
Current Assignee / Owner
Filing Date
2024-06-13
Publication Date
2025-03-25
Estimated Expiration
2034-06-13

AI Technical Summary

Technical Problem

The existing wafer detection methods have missed detection and misdetection, which are inefficient and cannot effectively detect the front and back surfaces and thickness of the silicon wafer.

Method used

A silicon wafer front and back detection mechanism is designed, including a mounting frame, a wafer streamline conveying mechanism, a front detection mechanism, a reverse detection mechanism and a thickness detection mechanism. The front and reverse detection mechanisms are CCD cameras respectively, which can be set inclined on the wafer streamline conveying mechanism to realize simultaneous detection of the front and back sides. Meanwhile, the first and second light source mechanisms are provided to assist in detection, and the limiting mechanism is used to fix the wafer for thickness detection.

Benefits of technology

The front and back sides of the silicon wafer are detected simultaneously during the flow line, ensuring that each silicon wafer is fully inspected and wafer thickness can be detected, improving detection efficiency and accuracy.

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Abstract

The utility model discloses a silicon wafer front and back detection mechanism, which comprises a mounting rack, a wafer streamline conveying mechanism arranged on the mounting rack, a front detection mechanism arranged above the wafer streamline conveying mechanism, a back detection mechanism arranged below the wafer streamline conveying mechanism, and a thickness detection mechanism arranged on the wafer streamline conveying mechanism, and the front surface detection mechanism and the back surface detection mechanism are fixedly arranged on the wafer streamline conveying mechanism. The beneficial effects of the utility model are that the device can realize the function of simultaneously detecting the front and back surfaces of the silicon wafers in the process of moving on a streamline, and can ensure that each silicon wafer is completely detected; and the thickness detection of the wafer can be realized, the operation is convenient, and the use effect is good.
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Description

Technical Field

[0001] The utility model relates to the technical field of wafer detection, in particular to a silicon wafer front and back surface detection mechanism. Background Art

[0002] In the semiconductor silicon wafer manufacturing process, cylindrical silicon ingots are cut into countless stacked thin slices, namely wafers. The appearance and thickness of the wafers affect the subsequent wafer production. Before production, each wafer needs to be inspected for appearance, and defective wafers are removed. Then, the thickness of each wafer is classified according to different ranges.

[0003] Wafer inspection is usually divided into appearance inspection, thickness inspection, hidden crack inspection, etc. In appearance inspection, it is usually necessary to remove the wafers with defects and scratches on the surface. Currently, the inspection of whether the wafer has defects and scratches is usually performed by operators, which often results in missed inspections and false inspections, and is inefficient.

[0004] In view of the above situation, it is necessary to improve the existing wafer detection method so that it can adapt to the current needs of wafer processing. Utility Model Content

[0005] The utility model aims to solve the above problems and designs a silicon wafer front and back surface detection mechanism.

[0006] To achieve the above-mentioned purpose, the technical solution of the utility model is a silicon wafer front and back side detection mechanism, including a mounting frame, a wafer streamline conveying mechanism arranged on the mounting frame, a front side detection mechanism arranged above the wafer streamline conveying mechanism, a back side detection mechanism arranged below the wafer streamline conveying mechanism, and a thickness detection mechanism arranged on the wafer streamline conveying mechanism, wherein the front side detection mechanism and the back side detection mechanism are fixedly mounted on the wafer streamline conveying mechanism.

[0007] As a further supplement to the technical solution, the front detection mechanism is a CCD camera.

[0008] As a further supplement to the technical solution, the back surface detection mechanism is a CCD camera.

[0009] As a further supplement to the technical solution, the front detection mechanism and the back detection mechanism are arranged at an angle.

[0010] As a further supplement to the technical solution, a first light source mechanism is provided on the wafer streamline conveying mechanism on one side of the front detection mechanism, and the first light source mechanism is vertically arranged to the wafer streamline conveying mechanism.

[0011] As a further supplement to the technical solution, a second light source mechanism is provided below the wafer streamline conveying mechanism and located on one side of the reverse side detection mechanism, and the second light source mechanism is arranged parallel to the first light source mechanism.

[0012] As a further supplement to the technical solution, a limiting mechanism is also provided below the wafer streamline conveying mechanism, and the limiting mechanism is fixedly installed on the wafer streamline conveying mechanism.

[0013] As a further supplement to the technical solution, the limiting mechanism includes a bidirectional cylinder and a clamping block connected to the bidirectional cylinder, the upper end of the clamping block passes through the wafer streamline conveying mechanism and protrudes from its surface, and the clamping blocks on the front and rear sides are symmetrically arranged.

[0014] As a further supplement to the technical solution, the clamping block is arranged in an arc shape on a side close to the wafer.

[0015] The beneficial effect is that the utility model can realize the function of simultaneous detection of the front and back sides of the silicon wafer while it moves on the streamline, and can ensure full inspection of each silicon wafer; and can realize wafer thickness detection, with easy operation and good use effect. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 This is a schematic diagram of the overall structure of the utility model from a first angle;

[0017] Figure 2 This is a second angle overall structural diagram of the utility model;

[0018] Figure 3 This is a schematic diagram of the overall structure of the utility model from a third angle;

[0019] Figure 4 yes Figure 3 A partial enlarged view of middle A;

[0020] In the figure, 1. mounting frame; 2. wafer streamline conveying mechanism; 3. front side detection mechanism; 4. back side detection mechanism; 5. thickness detection mechanism; 6. first light source mechanism; 7. second light source mechanism; 8. limiting mechanism; 81. bidirectional cylinder; 82. clamping block. DETAILED DESCRIPTION

[0021] In order to make the technical solution more clear to those skilled in the art, Figure 1 -4 Detailed description of the technical solution of the utility model:

[0022] A silicon wafer front and back side detection mechanism comprises a mounting frame 1, a wafer streamline conveying mechanism 2 arranged on the mounting frame 1, a front side detection mechanism 3 arranged above the wafer streamline conveying mechanism 2, a back side detection mechanism 4 arranged below the wafer streamline conveying mechanism 2, and a thickness detection mechanism 5 arranged on the wafer streamline conveying mechanism 2, wherein the front side detection mechanism 3 and the back side detection mechanism 4 are fixedly mounted on the wafer streamline conveying mechanism 2, and the front side detection mechanism 3 and the back side detection mechanism 4 can detect the appearance of the wafer, wherein the detection positions of the front side detection mechanism 3 and the back side detection mechanism 4 are set at the middle position in the width direction of the wafer streamline conveying mechanism 2, wherein the wafer streamline conveying mechanism 2 is composed of two sections of conveying mechanisms, which are disconnected at the appearance detection position to provide space for the front side detection mechanism 3 and the back side detection mechanism, and preferably, the front side detection mechanism 3 is a CCD camera, and the back side detection mechanism 4 is a CCD camera.

[0023] As a further supplement to the technical solution, the front detection mechanism 3 and the back detection mechanism 4 are arranged at an angle.

[0024] In order to facilitate the front side detection mechanism 3 and the back side detection mechanism 4 to work better, a first light source mechanism 6 is provided on the wafer streamline conveying mechanism 2 at one side of the front side detection mechanism 3, and the first light source mechanism 6 is vertically arranged to the wafer streamline conveying mechanism 2, and a second light source mechanism 7 is provided below the wafer streamline conveying mechanism 2 at one side of the back side detection mechanism 4, and the second light source mechanism 7 is arranged parallel to the first light source mechanism 6.

[0025] In order to facilitate the thickness detection mechanism 5 to better detect the wafer thickness, a limit mechanism 8 is further provided under the wafer streamline conveying mechanism 2. The limit mechanism 8 is fixedly installed on the wafer streamline conveying mechanism 2. When the wafer moves to the position of the thickness detection mechanism 5, the limit mechanism 8 can limit and fix the wafer and pause moving on the wafer streamline conveying mechanism 2, so that the thickness detection mechanism 5 can better detect the thickness of the wafer. In detail, the limit mechanism 8 includes a two-way cylinder 81 and a clamping block 82 connected to the two-way cylinder 81. The upper end of the clamping block 82 passes through the wafer streamline conveying mechanism 2 and protrudes from its surface. The clamping blocks 82 on the front and rear sides are symmetrically arranged. The two-way cylinder 81 can control the clamping block 82 to move forward and backward, so as to adapt to wafers of various sizes. The operation is convenient and the use effect is good. In order to better protect and clamp the wafer, the clamping block 82 is arranged in an arc shape close to one side of the wafer.

[0026] The above technical solutions only reflect the preferred technical solutions of the technical solutions of the present utility model. Some changes that may be made to certain parts thereof by technicians in this technical field all reflect the principles of the present utility model and fall within the protection scope of the present utility model.

Claims

1. A silicon wafer front and back surface detection mechanism, characterized in that: The invention comprises a mounting frame (1), a wafer streamline conveying mechanism (2) arranged on the mounting frame (1), a front side detection mechanism (3) arranged above the wafer streamline conveying mechanism (2), a back side detection mechanism (4) arranged below the wafer streamline conveying mechanism (2), and a thickness detection mechanism (5) arranged on the wafer streamline conveying mechanism (2), wherein the front side detection mechanism (3) and the back side detection mechanism (4) are fixedly mounted on the wafer streamline conveying mechanism (2).

2. A silicon wafer front and back surface detection mechanism according to claim 1, characterized in that: The front detection mechanism (3) is a CCD camera.

3. A silicon wafer front and back surface detection mechanism according to claim 2, characterized in that: The back surface detection mechanism (4) is a CCD camera.

4. A silicon wafer front and back surface detection mechanism according to claim 3, characterized in that: The front side detection mechanism (3) and the back side detection mechanism (4) are arranged in an inclined manner.

5. The silicon wafer front and back surface detection mechanism according to claim 1, characterized in that: A first light source mechanism (6) is provided on the wafer streamline conveying mechanism (2) at one side of the front detection mechanism (3), and the first light source mechanism (6) is arranged vertically to the wafer streamline conveying mechanism (2).

6. A silicon wafer front and back surface detection mechanism according to claim 5, characterized in that: A second light source mechanism (7) is provided below the wafer streamline conveying mechanism (2) and on one side of the reverse side detection mechanism (4), and the second light source mechanism (7) is arranged in parallel with the first light source mechanism (6).

7. The silicon wafer front and back surface detection mechanism according to claim 1, characterized in that: A limiting mechanism (8) is also provided below the wafer streamline conveying mechanism (2), and the limiting mechanism (8) is fixedly mounted on the wafer streamline conveying mechanism (2).

8. A silicon wafer front and back surface detection mechanism according to claim 7, characterized in that: The limiting mechanism (8) comprises a bidirectional cylinder (81) and a clamping block (82) connected to the bidirectional cylinder (81); the upper end of the clamping block (82) passes through the wafer streamline conveying mechanism (2) and protrudes from the surface thereof; the clamping blocks (82) on the front and rear sides are symmetrically arranged.

9. A silicon wafer front and back surface detection mechanism according to claim 8, characterized in that: The clamping block (82) is arranged in an arc shape close to one side of the wafer.