Digital signal isolator and chip

Abstract

The utility model provides a digital signal isolator and a chip. The digital signal isolator comprises a transmitting circuit, a coupling transmission circuit and a receiving circuit which are connected in sequence, the sending circuit is used for receiving a digital signal, modulating the digital signal to obtain a modulation pulse signal, and transmitting the modulation pulse signal to the coupling transmission circuit; the coupling transmission circuit comprises a first capacitor, a second capacitor and a transformer which are connected in series; the capacitance value of the first capacitor is equal to the capacitance value of the second capacitor, a primary coil and a secondary coil of the transformer are respectively provided with a grounding end, and the grounding end of the primary coil and the grounding end of the secondary coil of the transformer are connected with the same ground; the modulation pulse signal is coupled and transmitted to a receiving circuit through the first capacitor, the second capacitor and the transformer; and the receiving circuit is used for demodulating the received modulation pulse signal to obtain an output signal. The voltage endurance capability and the CMTI performance of the digital signal isolator are improved.

Description

Technical Field

[0001] The present application relates to the field of signal processing, and in particular, to a digital signal isolator and a chip. Background Art

[0002] Digital signal isolators are devices that transmit digital signals in an electrically isolated state. They are widely used in fieldbuses in industrial network environments, automotive electronic systems, and medical equipment, especially in some harsh application environments. One of the primary reasons for using isolators is to eliminate noise; another important reason is to protect devices or people from the harm of high voltage.

[0003] Currently, common digital signal isolators include magnetic isolators and capacitive isolators. Among them, magnetic isolators often use polyimide as the isolation layer material. 20um polyimide can achieve an isolation withstand voltage of 5kV, but some application environments require an isolation withstand voltage of 5.7kV or higher. The common method is to increase the thickness of the isolation layer, but this also increases the spacing between the primary coil and the secondary coil of the on-chip transformer, which weakens the coupling ability of the on-chip transformer, resulting in a reduction in the amplitude of the coupled signal and possible decoding errors. Therefore, the withstand voltage of the magnetic isolator is affected by the isolation layer material and spacing, and it is difficult to meet higher application requirements. The common-mode transient immunity (CMTI) performance of the capacitive isolator is poor because both the signal to be transmitted and the common-mode transient voltage dV / dt are transmitted through capacitive coupling. When a CMTI event occurs, the receiving side completely receives the CMTI current, which will cause a large instantaneous change in the input common-mode voltage of the receiving circuit, making the comparison circuit on the receiving side invalid. If the CMTI performance of the capacitive isolator is to be improved, a complex CMTI circuit must be designed to suppress the common-mode voltage transient on the receiving side during the CMTI event, which requires sacrificing additional area and power consumption. At the same time, the large voltage change on the receiving side brings difficulty to the design of the receiving side comparator. In addition, the capacitive isolator is easily affected by the external electric field and it is difficult to meet the requirements of simultaneous transmission of signals and energy. Prior art "202120187018.2 Digital Signal Isolator, Package Shell and Electronic Device" proposes a digital isolator with a new coupled transmission structure. The on-chip capacitor and the on-chip transformer are connected in series to form a coupled transmission structure, and the on-chip capacitor and the parasitic capacitance of the on-chip transformer are connected in series to enhance the voltage resistance of the digital signal isolator. Compared with the capacitive isolator, this isolator can improve the CMTI performance of the isolator; compared with the magnetic isolator, it can improve the voltage resistance of the isolator. However, there is a design problem in the prior art. The on-chip capacitor is generally tens of fF, and the parasitic capacitance of the on-chip transformer is generally in the order of pF, which is much larger than the on-chip capacitor. If the on-chip capacitance is increased to the pF level, the area and cost will increase significantly; if the parasitic capacitance of the on-chip transformer is reduced to the fF level, the inductance and coupling coefficient of the on-chip transformer will be greatly reduced, resulting in the transformer coupling capability being too low to effectively transmit signals. Assuming that the capacitance CL of the on-chip transformer parasitic capacitance is 10 times the capacitance C0 of the on-chip capacitance, if the isolation materials of the on-chip capacitor and the on-chip transformer are both 20um polyimide, the withstand voltage limit of the on-chip capacitor is 5000V, and the withstand voltage limit of the on-chip transformer is also 5000V. However, according to the principle of capacitor series voltage division, C0 and CL are connected in series. When the withstand voltage value of C0 is 5000V, the withstand voltage value of CL is only 500V, that is, the withstand voltage value of the digital signal isolator is only 5500V.Therefore, the mismatch between the on-chip capacitor and the on-chip transformer parasitic capacitance results in the voltage withstand capability of the digital signal isolator being mainly determined by the voltage withstand bottleneck of the on-chip capacitor, that is, the isolation material and isolation layer thickness between the two plates of the on-chip capacitor, making it difficult to significantly improve the voltage withstand capability of the digital signal isolator.

[0004] Therefore, in view of the shortcomings of the existing technology, there is an urgent need for a digital signal isolator that can improve the voltage resistance and CMTI performance. Utility Model Content

[0005] The purpose of the embodiments of this article is to provide a digital signal isolator and a chip to improve the voltage resistance and CMTI performance.

[0006] To achieve the above-mentioned object, on the one hand, the embodiments of this document provide a digital signal isolator, including: a transmitting circuit, a coupling transmission circuit and a receiving circuit connected in sequence;

[0007] The transmitting circuit is used to receive a digital signal, modulate the digital signal to obtain a modulated pulse signal, and transmit the modulated pulse signal to a coupling transmission circuit;

[0008] The coupling transmission circuit comprises a first capacitor, a second capacitor and a transformer connected in series;

[0009] The capacitance of the first capacitor is equal to the capacitance of the second capacitor, the primary coil and the secondary coil of the transformer are both provided with a ground terminal, and the ground terminal of the primary coil and the ground terminal of the secondary coil of the transformer are connected to the same ground;

[0010] The modulated pulse signal is transmitted to the receiving circuit through the first capacitor, the second capacitor and the transformer coupling;

[0011] The receiving circuit is used for demodulating the received modulated pulse signal to obtain an output signal.

[0012] Preferably, one plate of the first capacitor is connected to the transmitting circuit, and the other plate of the first capacitor is connected to one plate of the second capacitor; the other plate of the second capacitor is connected to one port of the primary coil of the transformer, and the other port of the primary coil is the ground; one port of the secondary coil of the transformer is connected to the receiving circuit, and the other port of the secondary coil is the ground.

[0013] Preferably, the transmitting circuit includes a Schmitt trigger, an oscillator, a logic circuit, a first buffer and a first LDO circuit;

[0014] The Schmitt trigger receives a digital signal, shapes the digital signal to obtain a shaped signal, and transmits the shaped signal to the oscillator and the logic circuit in two paths;

[0015] The oscillator receives the shaped signal, and when the shaped signal is at a high level, modulates the shaped signal into an oscillation signal having a frequency higher than that of the shaped signal, and transmits the oscillation signal to the logic circuit;

[0016] The logic circuit operates the shaped signal and the oscillation signal to obtain an initial modulated pulse signal, and transmits the initial modulated pulse signal to the first buffer;

[0017] The first buffer receives the initial modulated pulse signal and outputs a modulated pulse signal;

[0018] The first LDO circuit supplies power to an oscillator, a logic circuit and a first buffer in the transmitting circuit.

[0019] Preferably, the receiving circuit includes a CMTI suppression circuit, a comparator, a second buffer and a second LDO circuit;

[0020] The non-inverting input terminal of the comparator receives the modulated pulse signal output by the port of the secondary coil of the transformer, and the inverting input terminal of the comparator is grounded;

[0021] The comparator demodulates the modulated pulse signal to obtain an initial output signal, and transmits the initial output signal to a second buffer;

[0022] The second buffer receives the initial output signal and outputs an output signal;

[0023] The CMTI suppression circuit is used to suppress common mode transient interference;

[0024] The second LDO circuit supplies power to the CMTI suppression circuit and the comparator in the receiving circuit.

[0025] Preferably, the coupling transmission circuit further includes a third capacitor and a fourth capacitor, and the third capacitor, the fourth capacitor and the transformer are connected in series;

[0026] The capacitance of the first capacitor, the capacitance of the second capacitor, the capacitance of the third capacitor and the capacitance of the fourth capacitor are all equal;

[0027] The transmitting circuit is used to receive a digital signal, modulate the digital signal to obtain a first modulated pulse signal and a second modulated pulse signal, and transmit the first modulated pulse signal and the second modulated pulse signal to a coupled transmission circuit respectively, wherein the first modulated pulse signal and the second modulated pulse signal are differential signals;

[0028] The first modulated pulse signal is transmitted to the receiving circuit through the first capacitor, the second capacitor and the transformer coupling, and the second modulated pulse signal is transmitted to the receiving circuit through the third capacitor, the fourth capacitor and the transformer coupling;

[0029] The receiving circuit is used to demodulate the received first modulated pulse signal and the second modulated pulse signal respectively to obtain output signals.

[0030] Preferably, one plate of the first capacitor is connected to an output end of the sending circuit, another plate of the first capacitor is connected to one plate of the second capacitor, and another plate of the second capacitor is connected to one port of the primary coil of the transformer; one plate of the third capacitor is connected to another output end of the sending circuit, another plate of the third capacitor is connected to one plate of the fourth capacitor, and another plate of the fourth capacitor is connected to another port of the primary coil of the transformer; both ports of the secondary coil of the transformer are connected to the receiving circuit;

[0031] The primary coil and the secondary coil of the transformer both adopt a center-tapped structure, and the center-tapped ends of the primary coil and the secondary coil are grounded.

[0032] Preferably, the transmitting circuit includes a Schmitt trigger, an oscillator, a logic circuit, a first buffer, an inverter and a first LDO circuit;

[0033] The Schmitt trigger receives a digital signal, shapes the digital signal to obtain a shaped signal, and transmits the shaped signal to the oscillator and the logic circuit in two paths;

[0034] The oscillator receives the shaped signal, and when the shaped signal is at a high level, modulates the shaped signal into an oscillation signal having a frequency higher than that of the shaped signal, and transmits the oscillation signal to the logic circuit;

[0035] The logic circuit operates the shaping signal and the oscillation signal to obtain an initial modulated pulse signal, and transmits the initial modulated pulse signal in two paths to the first buffer and the inverter respectively;

[0036] The first buffer receives the initial modulated pulse signal and outputs a first modulated pulse signal, and the inverter receives the initial modulated pulse signal and outputs a second modulated pulse signal;

[0037] The first LDO circuit supplies power to an oscillator, a logic circuit, a first buffer and an inverter in the transmitting circuit.

[0038] Preferably, the receiving circuit includes a CMTI suppression circuit, a comparator, a second buffer and a second LDO circuit;

[0039] The non-inverting input terminal of the comparator receives the first modulated pulse signal outputted from the port of the secondary coil of the transformer, and the inverting input terminal of the comparator receives the second modulated pulse signal outputted from the port of the secondary coil of the transformer;

[0040] The comparator demodulates the first modulated pulse signal and the second modulated pulse signal to obtain an initial output signal, and transmits the initial output signal to a second buffer;

[0041] The second buffer receives the initial output signal and outputs an output signal;

[0042] The CMTI suppression circuit is used to suppress common mode transient interference;

[0043] The second LDO circuit supplies power to the CMTI suppression circuit and the comparator in the receiving circuit.

[0044] The embodiment of the present invention further provides a transmitting chip, which is applied to any of the digital signal isolators described above;

[0045] The transmitting chip includes: a transmitting circuit, and a first capacitor in a coupling transmission circuit;

[0046] Alternatively, the transmitting chip includes: a transmitting circuit, and a first capacitor and a third capacitor in a coupling transmission circuit.

[0047] The embodiment of the present invention further provides a receiving chip, which is applied to any of the digital signal isolators described above;

[0048] The receiving chip includes: a receiving circuit, and a second capacitor and a transformer in a coupling transmission circuit;

[0049] Alternatively, the receiving chip includes: a receiving circuit, and a second capacitor, a fourth capacitor and a transformer in a coupling transmission circuit.

[0050] The embodiment of the present invention also provides a digital signal isolator chip, including the transmitting chip and the receiving chip.

[0051] It can be seen from the technical solutions provided in the embodiments of this invention that the capacitance of the first capacitor and the capacitance of the second capacitor are equal in the embodiments of this invention, so that the withstand voltage capability of the digital signal isolator is determined by the withstand voltage bottleneck of the first capacitor or the second capacitor, thereby obtaining a high withstand voltage. The grounding terminal of the primary coil of the transformer and the grounding terminal of the secondary coil are connected to the same ground, so that the transformer only participates in the discharge of CMTI and does not participate in the isolation withstand voltage, so as to improve the CMTI performance of the digital signal isolator.

[0052] In order to make the above and other purposes, features and advantages of this article more obvious and easy to understand, the following specifically cites preferred embodiments and describes them in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0053] In order to more clearly illustrate the technical solutions in the embodiments of this article or the prior art, the drawings required for use in the embodiments or the prior art descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments of this article. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0054] Figure 1 A schematic diagram of the structural framework of a digital signal isolator provided in an embodiment of this invention is shown;

[0055] Figure 2 A schematic diagram of the structural framework of another digital signal isolator provided in an embodiment of this invention is shown;

[0056] Figure 3 A schematic diagram showing the structural details of a digital signal isolator provided in an embodiment of this invention is shown;

[0057] Figure 4 A schematic diagram showing the structural details of another digital signal isolator provided in an embodiment of this invention is shown;

[0058] Figure 5 A schematic diagram of node waveforms provided in the embodiments of this invention is shown;

[0059] Figure 6 A schematic diagram of the three-dimensional structure of a coupling transmission circuit provided in an embodiment of this invention is shown;

[0060] Figure 7 Another three-dimensional structural schematic diagram of the coupling transmission circuit provided in the embodiments of this document is shown;

[0061] Figure 8 Another three-dimensional structural schematic diagram of the coupling transmission circuit provided in the embodiments of this document is shown.

[0062] Description of the accompanying symbols:

[0063] 11. Upper plate;

[0064] 12. Lower plate;

[0065] 21. Primary coil;

[0066] 22. Secondary coil;

[0067] 30. Isolation layer;

[0068] 40. Isolation layer;

[0069] 50. Isolation layer;

[0070] 60. Substrate. DETAILED DESCRIPTION

[0071] The following will be combined with the drawings in the embodiments of this article to clearly and completely describe the technical solutions in the embodiments of this article. Obviously, the described embodiments are only part of the embodiments of this article, not all of the embodiments. Based on the embodiments of this article, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of this article.

[0072] It should be noted that the terms "first", "second", etc. in the specification and claims of this article and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of this article described here can be implemented in an order other than those illustrated or described here. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, device, product or equipment that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or equipment.

[0073] Reference Figure 1 , the embodiment of this article provides a digital signal isolator, including: a transmitting circuit, a coupled transmission circuit and a receiving circuit connected in sequence;

[0074] The transmitting circuit is used to receive a digital signal, modulate the digital signal to obtain a modulated pulse signal, and transmit the modulated pulse signal to a coupling transmission circuit;

[0075] The coupling transmission circuit comprises a first capacitor, a second capacitor and a transformer connected in series;

[0076] The capacitance of the first capacitor is equal to the capacitance of the second capacitor, the primary coil and the secondary coil of the transformer are both provided with a ground terminal, and the ground terminal of the primary coil and the ground terminal of the secondary coil of the transformer are connected to the same ground;

[0077] The modulated pulse signal is transmitted to the receiving circuit through the first capacitor, the second capacitor and the transformer coupling;

[0078] The receiving circuit is used for demodulating the received modulated pulse signal to obtain an output signal.

[0079] In the first embodiment of this article, the coupling transmission circuit is used to couple the modulated pulse signal to the receiving circuit. Ideally, the capacitance of the first capacitor is equal to the capacitance of the second capacitor to improve the withstand voltage of the digital signal isolator. Of course, in actual use, due to the influence of the process, there may be errors that cause the capacitance of the first capacitor to be not completely equal to the capacitance of the second capacitor. The grounding terminal of the primary coil of the transformer and the grounding terminal of the secondary coil are connected to the same ground, so that the transformer only participates in the discharge of CMTI and does not participate in the isolation withstand voltage to improve the CMTI performance of the digital signal isolator.

[0080] Specifically, refer to Figure 3 , one plate of the first capacitor C1 is connected to the sending circuit, and the other plate of the first capacitor C1 is connected to one plate of the second capacitor C2; the other plate of the second capacitor C2 is connected to one port of the primary coil of the transformer T1, and the other port of the primary coil is the ground; one port of the secondary coil of the transformer T1 is connected to the receiving circuit, and the other port of the secondary coil is the ground.

[0081] The first capacitor and the transmitting circuit are located in the same voltage domain, and the second capacitor, the transformer and the receiving circuit are located in the same voltage domain. In the coupled transmission structure, the voltage withstand capability of the digital signal isolator can be determined only by the first capacitor and the second capacitor connected in series. Since the capacitance of the first capacitor and the capacitance of the second capacitor are equal, the voltage withstand capability of the digital signal isolator is determined by the voltage withstand bottleneck of the first capacitor or the second capacitor, thereby obtaining a high voltage withstand capability. In addition, the secondary coil of the transformer located on the receiving circuit side forms a path to the ground, and is connected to the ground through the parasitic resistance of the secondary coil, so that a good CMTI effect can be achieved. When a CMTI event occurs, most of the generated CMTI current flows through the secondary coil of the transformer to the ground, and a small part of the current flows through the receiving circuit, so the common mode level of the receiving circuit changes very little, and the CMTI effect is good.

[0082] Specifically, the transmitting circuit includes a Schmitt trigger, an oscillator, a logic circuit, a first buffer and a first LDO circuit;

[0083] The Schmitt trigger receives a digital signal, shapes the digital signal to obtain a shaped signal, and transmits the shaped signal to the oscillator and the logic circuit in two paths;

[0084] The oscillator receives the shaped signal, and when the shaped signal is at a high level, modulates the shaped signal into an oscillation signal having a frequency higher than that of the shaped signal, and transmits the oscillation signal to the logic circuit;

[0085] The logic circuit operates the shaped signal and the oscillation signal to obtain an initial modulated pulse signal, and transmits the initial modulated pulse signal to the first buffer;

[0086] The first buffer receives the initial modulated pulse signal and outputs a modulated pulse signal;

[0087] The first LDO circuit supplies power to an oscillator, a logic circuit and a first buffer in the transmitting circuit.

[0088] The receiving circuit includes a CMTI suppression circuit, a comparator, a second buffer and a second LDO circuit;

[0089] The non-inverting input terminal of the comparator receives the modulated pulse signal output by the port of the secondary coil of the transformer, and the inverting input terminal of the comparator is grounded;

[0090] The comparator demodulates the modulated pulse signal to obtain an initial output signal, and transmits the initial output signal to a second buffer;

[0091] The second buffer receives the initial output signal and outputs an output signal;

[0092] The CMTI suppression circuit is used to suppress common mode transient interference;

[0093] The second LDO circuit supplies power to the CMTI suppression circuit and the comparator in the receiving circuit.

[0094] The input digital signal IN is shaped by the Schmitt trigger SMIT1 to obtain the shaped signal IN1. The first LDO circuit LDO1 supplies power to the oscillator, the logic circuit and the first buffer BUF1 in the sending circuit. The oscillator and the logic circuit receive the shaped signal IN1. When the shaped signal IN1 is at a high level, the oscillator oscillates to modulate the shaped signal IN1 into an oscillation signal with a higher frequency. The oscillation signal and the shaped signal IN1 are subjected to a logic operation by the logic circuit to obtain an initial modulated pulse signal. Generally speaking, the logic circuit is an AND gate. After the AND operation is performed, the initial modulated pulse signal passes through the first buffer BUF1 to obtain a modulated pulse signal A. The modulated pulse signal A is coupled and transmitted by the coupling transmission circuit to obtain a modulated pulse signal C.

[0095] The in-phase input terminal of the comparator CMP receives the modulated pulse signal C transmitted by the coupling transmission circuit, and the inverting input terminal of the comparator CMP is grounded. The modulated pulse signal C is demodulated by the comparator CMP to obtain the initial output signal OUT1, and the initial output signal OUT1 is passed through the second buffer BUF2 to obtain the output signal OUT, and the output signal OUT has a certain delay compared with the input digital signal IN. The second LDO circuit LDO2 supplies power to the comparator CMP and the CMTI suppression circuit, wherein the CMTI suppression circuit is used to further suppress common-mode transient interference and improve the CMTI performance of the digital signal isolator. The CMTI suppression circuit is arranged between the secondary coil of the transformer T1 and the comparator CMP, and one end of the CMTI suppression circuit is connected to a port of the secondary coil of the transformer T1, specifically the port where the secondary coil of the transformer T1 is connected to the receiving circuit, and the other end of the CMTI suppression circuit is grounded.

[0096] In the second embodiment of this article, referring to Figure 2 , in addition to the first capacitor C1 and the second capacitor C2, the coupling transmission circuit also includes a third capacitor C3 and a fourth capacitor C4, and the third capacitor C3, the fourth capacitor C4 and the transformer T1 are connected in series;

[0097] The capacitance of the first capacitor C1, the capacitance of the second capacitor C2, the capacitance of the third capacitor C3 and the capacitance of the fourth capacitor C4 are all equal;

[0098] The transmitting circuit is used to receive a digital signal, modulate the digital signal to obtain a first modulated pulse signal and a second modulated pulse signal, and transmit the first modulated pulse signal and the second modulated pulse signal to a coupled transmission circuit respectively, wherein the first modulated pulse signal and the second modulated pulse signal are differential signals;

[0099] The first modulated pulse signal is coupled and transmitted to the receiving circuit through the first capacitor C1, the second capacitor C2 and the transformer T1, and the second modulated pulse signal is coupled and transmitted to the receiving circuit through the third capacitor C3, the fourth capacitor C4 and the transformer T1;

[0100] The receiving circuit is used to demodulate the received first modulated pulse signal and the second modulated pulse signal respectively to obtain output signals.

[0101] Different from the first embodiment, the transmitting circuit is used to modulate the received digital signal to obtain a differential modulated pulse signal, the coupling transmission circuit is used to couple the differential modulated pulse signal to the receiving circuit, and the receiving circuit is used to demodulate the received differential pulse signal to obtain an output signal.

[0102] Specifically, refer to Figure 4 and Figure 5, one plate of the first capacitor is connected to an output end of the sending circuit, the other plate of the first capacitor is connected to one plate of the second capacitor, and the other plate of the second capacitor is connected to one port of the primary coil of the transformer; one plate of the third capacitor is connected to another output end of the sending circuit, the other plate of the third capacitor is connected to one plate of the fourth capacitor, and the other plate of the fourth capacitor is connected to another port of the primary coil of the transformer; both ports of the secondary coil of the transformer are connected to the receiving circuit;

[0103] The primary coil and the secondary coil of the transformer both adopt a center-tapped structure, and the center-tapped ends of the primary coil and the secondary coil are grounded.

[0104] Among them, the first capacitor, the third capacitor and the sending circuit in the coupling circuit are located in the same voltage domain, and the second capacitor, the fourth capacitor, the transformer and the receiving circuit are located in the same voltage domain.

[0105] The transmitting circuit includes a Schmitt trigger, an oscillator, a logic circuit, a first buffer, an inverter and a first LDO circuit;

[0106] The Schmitt trigger receives a digital signal, shapes the digital signal to obtain a shaped signal, and transmits the shaped signal to the oscillator and the logic circuit in two paths;

[0107] The oscillator receives the shaped signal, and when the shaped signal is at a high level, modulates the shaped signal into an oscillation signal having a frequency higher than that of the shaped signal, and transmits the oscillation signal to the logic circuit;

[0108] The logic circuit operates the shaping signal and the oscillation signal to obtain an initial modulated pulse signal, and transmits the initial modulated pulse signal in two paths to the first buffer and the inverter respectively;

[0109] The first buffer receives the initial modulated pulse signal and outputs a first modulated pulse signal, and the inverter receives the initial modulated pulse signal and outputs a second modulated pulse signal;

[0110] The first LDO circuit supplies power to an oscillator, a logic circuit, a first buffer and an inverter in the transmitting circuit.

[0111] The receiving circuit includes a CMTI suppression circuit, a comparator, a second buffer and a second LDO circuit;

[0112] The non-inverting input terminal of the comparator receives the first modulated pulse signal outputted from the port of the secondary coil of the transformer, and the inverting input terminal of the comparator receives the second modulated pulse signal outputted from the port of the secondary coil of the transformer;

[0113] The comparator demodulates the first modulated pulse signal and the second modulated pulse signal to obtain an initial output signal, and transmits the initial output signal to a second buffer;

[0114] The second buffer receives the initial output signal and outputs an output signal;

[0115] The CMTI suppression circuit is used to suppress common mode transient interference;

[0116] The second LDO circuit supplies power to the CMTI suppression circuit and the comparator in the receiving circuit.

[0117] The input digital signal IN is shaped by the Schmitt trigger SMIT1 to obtain the shaped signal IN1, and the first LDO circuit LDO1 supplies power to the oscillator, logic circuit, first buffer BUF1 and inverter INV1 in the sending circuit. The oscillator and the logic circuit receive the shaped signal IN1. When the shaped signal IN1 is at a high level, the oscillator oscillates to modulate the shaped signal IN1 into an oscillation signal with a higher frequency. The oscillation signal and the shaped signal IN1 are subjected to a logic operation of the logic circuit to obtain an initial modulated pulse signal. Generally speaking, the logic circuit is an AND gate. After the AND operation is performed, the initial modulated pulse signal is divided into two paths. One path passes through the first buffer BUF1 to obtain the first modulated pulse signal A, and the other path passes through the inverter INV1 to obtain the second modulated pulse signal B. The first modulated pulse signal A and the second modulated pulse signal B are differential signals. The first modulated pulse signal A and the second modulated pulse signal B are coupled and transmitted through the coupling transmission circuit to obtain the first modulated pulse signal C and the second modulated pulse signal D respectively.

[0118] The in-phase input terminal of the comparator CMP receives the first modulated pulse signal C transmitted by the coupling transmission circuit, and the inverting input terminal of the comparator CMP receives the second modulated pulse signal D transmitted by the coupling transmission circuit. After demodulation by the comparator CMP, an initial output signal OUT1 is obtained. The initial output signal OUT1 passes through the second buffer BUF2 to obtain an output signal OUT. The output signal OUT has a certain delay compared with the input digital signal IN. The second LDO circuit LDO2 supplies power to the comparator CMP and the CMTI suppression circuit in the receiving circuit, wherein the CMTI suppression circuit is used to further suppress common-mode transient interference and improve the CMTI performance of the isolator. The CMTI suppression circuit is arranged between the secondary coil of the transformer T1 and the comparator CMP, one end of the CMTI suppression circuit is connected to a port of the secondary coil of the transformer T1, and the other end of the CMTI suppression circuit is connected to another port of the secondary coil of the transformer T1. The port where the secondary coil is connected to the CMTI suppression circuit is not the center tap end.

[0119] The embodiment of the present invention further provides a transmitting chip, which is applied to the above-mentioned digital signal isolator;

[0120] The transmitting chip includes: a transmitting circuit, and a first capacitor in a coupling transmission circuit;

[0121] Alternatively, the transmitting chip includes: a transmitting circuit, and a first capacitor and a third capacitor in a coupling transmission circuit.

[0122] The embodiment of the present invention further provides a receiving chip, which is applied to the above-mentioned digital signal isolator;

[0123] The receiving chip includes: a receiving circuit, and a second capacitor and a transformer in a coupling transmission circuit;

[0124] Alternatively, the receiving chip includes: a receiving circuit, and a second capacitor, a fourth capacitor and a transformer in a coupling transmission circuit.

[0125] The embodiments of the present invention further provide a digital signal isolator chip, comprising the above-mentioned transmitting chip and the above-mentioned receiving chip.

[0126] Based on the second embodiment of the digital signal isolator in this article, refer to Figure 6 , the three-dimensional structure of the coupling transmission circuit can be obtained as follows: the lower plates 12 of the second capacitor C2 and the fourth capacitor C4 are in the same metal layer as the primary coil 21 of the transformer T1. The upper plates 11 of the second capacitor C2 and the fourth capacitor C4 are connected to the upper plates 11 of the first capacitor C1 and the third capacitor C3 respectively, the lower plates 12 of the first capacitor C1 and the third capacitor C3 are connected to the transmitting circuit, the lower plates 12 of the second capacitor C2 and the fourth capacitor C4 are connected to the primary coil 21 of the transformer T1, and the secondary coil 22 of the transformer T1 is connected to the receiving circuit.

[0127] The preparation process can be as follows:

[0128] First, a substrate 60 is prepared, and then an isolation layer 50 is prepared on the substrate, and the thickness of the isolation layer 50 can be set according to actual needs. Then, the secondary coil 22 of the transformer T1 is prepared on the isolation layer 50, and then an isolation layer 40 is prepared, and the thickness of the isolation layer 40 can be set according to actual needs.

[0129] During preparation, a metal layer may be prepared on the isolation layer 50 , and then the secondary coil 22 may be prepared by etching or the like to form a three-dimensional structure.

[0130] Then, the primary coil 21 of the transformer T1, the lower plates 12 of the second capacitor C2 and the fourth capacitor C4 are prepared on the isolation layer 40, and the lower plates 12 of the second capacitor C2 and the fourth capacitor C4 are connected to the primary coil 21 of the transformer T1 through a wire. Then, the isolation layer 30 is prepared, and the upper and lower plates of the second capacitor C2 and the fourth capacitor C4 are isolated by the isolation layer 30.

[0131] During preparation, a metal layer may be prepared on the isolation layer 40 , and then the lower electrode plate 12 and the primary coil 21 may be prepared by etching or the like to form a three-dimensional structure.

[0132] It should be understood that the thickness of the isolation layer between the upper and lower plates of the second capacitor C2 and the fourth capacitor C4 is t, and the thickness determines the withstand voltage value of the isolator. When the isolation material between the upper and lower plates of the second capacitor C2 and the fourth capacitor C4 is polyimide, if t is 20um, the withstand voltage capacity of the second capacitor C2 and the fourth capacitor C4 is at least 5kV. In the transmitting chip, the isolation material between the upper and lower plates of the capacitors C1 and C3 is also polyimide, and t is 20um, then the withstand voltage capacity of the first capacitor C1 and the third capacitor C3 is also at least 5kV. Since the capacitance of the first capacitor, the capacitance of the second capacitor, the capacitance of the third capacitor and the capacitance of the fourth capacitor are all equal, the withstand voltage capacity of the digital signal isolator is 10kV. The primary and secondary coil spacing of the transformer T1 is t1, which does not affect the withstand voltage capacity of the isolator, and can be specifically designed according to the actual application.

[0133] Reference Figure 7 The three-dimensional structure of the coupling transmission circuit can also be shown as follows: the upper plate 11 of the second capacitor C2 and the fourth capacitor C4 and the primary coil 21 of the transformer T1 are in the same metal layer, the lower plate 12 of the second capacitor C2 and the fourth capacitor C4 and the secondary coil 22 of the transformer T1 are in the same metal layer, the lower plate 12 of the second capacitor C2 and the fourth capacitor C4 are connected to the primary coil 21 of the transformer T1, and the secondary coil 22 of the transformer T1 is connected to the receiving circuit.

[0134] Reference Figure 8 The three-dimensional structure of the coupling transmission circuit can also be as follows: the upper plate 11 of the second capacitor C2 and the fourth capacitor C4 and the secondary coil 22 of the transformer T1 are in the same metal layer, the lower plate 12 of the second capacitor C2 and the fourth capacitor C4 and the primary coil 21 of the transformer T1 are in the same metal layer, the lower plate 12 of the second capacitor C2 and the fourth capacitor C4 are connected to the primary coil 21 of the transformer T1, and the secondary coil 22 of the transformer T1 is connected to the receiving circuit.

[0135] Specific embodiments are used in this article to illustrate the principles and implementation methods of this article. The description of the above embodiments is only used to help understand the methods and core ideas of this article. At the same time, for general technicians in this field, according to the ideas of this article, there will be changes in the specific implementation methods and application scopes. In summary, the content of this specification should not be understood as a limitation on this article.

Claims

1. A digital signal isolator, characterized in that: include: A transmitting circuit, a coupled transmission circuit and a receiving circuit connected in sequence; The transmitting circuit is used to receive a digital signal, modulate the digital signal to obtain a modulated pulse signal, and transmit the modulated pulse signal to a coupling transmission circuit; The coupling transmission circuit comprises a first capacitor, a second capacitor and a transformer connected in series; The capacitance of the first capacitor is equal to the capacitance of the second capacitor, the primary coil and the secondary coil of the transformer are both provided with a ground terminal, and the ground terminal of the primary coil and the ground terminal of the secondary coil of the transformer are connected to the same ground; The modulated pulse signal is transmitted to the receiving circuit through the first capacitor, the second capacitor and the transformer coupling; The receiving circuit is used for demodulating the received modulated pulse signal to obtain an output signal.

2. The digital signal isolator according to claim 1, characterized in that: One plate of the first capacitor is connected to the transmitting circuit, and the other plate of the first capacitor is connected to one plate of the second capacitor; the other plate of the second capacitor is connected to one port of the primary coil of the transformer, and the other port of the primary coil is the ground; one port of the secondary coil of the transformer is connected to the receiving circuit, and the other port of the secondary coil is the ground.

3. The digital signal isolator according to claim 2, characterized in that: The transmitting circuit includes a Schmitt trigger, an oscillator, a logic circuit, a first buffer and a first LDO circuit; The Schmitt trigger receives a digital signal, shapes the digital signal to obtain a shaped signal, and transmits the shaped signal to the oscillator and the logic circuit in two paths; The oscillator receives the shaped signal, and when the shaped signal is at a high level, modulates the shaped signal into an oscillation signal having a frequency higher than that of the shaped signal, and transmits the oscillation signal to the logic circuit; The logic circuit operates the shaped signal and the oscillation signal to obtain an initial modulated pulse signal, and transmits the initial modulated pulse signal to the first buffer; The first buffer receives the initial modulated pulse signal and outputs a modulated pulse signal; The first LDO circuit supplies power to an oscillator, a logic circuit and a first buffer in the transmitting circuit.

4. The digital signal isolator according to claim 2, characterized in that: The receiving circuit includes a CMTI suppression circuit, a comparator, a second buffer and a second LDO circuit; The non-inverting input terminal of the comparator receives the modulated pulse signal output by the port of the secondary coil of the transformer, and the inverting input terminal of the comparator is grounded; The comparator demodulates the modulated pulse signal to obtain an initial output signal, and transmits the initial output signal to a second buffer; The second buffer receives the initial output signal and outputs an output signal; The CMTI suppression circuit is used to suppress common mode transient interference; The second LDO circuit supplies power to the CMTI suppression circuit and the comparator in the receiving circuit.

5. The digital signal isolator according to claim 1, characterized in that: The coupling transmission circuit further includes a third capacitor and a fourth capacitor, and the third capacitor, the fourth capacitor and the transformer are connected in series; The capacitance of the first capacitor, the capacitance of the second capacitor, the capacitance of the third capacitor and the capacitance of the fourth capacitor are all equal; The transmitting circuit is used to receive a digital signal, modulate the digital signal to obtain a first modulated pulse signal and a second modulated pulse signal, and transmit the first modulated pulse signal and the second modulated pulse signal to a coupled transmission circuit respectively, wherein the first modulated pulse signal and the second modulated pulse signal are differential signals; The first modulated pulse signal is transmitted to the receiving circuit through the first capacitor, the second capacitor and the transformer coupling, and the second modulated pulse signal is transmitted to the receiving circuit through the third capacitor, the fourth capacitor and the transformer coupling; The receiving circuit is used to demodulate the received first modulated pulse signal and the second modulated pulse signal respectively to obtain output signals.

6. The digital signal isolator according to claim 5, characterized in that: One plate of the first capacitor is connected to an output end of the transmitting circuit, another plate of the first capacitor is connected to one plate of the second capacitor, and another plate of the second capacitor is connected to one port of the primary coil of the transformer; one plate of the third capacitor is connected to another output end of the transmitting circuit, another plate of the third capacitor is connected to one plate of the fourth capacitor, and another plate of the fourth capacitor is connected to another port of the primary coil of the transformer; both ports of the secondary coil of the transformer are connected to the receiving circuit; The primary coil and the secondary coil of the transformer both adopt a center-tapped structure, and the center-tapped ends of the primary coil and the secondary coil are grounded.

7. The digital signal isolator according to claim 6, characterized in that: The transmitting circuit includes a Schmitt trigger, an oscillator, a logic circuit, a first buffer, an inverter and a first LDO circuit; The Schmitt trigger receives a digital signal, shapes the digital signal to obtain a shaped signal, and transmits the shaped signal to the oscillator and the logic circuit in two paths; The oscillator receives the shaped signal, and when the shaped signal is at a high level, modulates the shaped signal into an oscillation signal having a frequency higher than that of the shaped signal, and transmits the oscillation signal to the logic circuit; The logic circuit operates the shaping signal and the oscillation signal to obtain an initial modulated pulse signal, and transmits the initial modulated pulse signal in two paths to the first buffer and the inverter respectively; The first buffer receives the initial modulated pulse signal and outputs a first modulated pulse signal, and the inverter receives the initial modulated pulse signal and outputs a second modulated pulse signal; The first LDO circuit supplies power to an oscillator, a logic circuit, a first buffer and an inverter in the transmitting circuit.

8. The digital signal isolator according to claim 7, characterized in that: The receiving circuit includes a CMTI suppression circuit, a comparator, a second buffer and a second LDO circuit; The non-inverting input terminal of the comparator receives the first modulated pulse signal outputted from the port of the secondary coil of the transformer, and the inverting input terminal of the comparator receives the second modulated pulse signal outputted from the port of the secondary coil of the transformer; The comparator demodulates the first modulated pulse signal and the second modulated pulse signal to obtain an initial output signal, and transmits the initial output signal to a second buffer; The second buffer receives the initial output signal and outputs an output signal; The CMTI suppression circuit is used to suppress common mode transient interference; The second LDO circuit supplies power to the CMTI suppression circuit and the comparator in the receiving circuit.

9. A transmitting chip, characterized in that: A digital signal isolator applied to any one of claims 1 to 8 above; The transmitting chip includes: a transmitting circuit, and a first capacitor in a coupling transmission circuit; Alternatively, the transmitting chip includes: a transmitting circuit, and a first capacitor and a third capacitor in a coupling transmission circuit.

10. A receiving chip, characterized in that: A digital signal isolator applied to any one of claims 1 to 8 above; The receiving chip includes: a receiving circuit, and a second capacitor and a transformer in a coupling transmission circuit; Alternatively, the receiving chip includes: a receiving circuit, and a second capacitor, a fourth capacitor and a transformer in a coupling transmission circuit.

11. A digital signal isolator chip, characterized in that: It includes the transmitting chip as described in claim 9 and the receiving chip as described in claim 10.

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