Semiconductor structure, semiconductor device and electronic device
By directly etching the electrode slot to the channel layer in the semiconductor structure, the poor conductivity caused by ohmic metal passing through the barrier layer is solved, and the high temperature requirement in the annealing process is reduced, thereby achieving more efficient conductivity and process efficiency.
Patent Information
- Application Number
- CN202420547979.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-03-20
- Publication Date
- 2025-03-25
- Estimated Expiration
- 2034-03-20
AI Technical Summary
In the prior art, ohmic metals need to pass through a non-conductive barrier layer in order to contact the channel layer, resulting in poor conductivity and a high-temperature annealing process that is close to the upper limit of the machine capacity.
A semiconductor structure is designed in which the electrode trough is directly etched to the channel layer, and the ohmic metal can be in direct contact with the channel layer without passing through the barrier layer, reducing voltage loss and no high-temperature annealing process is required.
By directly etching the electrode slot to the channel layer, voltage loss is reduced, and the high temperature requirement in the annealing process is reduced, thereby improving the conductivity and process efficiency of semiconductor devices.
Smart Images
Figure CN222674849U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the field of semiconductor structures, in particular to a semiconductor structure, a semiconductor device and an electronic device. Background Art
[0002] Conventional ohmic contact openings are etched into the barrier layer. Since the barrier layer itself is not conductive, the ohmic metal needs to undergo a thermal process after deposition to diffuse into the channel layer to form a two-dimensional electron gas before it can be conductive. This requires the selection of a thermal process with high temperature, long time and good stability. The thermal process temperature of 890°C is close to the upper limit of the machine capability (900°C), and since the ohmic metal needs to pass through the barrier layer, the conductivity is poor. Utility Model Content
[0003] The purpose of the present application is to provide a semiconductor structure, a semiconductor device and an electronic device.
[0004] According to a first aspect of an embodiment of the present utility model, a semiconductor structure is provided, the semiconductor structure comprising:
[0005] Passivation layer;
[0006] A barrier layer, wherein the barrier layer is disposed on one side of the passivation layer;
[0007] A channel layer, wherein the channel layer is disposed on a side of the barrier layer away from the passivation layer;
[0008] An electrode groove extends from the passivation layer to the channel layer.
[0009] In some embodiments, the electrode groove includes a side wall, a bottom wall, and a transition wall connecting the side wall and the bottom wall, and the transition wall is arranged to grow along a first direction, and the first direction is a direction from the bottom wall to the side wall.
[0010] In some embodiments, the transition wall is entirely disposed on the channel layer.
[0011] In some embodiments, the transition wall is at least partially disposed in the channel layer and extends to the barrier layer along a thickness direction.
[0012] In some embodiments, the year-on-year growth rates of the transition walls along the first direction are arranged to be the same.
[0013] In some embodiments, the transition wall is arranged to have a gradually increasing year-on-year growth rate along the first direction.
[0014] In some embodiments, the transition wall is arranged with a gradually decreasing year-on-year growth rate along the first direction.
[0015] In some embodiments, the thickness of the electrode groove on the channel layer is greater than or equal to 5 nm and less than or equal to 15 nm.
[0016] In some embodiments, the thickness of the electrode groove on the channel layer is 10 nm.
[0017] In some embodiments, the length of the electrode groove along the first direction is greater than or equal to 0.8 μm and less than or equal to 1.5 μm.
[0018] In some embodiments, the bottom of the electrode groove is entirely configured as a circular arc.
[0019] According to a second aspect of the embodiments of the present utility model, a semiconductor device is provided, wherein the semiconductor device comprises the semiconductor structure described in any one of the above embodiments.
[0020] According to a third aspect of the embodiments of the present utility model, an electronic device is provided, wherein the electronic device comprises the semiconductor device described in the above embodiments.
[0021] The beneficial technical effects brought about by the technical solution provided by the embodiment of the present application are:
[0022] Since the electrode groove of the present application is directly etched to the channel layer, the ohmic metal deposited in the electrode groove can directly contact the channel layer without passing through the barrier layer, thereby reducing the voltage loss. In addition, since there is no need to diffuse the deposited ohmic metal to the channel layer through a thermal process, there is no need to perform annealing at an excessively high temperature during the annealing process. In summary, the structure disclosed in the present application can reduce the voltage loss while reducing the high temperature requirement in the annealing process. BRIEF DESCRIPTION OF THE DRAWINGS
[0023] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.
[0024] Figure 1 It is a structural schematic diagram of a part of a semiconductor structure according to an embodiment of the utility model.
[0025] Figure 2 It is a schematic structural diagram of another part of a semiconductor structure according to an embodiment of the utility model.
[0026] Figure 3 It is a schematic structural diagram of another part of a semiconductor structure according to an embodiment of the present utility model.
[0027] Figure 4It is a schematic structural diagram of another part of a semiconductor structure according to an embodiment of the utility model.
[0028] Figure 5 It is a schematic structural diagram of another part of a semiconductor structure according to an embodiment of the utility model.
[0029] Figure 6 It is a schematic structural diagram of another part of a semiconductor structure according to an embodiment of the utility model.
[0030] Description of reference numerals:
[0031] Passivation layer 100
[0032] Barrier layer 200
[0033] Channel layer 300
[0034] Electrode tank 400
[0035] Side wall 410
[0036] Bottom wall 420
[0037] Transition wall 430
[0038] First direction X
[0039] Thickness direction Y DETAILED DESCRIPTION
[0040] Exemplary embodiments will be described in detail herein, examples of which are shown in the accompanying drawings. When the following description refers to the drawings, the same numbers in different drawings represent the same or similar elements unless otherwise indicated. The implementations described in the following exemplary embodiments do not represent all implementations consistent with the present application. Instead, they are merely examples of devices and methods consistent with some aspects of the present application as detailed in the appended claims.
[0041] The terms used in this application are only for the purpose of describing specific embodiments and are not intended to limit this application. Unless otherwise defined, the technical terms or scientific terms used in this application should be understood by people with ordinary skills in the field to which this application belongs. The words "one" or "one" and the like used in this application specification and claims do not indicate a quantitative limitation, but indicate the existence of at least one. "Multiple" means two or more. "Including" or "including" and the like mean that the elements or objects appearing in front of "including" or "including" include the elements or objects listed after "including" or "including" and their equivalents, and do not exclude other elements or objects. "Connected" or "connected" and the like are not limited to physical or mechanical connections, and can include electrical connections, whether direct or indirect. "On" and / or "below" and the like are only for the convenience of explanation, and are not limited to a position or a spatial orientation. The singular forms of "one", "said" and "the" used in this application specification and the attached claims are also intended to include plural forms, unless the context clearly indicates other meanings. It should also be understood that the term "and / or" used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items.
[0042] “At least one of A, B, and C” has the same meaning as “at least one of A, B, or C” and both include the following combinations of A, B, and C: A only, B only, C only, the combination of A and B, the combination of A and C, the combination of B and C, and the combination of A, B, and C.
[0043] “A and / or B” includes the following three combinations: A only, B only, and a combination of A and B.
[0044] The use of "adapted to" or "configured to" in this specification is meant to be open and inclusive language that does not exclude devices adapted or configured to perform additional tasks or steps.
[0045] The triangles, rectangles, trapezoids, pentagons or hexagons used in the specification and claims of this application are not in a strict sense, and may be approximate triangles, rectangles, trapezoids, pentagons or hexagons, etc. There may be some small deformations caused by tolerances, and there may be chamfers, arc edges and deformations.
[0046] The term "about" as used in the specification and claims of this application refers to a numerical value that is not strictly limited and allows for process and measurement errors.
[0047] The transistors used in the present application can be triodes, thin film transistors or field effect transistors or other devices with the same characteristics. In the embodiments of the present application, in order to distinguish the two electrodes of the transistor except the control electrode, one of the electrodes is called the first electrode and the other is called the second electrode.
[0048] In actual operation, when the transistor is a triode, the control electrode may be a base, the first electrode may be a collector, and the second electrode may be an emitter; or, the control electrode may be a base, the first electrode may be an emitter, and the second electrode may be a collector.
[0049] In actual operation, when the transistor is a thin film transistor or a field effect transistor, the control electrode can be a gate, the first electrode can be a drain, and the second electrode can be a source; or, the control electrode can be a gate, the first electrode can be a source, and the second electrode can be a drain.
[0050] Common power semiconductors generally include components such as a substrate layer, a buffer layer, a passivation layer 100, an insulating layer, a channel layer 300, a barrier layer 200, a gate layer, and an electrode.
[0051] The substrate layer is the basic material of the device and provides a reference structure for growing crystals. The buffer layer is used to alleviate lattice mismatch and reduce the impact of lattice mismatch to improve crystal quality. The passivation layer 100 is used to protect the surface from environmental oxidation, pollution, etc., to improve the stability and reliability of the device. The insulating layer is used to achieve electrical isolation in the device to prevent interference between different parts. The channel layer 300 is a common layer in field effect transistors (FETs) and is used to control carrier channels. The barrier layer 200 is usually used to limit the flow of charge carriers to achieve control of current. The gate layer is used to control the conductivity of the device and is an important component in the field effect transistor (FET). The electrode is used for electrical connection of the device to connect the device to the external circuit. These components play an important role in the manufacture of power semiconductor devices. They work together to form a complete semiconductor device structure.
[0052] When preparing semiconductor devices, forming an ohmic contact opening is a very critical step. The process of forming an ohmic contact opening generally includes the following steps: 1-Photolithography: Use photolithography technology to cover the surface of the semiconductor device with photoresist, and expose it through a mask to form the desired pattern; 2-Etching: Use an etching process to remove the semiconductor material in the area not protected by the photoresist to form an electrode groove 400 structure; 3-Metal deposition: Perform metal deposition on the electrode groove 400 structure to fill the electrode groove 400 and form an ohmic contact electrode; 4-Annealing: After metal deposition, perform heat treatment (annealing) to improve the contact quality between the metal and the semiconductor. Then form the source and drain of the semiconductor device.
[0053] refer to Figure 1 As shown, the ohmic contact opening is etched to the barrier layer 200. Since the barrier layer 200 itself is not conductive, the ohmic metal needs to undergo a thermal process after deposition to diffuse to the channel layer 300 to form a two-dimensional electron gas before it can be conductive. This requires the selection of a thermal process with high temperature, long time and good stability. The thermal process temperature of 890°C is close to the upper limit of the machine capability (900°C), and since the ohmic metal needs to pass through the barrier layer 200, the conductive performance is poor.
[0054] In order to improve the conductivity of semiconductor devices, the inventors made the following improvements:
[0055] refer to Figure 2 As shown, the present application discloses a semiconductor structure, which includes: a passivation layer 100, a barrier layer 200, a channel layer 300 and an electrode groove 400. The barrier layer 200 is arranged on one side of the passivation layer 100; the channel layer 300 is arranged on the side of the barrier layer 200 away from the passivation layer 100; and the electrode groove 400 extends from the passivation layer 100 to the channel layer 300.
[0056] Since the electrode groove 400 of the present application is directly etched to the channel layer 300, the ohmic metal deposited in the electrode groove 400 can directly contact the channel layer 300 without passing through the barrier layer 200, thereby reducing the voltage loss. In addition, since there is no need to diffuse the deposited ohmic metal to the channel layer 300 through a thermal process, there is no need to perform annealing at an excessively high temperature in the annealing process. In summary, the structure disclosed in the present application can reduce the voltage loss while reducing the high temperature requirement in the annealing process.
[0057] In this embodiment, an ALN layer is further provided between the passivation layer 100 and the barrier layer 200, and the ALN layer can be used as an insulating layer or an isolation layer, which plays a role of electrical isolation in the semiconductor structure, prevents interference between different parts, and improves the stability and reliability of the device.
[0058] The electrode groove 400 includes a side wall 410, a bottom wall 420, and a transition wall 430 connecting the side wall 410 and the bottom wall 420. Because the present application deepens the bottom of the original electrode groove 400 from the barrier layer 200 to the channel layer 300, it is difficult for the metal to completely contact the bottom of the electrode groove 400 during the metal deposition process, especially at the transition between the side wall 410 and the bottom wall 420. Figure 2 , Figure 3 , Figure 4 as well as Figure 5 As shown, in this embodiment, the transition wall 430 is arranged to be extended along a first direction X, and the first direction X is the direction from the bottom wall 420 to the side wall 410 .
[0059] The transition wall 430 is arranged to grow along the first direction X and includes: Figure 4 As shown, the transition wall 430 is arranged at the same year-on-year growth rate along the first direction X; Figure 5 As shown, the transition wall 430 is arranged along the first direction X with a year-on-year growth rate gradually increasing; Figure 6 As shown, the transition wall 430 is arranged with a gradually decreasing year-on-year growth rate along the first direction X. The above three methods can well enable the ohmic metal to fully contact with the bottom of the electrode groove 400 to obtain better conductive performance.
[0060] Since the transition wall 430 is set as a growth, the ohmic metal can directly contact and deposit with the transition wall 430 during the ohmic metal deposition process, thereby enabling the ohmic metal to fully contact with the bottom of the electrode groove 400 to obtain better conductive performance.
[0061] In addition, reference Figure 6 As shown, the bottom of the electrode groove 400 is entirely configured as an arc, which can also allow the ohmic metal to fully contact the bottom of the electrode groove 400 to obtain better conductivity.
[0062] In one embodiment, reference Figure 3-Figure 5 As shown, the transition wall 430 is entirely disposed on the channel layer 300. In this case, the transition wall 430 is not disposed across the film layer, thereby avoiding the problem of linking the two film layers and ensuring the stability of the semiconductor structure.
[0063] In one embodiment, the transition wall 430 is at least partially disposed in the channel layer 300 and extends along the thickness direction Y to the barrier layer 200 .
[0064] refer to Figure 1 and Figure 2As shown, the deepened portion of the partial electrode groove 400 also includes a partial barrier layer 200 structure, so extending the transition wall 430 along the thickness direction Y to the barrier layer 200 can prevent the ohmic metal from not completely contacting the channel layer 300 on the one hand, and also prevent the ohmic metal from not completely contacting the barrier layer 200 on the other hand.
[0065] The inventors have found through a large number of experiments that when the thickness of the electrode groove 400 on the channel layer 300 is too small, it is difficult for the ohmic metal to fully contact the channel layer 300; when the thickness of the electrode groove 400 on the channel layer 300 is too large, the electrode groove 400 occupies too much of the channel layer 300, thereby destroying the stability of the semiconductor structure. In this embodiment, the thickness of the electrode groove 400 on the channel layer 300 is set to be greater than or equal to 5nm, and less than or equal to 15nm. For example, the thickness of the electrode groove 400 on the channel layer 300 can be 5nm, 6nm, 7nm, 8nm, 9nm, 10nm, 11nm, 12nm, 13nm, 14nm, 15nm. Preferably, the thickness of the electrode groove 400 on the channel layer 300 is 10nm. Within this range, on the one hand, the ohmic metal can fully contact the channel layer 300, and on the other hand, the stability of the semiconductor structure will not be destroyed.
[0066] The inventor has found through a large number of experiments that when the length of the electrode groove 400 along the first direction X is too large, the electrode groove 400 will occupy too much space, thereby causing the overall volume of the semiconductor structure to increase; when the length of the electrode groove 400 along the first direction X is too small, it is difficult for the ohmic metal to be deposited at the bottom of the electrode groove 400 during the metal deposition step. In this embodiment, the length of the electrode groove 400 along the first direction X is set to be greater than or equal to 0.8 μm and less than or equal to 1.5 μm. For example, the length of the electrode groove 400 along the first direction X can be 0.8 μm, 0.9 μm, 1.0 μm, 1.1 μm, 1.2 μm, 1.3 μm, 1.4 μm, and 1.5 μm. Within this range, on the one hand, the overall volume of the semiconductor structure can be prevented from increasing, and on the other hand, the ohmic metal can be deposited at the bottom of the electrode groove 400 and fully contact the bottom of the electrode groove 400.
[0067] The present application also proposes a semiconductor device, which includes the semiconductor structure described in any one of the above embodiments. Therefore, the semiconductor device also has the advantages and functions of the above semiconductor structure.
[0068] The semiconductor devices proposed in this application generally include power electronic devices, radio frequency devices, optoelectronic devices, sensors and detection devices, and optical fiber communication devices. Among them, power electronic devices can be used to manufacture high-frequency and high-efficiency power switching devices, such as GaN FET (field effect transistor), which are used in power adapters, DC-DC converters, electric vehicle inverters, etc.; radio frequency devices are widely used in the radio frequency field, such as manufacturing radio frequency power amplifiers, transmitting devices of wireless communication base stations, etc., which can achieve high frequency, high power density and high temperature operation; optoelectronic devices can be used to manufacture high-brightness and high-efficiency optoelectronic devices such as LEDs (light-emitting diodes) and lasers; sensors and detection devices, such as photoelectric sensors, ultraviolet detectors, etc.; optical fiber communication devices are also used in the field of optical communication, and can manufacture lasers and light detectors for optical fiber communication.
[0069] In addition, the present application also proposes an electronic device, which includes the semiconductor device described in the above embodiment, and can be used in a charger or a car, for example.
[0070] In the present application, the structural embodiments and method embodiments may complement each other if they do not conflict.
[0071] The above description is intended to be illustrative rather than restrictive. For example, the above examples (or one or more of them) can be used in combination with each other. For example, those of ordinary skill in the art can use other embodiments when reading the above description. In addition, in the above-mentioned specific embodiments, various features can be grouped together to simplify the application. This should not be interpreted as a feature of an application that does not require protection being necessary for any claim. On the contrary, the subject matter of the present application may be less than all the features of the embodiments of a specific application. Thus, the following claims are incorporated into the specific embodiments as examples or embodiments, wherein each claim is independently used as a separate embodiment, and it is considered that these embodiments can be combined with each other in various combinations or arrangements. The scope of the present application should be determined with reference to the full scope of the equivalent forms of the attached claims and these claims.
[0072] The present application describes exemplary embodiments with reference to cross-sectional views and / or plan views that are idealized exemplary drawings. In the drawings, the thickness of layers and regions is exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are conceivable. Therefore, the exemplary embodiments should not be interpreted as being limited to the shapes of the regions shown in the present application, but include shape deviations due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shapes of regions of the device, and are not intended to limit the scope of the exemplary embodiments.
[0073] When describing some embodiments, the expressions "coupled" and "connected" and their derivatives may be used. For example, when describing some embodiments, the term "connected" may be used to indicate that two or more components are in direct physical or electrical contact with each other. For another example, when describing some embodiments, the term "coupled" may be used to indicate that two or more components are in direct physical or electrical contact. However, the term "coupled" or "communicatively coupled" may also refer to two or more components that are not in direct contact with each other, but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the contents of this document.
[0074] In the present application, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance. The terms "plurality" and "several" refer to two or more than two, unless otherwise clearly defined.
[0075] Those skilled in the art will readily appreciate other embodiments of the present application after considering the specification and practicing the disclosure of the present application. The present application is intended to cover any modification, use or adaptation of the present application, which follows the general principles of the present application and includes common knowledge or customary techniques in the art that are not disclosed in the present application. The specification and examples are intended to be exemplary only, and the true scope and spirit of the present application are indicated by the following claims.
[0076] It should be understood that the present application is not limited to the precise structures that have been described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present application is limited only by the appended claims.
Claims
1. A semiconductor structure, characterized in that: The semiconductor structure comprises: Passivation layer; A barrier layer, wherein the barrier layer is disposed on one side of the passivation layer; A channel layer, wherein the channel layer is disposed on a side of the barrier layer away from the passivation layer; An electrode groove extends from the passivation layer to the channel layer.
2. The semiconductor structure according to claim 1, wherein: The electrode groove comprises a side wall, a bottom wall and a transition wall connecting the side wall and the bottom wall. The transition wall is arranged to grow along a first direction, and the first direction is a direction from the bottom wall to the side wall.
3. The semiconductor structure according to claim 2, wherein: The transition walls are all arranged on the channel layer.
4. The semiconductor structure according to claim 2, wherein: The transition wall is at least partially disposed on the channel layer and extends to the barrier layer along a thickness direction.
5. The semiconductor structure according to claim 2, wherein: The transition walls are arranged at the same year-on-year growth rate along the first direction.
6. The semiconductor structure according to claim 2, wherein: The transition wall is arranged with a gradually increasing year-on-year growth rate along the first direction.
7. The semiconductor structure according to claim 2, wherein: The transition wall is arranged with a year-on-year growth rate gradually decreasing along the first direction.
8. The semiconductor structure according to claim 1, wherein: The thickness of the electrode groove on the channel layer is greater than or equal to 5 nm and less than or equal to 15 nm.
9. The semiconductor structure according to claim 8, characterized in that The thickness of the electrode groove on the channel layer is 10 nm.
10. The semiconductor structure according to claim 1, wherein: The length of the electrode groove along the first direction is greater than or equal to 0.8 μm and less than or equal to 1.5 μm.
11. The semiconductor structure according to claim 1, wherein: The bottom of the electrode groove is entirely configured as an arc.
12. A semiconductor device, characterized in that: The semiconductor device comprises the semiconductor structure according to any one of claims 1 to 11.
13. An electronic device, characterized in that: The electronic device includes the semiconductor device according to claim 12.