Multi-channel signal memory based on FPGA (Field Programmable Gate Array) chip
By introducing a cache module and a retransmission control module into the multiple signal memory, the problem of data interruption or loss during the switching of the storage module is solved, and data integrity and continuity are achieved.
Patent Information
- Application Number
- CN202421512955.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-06-28
- Publication Date
- 2025-03-28
- Estimated Expiration
- 2034-06-28
AI Technical Summary
During the switching of the storage module, data may be interrupted or lost, and subsequent data flow and garbled code may occur.
A multi-channel signal memory based on FPGA chip is designed, including a cache module and a retransmission control module. Data is temporarily stored through the cache module, and under the control of the switching module, the integrity and continuity of the data during the switching process is ensured.
It effectively avoids interruption or loss of data during the switching of storage modules, ensures data integrity and continuity, and avoids subsequent data flow garbled code.
Smart Images
Figure CN222690155U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the technical field of memory, in particular to a multi-channel signal memory based on an FPGA chip. Background Art
[0002] A memory is an electronic device that stores data. It can store or retrieve information at a specified location according to instructions. In order to increase the read and write speed of the memory, existing memories often use multi-channel signal parallel processing to allow a large amount of data to be input into the memory module of the memory at the same time. However, the continuous transmission of a large amount of data puts the memory module at a higher risk of failure. In order to deal with the above problems, the general solution is to set up multiple storage modules inside the memory. This design not only increases the capacity of the memory, but also if a storage module has a problem, the switching module will start another storage module, thereby ensuring continuous and stable transmission of data.
[0003] However, during the process of starting another storage module, some data may be in the data transmission state. If the storage module is forcibly switched to another storage module, it may cause a short data interruption or loss, and the subsequent data flow may be garbled. Therefore, it is extremely important to solve the problem of maintaining data integrity during the storage module switching process. Utility Model Content
[0004] The purpose of the present application is to provide a multi-channel signal storage device based on an FPGA chip, which solves the technical problem of maintaining data integrity during the switching process of the storage module.
[0005] In order to solve the above technical problems, the solution adopted by this application is as follows:
[0006] The utility model provides a multi-channel signal memory based on FPGA chip, comprising a memory, a processor, a main storage module, a backup storage module, and a switching module arranged inside the memory, wherein the processor transmits processed data to the main storage module or the backup storage module connected thereto, and the processor controls the main storage module and the backup storage module to work respectively through the switching module; the utility model is characterized in that: it also comprises a cache module and a retransmission control module, and the cache module is connected to the switching module and the processor respectively;
[0007] The start control input terminal of the cache module is connected to the switching module, and the processor controls the operation of the cache module through the switching module;
[0008] The cache module includes a plurality of registers for temporarily storing data, and the data input end of the register is connected to the data output end of the processor;
[0009] An input end of the retransmission control module is connected to the end signal output end of the buffer module, and an output end of the retransmission control module and an output end of the retransmission module are connected to a retransmission signal receiving end of the processor.
[0010] In some embodiments, the switching module includes a cache startup module and a backup startup module, an input end of the cache startup module is connected to the control signal output end of the processor, a second input end of the cache startup module is connected to the fault signal output end of the main storage module, a third input end of the cache startup module is connected to the output end of the backup startup module; a fourth input end of the cache startup module is connected to the end signal output end of the cache module; and the output end of the cache startup module is connected to the startup control input end of the cache module.
[0011] In some embodiments, one input terminal of the backup startup module is connected to the fault signal output terminal of the main storage module; the second input terminal of the backup startup module is connected to the control signal output terminal of the processor; the third input terminal of the backup startup module is connected to the output terminal of the cache startup module; the fourth input terminal of the backup startup module is connected to the end signal output terminal of the cache module; the fifth input terminal of the backup startup module is connected to a low level; and the output terminal of the backup startup module is connected to the startup control input terminal of the backup module.
[0012] In some embodiments, the retransmission control module is also provided with two input terminals, three input terminals, and an output terminal, the two input terminals are connected to the verification signal output terminal of the main storage module, the three input terminals are connected to the verification signal output terminal of the backup storage module; the output terminal is connected to the signal receiving terminal of the processor.
[0013] In some embodiments, the external signal transmission interface of the processor serves as an external interface of the memory and is connected to a signal transmission interface of an external device.
[0014] In some embodiments, the processor includes a main control chip, and the main control chip is a FPGA chip.
[0015] In some embodiments, the FPGA chip processes data in parallel and transmits the processed data to a main storage module, a backup storage module, or a cache module.
[0016] The technical solution of the present application has at least the following advantages and beneficial effects:
[0017] 1. The utility model is provided with a cache module. In the process of switching from the main storage module to the backup storage module, the processor first transmits the data to the cache module. After the cache module completes data reception, the switching module starts the backup storage module. At the same time, the switching module sends an instruction to the processor to let the processor resend the data. At this time, the resent data is directly transmitted to the backup module, thereby ensuring the integrity and continuity of the data received by the backup storage module.
[0018] 2. The processor in the utility model includes an FPGA chip, which can process a large amount of data in parallel, thereby improving the speed of data processing. BRIEF DESCRIPTION OF THE DRAWINGS
[0019] Figure 1 It is a schematic diagram of the overall structure of the utility model.
[0020] Figure 2 This is a logic diagram of the retransmission control module of the present utility model.
[0021] Figure 3 This is a logic diagram of the cache startup module of the present utility model.
[0022] Figure 4 This is the logic diagram of the standby startup module of the utility model. DETAILED DESCRIPTION
[0023] The following will be combined with the drawings in the embodiments of the utility model to clearly and completely describe the technical solutions in the embodiments of the utility model. Obviously, the described embodiments are only part of the embodiments of the utility model, not all of the embodiments. Based on the embodiments in the utility model, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the utility model.
[0024] It should be noted that similar numbers and letters represent similar items in the following figures, so once an item is defined in one figure, it does not need to be further defined and explained in the subsequent figures. If the terms "center", "upper", "lower", "inner", "outer", etc. indicate an orientation or position relationship based on the orientation or position relationship shown in the figure, or the orientation or position relationship in which the product of the application is usually placed when in use, it is only for the convenience of describing the present application and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation of the present application. It should also be noted that unless otherwise clearly specified and limited, if the terms "set", "install", and "connect" appear, they should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be directly connected, or indirectly connected through an intermediate medium, or it can be a connection between the two elements. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.
[0025] Example 1
[0026] Please refer to Figure 1-Figure 4 , the utility model provides a multi-channel signal memory based on FPGA chip, which is the same as the prior art, including a memory, a processor arranged inside the memory, a main storage module, a backup storage module, and a switching module;
[0027] The external signal transmission interface of the processor is used as the external interface of the memory, and is connected to the signal transmission interface of the external device, and is used to receive data from the external device. The processed data is transmitted by the data transmission end of the processor to the main storage module or the backup storage module connected thereto for storage; the processor is connected to the switching module, and sends a control signal to the switching module, and controls the main storage module or the backup storage module to work through the switching module;
[0028] The processor is also provided with a signal receiving end, and the signal receiving end is connected with the switching module.
[0029] It should be noted that the processor includes a main control chip, which is an FPGA chip. The FPGA chip can process a large amount of data in parallel, thereby improving the speed of data processing.
[0030] The control end of the main storage module is connected to the output end of the switching module. After receiving the control signal transmitted by the processor, the switching module outputs the control signal to the main storage module, and the main storage module starts working; if the main storage module fails, the main storage module sends a fault signal from the fault signal output end to the switching module connected to it; if the main storage module has data errors when storing data, the main storage module outputs a check signal from the check signal output end to the switching module.
[0031] The control end of the backup storage module is connected to the output end of the switching module. After receiving the control signal transmitted by the processor, the switching module outputs the control signal to the backup storage module, and the backup storage module starts working; if the backup storage module has data errors when storing data, the backup storage module outputs a check signal from the check signal output end to the switching module.
[0032] It should be noted that the primary storage module takes precedence over the backup storage module. During the normal operation of the primary storage module, the backup storage module will not be started.
[0033] The switching module is used to switch between the main storage module and the backup storage module, and its control input end is connected to the control signal output end of the processor, and its output end is connected to the control end of the main storage module and the control end of the backup storage module.
[0034] Different from the prior art, the present invention further comprises a cache module, which comprises a plurality of registers for temporarily storing data, wherein the data input end of the register is connected to the data output end of the processor; the control end and the end signal output end of the cache module are respectively connected to the switching module;
[0035] In the process of switching from the main storage module to the backup storage module, the switching module first starts the cache module, and the processor transmits data to the cache module; after the cache module completes data reception, it sends an end signal to the switching module, and the switching module then starts the backup storage module and shuts down the cache module at the same time. The switching module sends an instruction to the processor to let the processor resend the data. At this time, the resent data is directly transmitted to the backup module, thereby ensuring the integrity and continuity of the data received by the backup storage module.
[0036] In order to facilitate the understanding of the switching process, the connection relationship of some modules in the switching module is now explained:
[0037] The switching module includes a cache startup module, a standby startup module, and a retransmission control module;
[0038] One input end of the cache startup module is connected to the control signal output end of the processor, the second input end of the cache startup module is connected to the fault signal output end of the main storage module, the third input end of the cache startup module is connected to the output end of the standby startup module; the fourth input end of the cache startup module is connected to the end signal output end of the cache module; the output end of the cache startup module is connected to the startup control input end of the cache module;
[0039] Specifically, Figure 3 As shown, the cache activation module includes NOT gates U5 and U13, and AND gates U1, U2, and U3;
[0040] Further, in the cache startup module, pin 1 of the AND gate U1 is set to the IN1 input terminal, and the IN1 input terminal is one input terminal of the cache startup module; pin 1 of the AND gate U2 is set to the IN2 input terminal, and the IN2 input terminal is the second input terminal of the cache startup module; pin 1 of the NOT gate U5 is set to the IN3 input terminal, and the IN3 input terminal is the third input terminal of the cache startup module, and pin 2 of the NOT gate U5 is connected to pin 2 of the AND gate U2; pin 1 of the NOT gate U13 is set to the IN4 input terminal, and the IN4 input terminal is the fourth input terminal of the cache startup module; pin 2 of the AND gate U1, pin 3 of the AND gate U2, and pin 3 of the AND gate U4 are connected, and pin 3 of the AND gate U1 is connected to pin 2 of the AND gate U4, and an OUT1 output terminal is set here, and the OUT1 output terminal is the output terminal of the cache startup module.
[0041] One input end of the standby startup module is connected to the fault signal output end of the main storage module; the second input end of the standby startup module is connected to the control signal output end of the processor; the third input end of the standby startup module is connected to the output end of the cache startup module; the fourth input end of the standby startup module is connected to the end signal output end of the cache module; the fifth input end of the standby startup module is connected to a low level; the output end of the standby startup module is connected to the startup control input end of the standby module.
[0042] Specifically, Figure 4 As shown, the standby startup module includes OR gates U8 and U12, and AND gates U9, U10, and U11;
[0043] Further, in the standby startup module, pin 2 of the OR gate U8 is set to the IN8 input terminal, and the IN8 input terminal is one input terminal of the standby startup module; pin 3 of the OR gate U8 is connected to pin 1 of the AND gate U9, and pin 2 of the AND gate U9 is set to the IN9 input terminal, and the IN9 input terminal is the second input terminal of the standby startup module; pin 3 of the AND gate U9 is connected to pin 1 of the AND gate U10; pin 1 of the AND gate U11 is set to the IN10 input terminal, and the IN10 input terminal is the third input terminal of the standby startup module, and pin 2 of the AND gate U11 is set to the IN11 input terminal, and the IN11 input terminal serves as the fourth input terminal of the standby startup module; pin 3 of the AND gate U11, pin 2 of the AND gate U10, and pin 3 of the OR gate U12 are connected; pin 1 of the OR gate U12 is set to the IN12 input terminal, and pin 2 of the OR gate U12, pin 1 of the OR gate U8, and pin 3 of the AND gate U10 are connected, and the OUT1 output terminal is set here, and the OUT1 output terminal is the output terminal of the standby startup module.
[0044] The retransmission control module is provided with three input terminals and one output terminal, wherein one input terminal is connected to the end signal output terminal of the cache module, the second input terminal is connected to the check signal output terminal of the main storage module, and the third input terminal is connected to the check signal output terminal of the backup storage module; the output terminal of the retransmission control module is connected to the signal receiving terminal of the processor.
[0045] Specifically, Figure 2 As shown, the retransmission control module includes OR gates U6 and U7;
[0046] Further, in the retransmission control module, pin 1 of the OR gate U7 is set to the IN5 input terminal, which is one input terminal of the retransmission control module; pin 1 of the OR gate U6 is set to the IN6 input terminal, which is the second input terminal of the retransmission control module; pin 1 of the OR gate U6 is set to the IN7 input terminal, which is the third input terminal of the retransmission control module; pin 3 of the OR gate U6 is connected to pin 2 of the OR gate U7, and the output terminal of pin 3 of the OR gate U7 is set to the OUT2 output terminal, which is the output terminal of the retransmission control module.
[0047] To facilitate understanding of the switching process, the operation modes of the cache startup module, the standby startup module, and the retransmission control module are described below:
[0048] When the main storage module fails, the IN1 input terminal of the buffer startup module continues to receive the control signal of the processor, that is, the IN1 input terminal continues to be at a high level, which can also be expressed as the pin 1 of the AND gate U1 continues to be at a high level;
[0049] The IN2 input terminal receives the fault signal sent by the main storage module, that is, the IN2 input terminal inputs a high level; at this time, the backup storage module has not yet started, that is, the backup startup module outputs a low level to the IN3 input terminal, and this low level passes through the NOT gate U5 and outputs a high level to the AND gate U2. Both input terminals of the AND gate U2 are high levels. At this time, the AND gate U2 outputs a high level to the pin 2 of the AND gate U1;
[0050] When both input terminals of AND gate U1 are high level, the output terminal of AND gate U1 outputs high level. At this time, the output terminal OUT1 outputs high level to the cache module, and the cache module starts to work. At this time, the pin 2 of AND gate U4 changes from low level to high level.
[0051] At this time, the cache module has not sent an end signal to the cache start module, that is, the IN4 input of the cache start module receives the low level continuously output by the end signal output of the cache module, and passes through the NOT gate U13, and the pin 1 of the AND gate U4 continuously receives the high level. At this time, the two inputs of the AND gate U4 are both high levels, and the AND gate U4 outputs a high level and contacts the pin 2 of the AND gate U1. At this time, the self-locking state is completed. When the cache module sends an end signal to the cache start module, that is, when the IN4 input of the cache start module receives the high level output by the end signal output of the cache module, the self-locking state will be released and the cache module will be closed.
[0052] When the main storage module fails and the cache module is in operation, the IN8 input terminal of the standby startup module receives the fault signal of the main storage module, that is, the IN1 input terminal continuously inputs a high level, which can also be represented as the pin 2 of the OR gate U8 inputting a high level. At this time, no matter the pin 1 of the OR gate U8 is a high level or a low level, the OR gate U8 outputs a high level to the pin 1 of the AND gate U9;
[0053] The IN9 input terminal continues to receive the high level sent by the processor. At this time, both input terminals of the AND gate U9 are high level, and the AND gate U9 outputs a high level to the pin 1 of the AND gate U10.
[0054] At this time, the OUT1 output terminal of the cache startup module outputs a high level to the IN10 input terminal, that is, the pin 1 of the AND gate U11 is at a high level; when the IN11 input terminal receives the high level output by the end signal output terminal of the cache module, the two input terminals of the AND gate U11 are only at high levels, and the AND gate U11 outputs a high level at this time;
[0055] At this time, the two input ends of the AND gate U10 are at a high level, and the output end of the AND gate U10 outputs a high level, and the standby module is started; at this time, pin 1 of the OR gate U8 and pin 2 of the OR gate U12 both receive a high level, and the self-locking state is completed; IN12 continuously inputs a low level.
[0056] The IN5 input terminal in the retransmission control module receives the check signal from the main storage module, that is, the IN5 input terminal is at a high level. At this time, no matter whether the pin 2 of the OR gate U7 is at a high level or a low level, the retransmission control module outputs a high level, that is, the retransmission control module outputs a control signal to the processor, requiring the processor to resend the data;
[0057] The IN6 input terminal receives the check signal of the standby main storage module, that is, the IN6 input terminal is at a high level. At this time, no matter whether the pin 2 of the OR gate U6 is at a high level or a low level, no matter whether the pin 1 of the OR gate U7 is at a high level or a low level, the retransmission control module outputs a high level, that is, the retransmission control module outputs a control signal to the processor, requiring the processor to resend the data;
[0058] The IN7 input terminal receives the end signal of the cache module, that is, a high level. At this time, no matter whether the pin 2 of the OR gate U6 is a high level or a low level, and no matter whether the pin 1 of the OR gate U7 is a high level or a low level, the retransmission control module outputs a high level, that is, the retransmission control module outputs a control signal to the processor, requiring the processor to resend the data.
[0059] So far, various embodiments of the present invention have been described in detail. In order to avoid obscuring the concept of the present invention, some details known in the art are not described. Based on the above description, those skilled in the art can fully understand how to implement the technical solution of the present invention, and the scope of the present invention is defined by the attached claims.
Claims
1. A multi-channel signal memory based on an FPGA chip, comprising a memory, a processor, a main storage module, a backup storage module, and a switching module arranged inside the memory, wherein the processor transmits processed data to the main storage module or the backup storage module connected thereto, and the processor controls the main storage module and the backup storage module to work respectively through the switching module; characterized in that: It also includes a cache module and a retransmission control module, wherein the cache module is connected to the switching module and the processor respectively; The start control input terminal of the cache module is connected to the switching module, and the processor controls the operation of the cache module through the switching module; The cache module includes a plurality of registers for temporarily storing data, and the data input end of the register is connected to the data output end of the processor; An input end of the retransmission control module is connected to the end signal output end of the buffer module, and an output end of the retransmission control module and an output end of the retransmission control module are connected to the retransmission signal receiving end of the processor.
2. The multi-channel signal memory based on FPGA chip according to claim 1, characterized in that: The switching module includes a cache startup module and a backup startup module, wherein one input end of the cache startup module is connected to the control signal output end of the processor, the second input end of the cache startup module is connected to the fault signal output end of the main storage module, the third input end of the cache startup module is connected to the output end of the backup startup module; the fourth input end of the cache startup module is connected to the end signal output end of the cache module; and the output end of the cache startup module is connected to the startup control input end of the cache module.
3. The multi-channel signal memory based on FPGA chip according to claim 2, characterized in that: One input end of the standby startup module is connected to the fault signal output end of the main storage module; the second input end of the standby startup module is connected to the control signal output end of the processor; the third input end of the standby startup module is connected to the output end of the cache startup module; the fourth input end of the standby startup module is connected to the end signal output end of the cache module; the fifth input end of the standby startup module is connected to a low level; the output end of the standby startup module is connected to the startup control input end of the standby module.
4. The multi-channel signal memory based on FPGA chip according to claim 1, characterized in that: The retransmission control module is also provided with two input terminals, three input terminals and an output terminal. The two input terminals are connected to the verification signal output terminal of the main storage module, and the three input terminals are connected to the verification signal output terminal of the backup storage module; the output terminal is connected to the signal receiving terminal of the processor.
5. The multi-channel signal memory based on FPGA chip according to claim 1, characterized in that: The external signal transmission interface of the processor serves as an external interface of the memory and is connected to a signal transmission interface of an external device.
6. The multi-channel signal memory based on FPGA chip according to claim 1, characterized in that: The processor includes a main control chip, and the main control chip is a FPGA chip.
7. The multi-channel signal memory based on FPGA chip according to claim 6, characterized in that: The FPGA chip processes data in parallel and transmits the processed data to the main storage module, the backup storage module, or the cache module.