Data encryption and decryption circuit and credential mobile terminal

Abstract

The utility model discloses a data encryption and decryption circuit and a credential mobile terminal, and belongs to the technical field of credential mobile terminal encryption. Comprising a central processing unit, an encryption and decryption chip, a power supply module and a power supply decoupling circuit, and a first data transmission channel and a second data transmission channel are arranged between the central processing unit and the encryption and decryption chip; the power supply decoupling circuit comprises a first capacitor, a second capacitor, a third capacitor and a fourth capacitor, the power supply module is electrically connected with the first capacitor, the second capacitor and the third capacitor respectively, the first capacitor and the second capacitor are electrically connected with a first power supply pin of the encryption and decryption chip respectively, and the third capacitor is electrically connected with a second power supply pin of the encryption and decryption chip. And the fourth capacitor is electrically connected with a third power supply pin of the encryption and decryption chip. Two-channel data transmission can be supported, voltage fluctuation output by a power supply is reduced, the working stability of the encryption and decryption circuit is guaranteed, and the problem that the operation stability of the encryption and decryption circuit is interfered by the power supply is solved.

Description

Technical Field

[0001] The utility model relates to the technical field of encryption of trusted mobile terminals, and in particular to a data encryption and decryption circuit and a trusted mobile terminal. Background Art

[0002] The statements herein merely provide background art related to the present invention and do not necessarily constitute prior art.

[0003] Trusted mobile terminals are a type of mobile device that is mostly used in areas that have high requirements for information security. However, the storage and transmission of existing trusted mobile terminal data is mostly encrypted through software encryption technology. The software encryption code and key are vulnerable to attacks by malware or easy to obtain through software vulnerabilities, which is less secure and poses data security issues.

[0004] Patent application number 201220124696.5 discloses an encryption and decryption circuit based on an IOS system mobile terminal. Although it uses hardware encryption technology to protect the secure access and key data of the mobile terminal, it directly powers the system through a power controller. The power supply voltage will interfere with the encryption and decryption circuit and affect its working stability. Utility Model Content

[0005] In view of the shortcomings of the prior art, the purpose of the embodiments of the utility model is to provide a data encryption and decryption circuit and a trusted mobile terminal, which filters the power supply noise through a power decoupling circuit, reduces the interference of the power supply output voltage to the encryption and decryption circuit, and improves the operating stability of the encryption and decryption circuit.

[0006] In order to achieve the above purpose, the utility model provides the following technical solutions:

[0007] In a first aspect, the utility model provides a data encryption and decryption circuit;

[0008] A data encryption and decryption circuit comprises a central processing unit, an encryption and decryption chip, a power supply module and a power supply decoupling circuit, wherein a first data transmission channel and a second data transmission channel are arranged between the central processing unit and the encryption and decryption chip;

[0009] The power module is electrically connected to the power decoupling circuit, and the power decoupling circuit is electrically connected to the encryption and decryption chip;

[0010] Among them, the power decoupling circuit includes a first capacitor, a second capacitor, a third capacitor and a fourth capacitor, the power module is electrically connected to the first capacitor, the second capacitor and the third capacitor respectively, the first capacitor and the second capacitor are electrically connected to the first power supply pin of the encryption and decryption chip respectively, the third capacitor is electrically connected to the second power supply pin of the encryption and decryption chip, and the fourth capacitor is electrically connected to the third power supply pin of the encryption and decryption chip.

[0011] In some embodiments, a power supply pin of the central processing unit is electrically connected to a decoupling capacitor;

[0012] The first end of the decoupling capacitor is electrically connected to the power module and the central processing unit respectively, and the second end of the decoupling capacitor is grounded.

[0013] In some embodiments, a reset circuit is further included, and the reset circuit is electrically connected to the PCR pin of the encryption / decryption chip.

[0014] In some embodiments, the reset circuit includes a first resistor and a fifth capacitor;

[0015] A first end of the fifth capacitor is electrically connected to the first resistor and a PCR pin of the encryption / decryption chip respectively, and a second end of the fifth capacitor is grounded.

[0016] In some embodiments, the central processor has a serial port data receiving pin and a serial port data sending pin;

[0017] The serial port data sending pin is electrically connected to the RXD pin of the encryption and decryption chip, and the serial port data receiving pin is electrically connected to the TXD pin of the encryption and decryption chip.

[0018] In some embodiments, the central processing unit has a data output function pin, a data input function pin, a clock function pin and a chip select function pin;

[0019] The data output function pin is electrically connected to the MOSI1 pin of the encryption and decryption chip, the data input function pin is electrically connected to the MISO1 pin of the encryption and decryption chip, the clock function pin is electrically connected to the SCK1 pin of the encryption and decryption chip, and the chip select function pin is electrically connected to the SS1 pin of the encryption and decryption chip.

[0020] In some implementations, the central processing unit has a handshake control pin, and the handshake control pin is electrically connected to the GINT pin of the encryption / decryption chip.

[0021] In some implementations, the first data transmission channel is an SPI data transmission channel, and the second data transmission channel is a UART data transmission channel.

[0022] In some implementations, the model of the central processing unit is RK3588S, and the model of the encryption and decryption chip is CCM3310-S.

[0023] In a second aspect, the utility model provides a trustworthy mobile terminal;

[0024] A secure mobile terminal, comprising the above-mentioned data encryption and decryption circuit.

[0025] One or more technical solutions provided by the utility model have at least the following technical effects or advantages:

[0026] 1. The technical solution provided by the utility model designs a power decoupling circuit to filter out power supply noise, provide a stable power supply for the encryption and decryption circuit, ensure the stability of the operation of the encryption and decryption circuit, and ensure data security.

[0027] 2. The technical solution provided by the utility model utilizes the SPI interface to transmit the data to be decrypted / encrypted and utilizes the UART interface to transmit the instructions. The two transmission data interfaces can be used simultaneously for data transmission, thereby improving the data transmission efficiency.

[0028] 3. The technical solution provided by the utility model utilizes hardware encryption and decryption chips to encrypt and decrypt data, thereby increasing security. At the same time, the model of the encryption and decryption chip is CCM3310-S, and the minimum power consumption is 33uW. It is suitable for battery-powered trusted mobile terminals, thereby extending the working time of the trusted mobile terminals. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] The drawings in the specification, which constitute a part of the present invention, are used to provide a further understanding of the present invention. The illustrative embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation on the present invention.

[0030] Figure 1 It is a schematic diagram of the architecture provided by an embodiment of the utility model;

[0031] Figure 2 It is a circuit connection diagram of a central processing unit provided by an embodiment of the utility model;

[0032] Figure 3 This is a circuit connection diagram of the encryption and decryption chip provided by the embodiment of the utility model;

[0033] In the picture: 1. Central processing unit; 2. Encryption and decryption chip.

[0034] In order to show the positions of various parts, the distances or sizes between them are exaggerated and the schematic diagram is for reference only. DETAILED DESCRIPTION

[0035] It should be noted that the following detailed descriptions are all illustrative and are intended to provide further explanation of the present invention. Unless otherwise specified, all technical and scientific terms used in the present invention have the same meanings as those commonly understood by those skilled in the art to which the present invention belongs.

[0036] Embodiment 1

[0037] As introduced in the background technology, the operation of the existing encryption and decryption circuit is easily affected by the fluctuation of the power supply output voltage. In order to solve the above technical problems, the utility model proposes a data encryption and decryption circuit.

[0038] Combination Figure 1-Figure 3 The data encryption and decryption circuit includes a central processing unit 1, an encryption and decryption chip 2, a power module and a power decoupling circuit. A first data transmission channel and a second data transmission channel are electrically connected between the central processing unit 1 and the encryption and decryption chip 2, thereby realizing dual-channel data transmission and improving the data transmission efficiency during data encryption and decryption.

[0039] As an implementation mode, in order to reduce the interference caused by the power supply output voltage fluctuation on the central processing unit 1 and the encryption and decryption chip 2, a power supply decoupling circuit is designed. The power supply decoupling circuit includes a first capacitor C4, a second capacitor C5, a third capacitor C6, a fourth capacitor C7, a first decoupling capacitor C1 and a second decoupling capacitor C2. The power supply module is electrically connected to the first capacitor C4, the second capacitor C5 and the third capacitor C3, respectively. The first capacitor C4 and the second capacitor C5 are electrically connected to the first power supply pin VDD5V of the encryption and decryption chip 2, respectively. The third capacitor C6 is electrically connected to the second power supply pin VCCQ of the encryption and decryption chip 2. The fourth capacitor C7 is electrically connected to the third power supply pin VDD of the encryption and decryption chip 2. The first power supply pin VDD5V, the second power supply pin VCCQ and the third power supply pin VDD of the encryption and decryption chip 2 are electrically connected to the output end corresponding to the power supply module. The first end of the first decoupling capacitor C1 is electrically connected to the power module and the W25 pin VCCI05_1V8 of the central processing unit 1 respectively, the second end of the first decoupling capacitor C1 is grounded, the first end of the second decoupling capacitor C2 is electrically connected to the W26 pin VCCIO5 of the central processing unit 1, the second end of the second decoupling capacitor C2 is grounded, and the W26 pin VCCIO5 of the central processing unit 1 and the W26 pin VCCIO5 are electrically connected to the output end corresponding to the power module.

[0040] When the power supply is used to supply power to the CPU 1 and the encryption / decryption chip 2, the first capacitor C4, the second capacitor C5, the third capacitor C6, the fourth capacitor C7, the first decoupling capacitor C1 and the second decoupling capacitor C2 are used to decouple the voltage output by the power supply to filter out power supply noise.

[0041] The PCR pin of the encryption and decryption chip 2 is electrically connected to a reset circuit for realizing power-on reset of the encryption and decryption chip 2; the reset circuit includes a first resistor R1 and a fifth capacitor C3, the first end of the fifth capacitor C3 is electrically connected to the first resistor R1 and the PCR pin of the encryption and decryption chip 2 respectively, and the second end of the fifth capacitor C3 is grounded.

[0042] In this embodiment, the encryption and decryption chip 2 is the CCM3310-S model encryption and decryption chip 2 of Tianjin Guoxin Technology Co., Ltd., and the central processing unit 1 is the RK3588S model central processing unit 1 of Fujian Rockchip Microelectronics Co., Ltd.; the first data transmission channel is the SPI data transmission channel, that is, data transmission is performed through the SPI interface, and the SPI interface is used to transmit data content that needs to be encrypted and decrypted; the second data transmission channel is the UART data transmission channel, that is, data transmission is performed through the UART interface, and the UART interface is used to transmit instructions between the central processing unit 1 and the encryption and decryption IC.

[0043] Specifically, the central processing unit 1 has a serial port data receiving pin, a serial port data sending pin, a data output function pin of the SPI interface, a data input function pin of the SPI interface, a clock function pin of the SPI interface and a chip select function pin of the SPI interface; the serial port data sending pin is electrically connected to the RXD pin of the encryption and decryption chip 2, the serial port data receiving pin is electrically connected to the TXD pin of the encryption and decryption chip 2, the data output function pin is electrically connected to the MOSI1 pin of the encryption and decryption chip 2, the data input function pin is electrically connected to the MISO1 pin of the encryption and decryption chip 2, the clock function pin is electrically connected to the SCK1 pin of the encryption and decryption chip 2, and the chip select function pin is electrically connected to the SS1 pin of the encryption and decryption chip 2.

[0044] The AG25 pin of the central processing unit 1 is electrically connected to the 9th pin of the encryption and decryption chip 2. The AG25 pin is the functional pin for waking up the encryption and decryption chip 2. When there is no data transmission on the SPI interface, the encryption and decryption chip 2 will automatically enter sleep mode to save power consumption. This is a built-in function of the encryption and decryption chip 2 and will not be described in detail here. The AG24 pin of the central processing unit 1 is electrically connected to the eighth pin of the encryption and decryption chip 2. Before transmitting data, the central processing unit 1 will determine whether the encryption and decryption chip 2 is in an idle state by whether the signal of the AG24 pin is at a high level.

[0045] The working method of this embodiment is as follows:

[0046] The central processing unit 1 reads the original data to be encrypted or decrypted from the storage medium, transmits the encryption signal or decryption signal to the encryption / decryption chip 2 through the UART interface, transmits the original data to be encrypted or decrypted to the encryption / decryption chip 2 through the SPI interface, and the encryption / decryption chip 2 encrypts or decrypts the received data according to the encryption signal or decryption signal; the central processing unit 1 obtains the encrypted or decrypted data through the SPI interface for storage in the storage medium or application software call.

[0047] Here, the encryption or decryption of the received data by the encryption / decryption chip 2 is a built-in function of the CCM3310-S model encryption / decryption chip 2, and this embodiment does not make any improvements to it, so it will not be repeated here.

[0048] Embodiment 2

[0049] Based on the above-mentioned data encryption and decryption circuit, this embodiment also provides a trusted mobile terminal, in which the data encryption and decryption circuit described in the above-mentioned embodiment is arranged. Since the above-mentioned data encryption and decryption circuit has the above-mentioned technical effect, please refer to the above-mentioned embodiment for the technical effect of the trusted mobile terminal adopting the data encryption and decryption circuit.

[0050] Although the above describes the specific implementation methods of the utility model in conjunction with the accompanying drawings, it is not intended to limit the scope of protection of the utility model. Technical personnel in the relevant field should understand that on the basis of the technical solution of the utility model, various modifications or deformations that can be made by technical personnel in this field without creative work are still within the scope of protection of the utility model.

Claims

1. A data encryption and decryption circuit, characterized in that: It includes a central processing unit, an encryption and decryption chip, a power supply module and a power supply decoupling circuit, wherein a first data transmission channel and a second data transmission channel are provided between the central processing unit and the encryption and decryption chip; The power module is electrically connected to the power decoupling circuit, and the power decoupling circuit is electrically connected to the encryption and decryption chip; Among them, the power decoupling circuit includes a first capacitor, a second capacitor, a third capacitor and a fourth capacitor, the power module is electrically connected to the first capacitor, the second capacitor and the third capacitor respectively, the first capacitor and the second capacitor are electrically connected to the first power supply pin of the encryption and decryption chip respectively, the third capacitor is electrically connected to the second power supply pin of the encryption and decryption chip, and the fourth capacitor is electrically connected to the third power supply pin of the encryption and decryption chip.

2. The data encryption and decryption circuit according to claim 1, characterized in that: The power supply pin of the central processing unit is electrically connected to a decoupling capacitor; The first end of the decoupling capacitor is electrically connected to the power module and the central processing unit respectively, and the second end of the decoupling capacitor is grounded.

3. The data encryption and decryption circuit according to claim 1, characterized in that: It also includes a reset circuit, which is electrically connected to the PCR pin of the encryption and decryption chip.

4. The data encryption and decryption circuit according to claim 3, characterized in that: The reset circuit includes a first resistor and a fifth capacitor; A first end of the fifth capacitor is electrically connected to the first resistor and a PCR pin of the encryption / decryption chip respectively, and a second end of the fifth capacitor is grounded.

5. The data encryption and decryption circuit according to claim 1, characterized in that: The central processing unit has a serial port data receiving pin and a serial port data sending pin; The serial port data sending pin is electrically connected to the RXD pin of the encryption and decryption chip, and the serial port data receiving pin is electrically connected to the TXD pin of the encryption and decryption chip.

6. The data encryption and decryption circuit according to claim 1, characterized in that: The central processing unit has a data output function pin, a data input function pin, a clock function pin and a chip selection function pin; The data output function pin is electrically connected to the MOSI1 pin of the encryption and decryption chip, the data input function pin is electrically connected to the MISO1 pin of the encryption and decryption chip, the clock function pin is electrically connected to the SCK1 pin of the encryption and decryption chip, and the chip select function pin is electrically connected to the SS1 pin of the encryption and decryption chip.

7. The data encryption and decryption circuit according to claim 1, characterized in that: The central processing unit has a handshake control pin, and the handshake control pin is electrically connected to the GINT pin of the encryption and decryption chip.

8. The data encryption and decryption circuit according to claim 1, characterized in that: The first data transmission channel is an SPI data transmission channel, and the second data transmission channel is a UART data transmission channel.

9. The data encryption and decryption circuit according to claim 1, characterized in that: The model of the central processing unit is RK3588S, and the model of the encryption and decryption chip is CCM3310-S.

10. A credible mobile terminal, characterized in that: The invention comprises the data encryption and decryption circuit as described in any one of claims 1 to 9.

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