Semiconductor structure and electronic equipment

Abstract

The utility model relates to a semiconductor structure and electronic equipment. The semiconductor structure comprises a channel layer, a barrier layer, an insulating medium layer and a grid electrode. The barrier layer is located between the channel layer and the grid electrode, and the grid electrode is located on the side, opposite to the channel layer, of the barrier layer. The grid electrode comprises a first grid electrode and a second grid electrode. The second grid electrode is located between the first grid electrode and the barrier layer, and the first grid electrode is located on the side, opposite to the barrier layer, of the second grid electrode. And the insulating dielectric layer is in contact with the side wall of the second grid electrode and surrounds the second grid electrode. According to the embodiment of the invention, breakdown of the semiconductor structure is effectively prevented.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a semiconductor structure and an electronic device. Background Art

[0002] In the related art, high electron mobility transistors (HEMT) are increasingly used in production and life due to their properties. For HEMT devices, during the preparation process, the gate will inevitably have etching damage due to the process of etching to form the gate. The damaged gate will increase the leakage of the gate. In severe cases, the leakage voltage may even break through the gate, causing the HEMT device to fail. In order to avoid the problem of leakage voltage breaking through the gate and causing the device to fail, people try to improve the anti-breakdown capability of HEMT devices in some ways. However, the problem of gate damage in the preparation process still needs to be solved urgently. Summary of the invention

[0003] According to a first aspect of an embodiment of the present application, there is provided a semiconductor structure, comprising: a channel layer, a barrier layer, an insulating dielectric layer and a gate;

[0004] The barrier layer is located between the channel layer and the gate, and the gate is located on a side of the barrier layer facing away from the channel layer;

[0005] The gate includes a first gate and a second gate; the second gate is located between the first gate and the barrier layer, and the first gate is located on the side of the second gate facing away from the barrier layer; the insulating dielectric layer contacts the side wall of the second gate and surrounds the second gate.

[0006] In some embodiments, the orthographic projection of the first gate on the second gate is located within the second gate;

[0007] The insulating dielectric layer extends to a side of the second gate facing away from the barrier layer, and at least covers a portion of the second gate that is outside an orthographic projection of the first gate on the second gate.

[0008] In some embodiments, it further includes: a damage repair layer; the damage repair layer is located on a side of the barrier layer facing away from the channel layer and is used to repair damage to the gate and the barrier layer;

[0009] The second gate and the insulating dielectric layer are both located between the damage repair layer and the barrier layer; and the first gate is located on a side of the damage repair layer facing away from the barrier layer.

[0010] In some embodiments, it further includes: a damage repair layer; the damage repair layer is located on a side of the barrier layer facing away from the channel layer and is used to repair damage to the gate and the barrier layer;

[0011] The second gate and the insulating dielectric layer are both located between the damage repair layer and the barrier layer; the first gate is in contact with the second gate, and the first gate extends out of the damage repair layer along the barrier layer in a direction away from the channel layer; the insulating dielectric layer located on the side of the second gate facing away from the barrier layer is in contact with the side wall of the first gate and surrounds the first gate.

[0012] In some embodiments, the insulating dielectric layer covers a side of the second gate facing away from the barrier layer; the first gate is located on a side of the insulating dielectric layer facing away from the second gate and is in direct contact with the insulating dielectric layer.

[0013] In some embodiments, the insulating dielectric layer extends to a side of the barrier layer facing away from the channel layer, and contacts the barrier layer;

[0014] The portion of the barrier layer that is outside the orthographic projection of the second gate on the barrier layer is a damaged portion; the insulating dielectric layer that is in contact with the barrier layer covers at least a portion of the damaged portion.

[0015] In some embodiments, the method further comprises: two electrodes; the two electrodes are in contact with the channel layer and extend out of the barrier layer along a direction from the barrier layer to the channel layer;

[0016] The insulating medium layer contacts the side walls of the two electrodes and surrounds the two electrodes respectively.

[0017] In some embodiments, the material of the insulating dielectric layer includes: a high-resistance compound of elements from Group III to Group V.

[0018] In some embodiments, the material of the insulating dielectric layer includes: one of aluminum nitride, silicon nitride, aluminum gallium nitride or indium gallium nitride.

[0019] According to a second aspect of the present application, an electronic device is provided, comprising any one of the above-mentioned semiconductor structures.

[0020] According to the above embodiments, the insulating dielectric layer is in contact with the side wall of the second gate and surrounds the second gate. The insulating dielectric layer can effectively isolate the contact relationship between the second gate and other structures in the semiconductor structure, so that the insulating dielectric layer can effectively avoid the leakage current generated by the etching scar on the side wall of the second gate, and further, the insulating dielectric layer can effectively prevent the breakdown of the semiconductor structure caused by the leakage current generated by the etching scar on the side wall of the second gate.

[0021] It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0023] Figure 1 It is a structural schematic diagram of a semiconductor structure according to an embodiment of the present application.

[0024] Figure 2 It is a schematic structural diagram of another semiconductor structure according to an embodiment of the present application.

[0025] Figure 3 It is a schematic structural diagram of another semiconductor structure according to an embodiment of the present application.

[0026] Figure 4 It is a schematic structural diagram of another semiconductor structure according to an embodiment of the present application.

[0027] Figure 5 It is an intermediate structure in a semiconductor structure preparation process shown in an embodiment of the present application.

[0028] Figure 6 It is an intermediate structure in the preparation process of another semiconductor structure shown in an embodiment of the present application.

[0029] Figure 7 It is an intermediate structure in the preparation process of another semiconductor structure shown in an embodiment of the present application. DETAILED DESCRIPTION

[0030] Exemplary embodiments will be described in detail herein, examples of which are shown in the accompanying drawings. When the following description refers to the drawings, the same numbers in different drawings represent the same or similar elements unless otherwise indicated. The implementations described in the following exemplary embodiments do not represent all implementations consistent with the present application. Instead, they are merely examples of devices and methods consistent with some aspects of the present application as detailed in the appended claims.

[0031] In the existing process of preparing HEMT devices, it is necessary to deposit gate materials and then etch the deposited gate materials to form the gate. Therefore, in the process of etching the deposited gate materials, etching scars will inevitably be left. When the gate is subjected to current, the etching scars left in the gate will cause the leakage current generated by the etching scars to increase. When the leakage current out of the gate increases, in severe cases, it may even cause the HEMT device to have a gate breakdown problem.

[0032] In addition, during the process of preparing the gate, the problem of etching scars on the sidewalls of the gate is particularly prominent. Therefore, how to avoid the increase of leakage current caused by etching scars on the gate and improve the overall anti-breakdown capability of the HEMT device has become an urgent problem to be solved.

[0033] In order to solve the aforementioned problem, an embodiment of the present application provides a semiconductor structure 10 . Figure 1 FIG. 1 is a schematic diagram of the structure of the semiconductor structure 10. Figure 1 As shown, the semiconductor structure 10 includes a channel layer 11 , a barrier layer 12 , an insulating dielectric layer 13 and a gate 14 .

[0034] The barrier layer 12 is located between the channel layer 11 and the gate 14, and the gate 14 is located on the side of the barrier layer 12 facing away from the channel layer 11. The barrier layer 12 is in direct contact with the channel layer 11, and the band gap of the material forming the barrier layer 12 is higher than the band gap of the material forming the channel layer 11, so that when the barrier layer 12 and the channel layer 11 are subjected to an electric field, a two-dimensional electron gas (2DEG) is generated at the interface of the barrier layer 12 and the channel layer 11 in the heterojunction formed by the barrier layer 12 and the channel layer 11, facing the side of the channel layer 11. By controlling the electric field applied to the barrier layer 12 and the channel layer 11, the semiconductor structure 10 can be turned on and off. The voltage applied to the gate 14 can be higher than the threshold voltage of the semiconductor structure 10 to turn on, or the voltage applied to the gate 14 can be lower than the threshold voltage of the semiconductor structure 10 to turn on, which is not limited here.

[0035] The gate 14 includes a first gate 141 and a second gate 142. The second gate 142 is located between the first gate 141 and the barrier layer 12, and the first gate 141 is located on the side of the second gate 142 facing away from the barrier layer 12. The second gate 142 may be in direct contact with the barrier layer 12. The insulating dielectric layer 13 is in contact with the sidewall C1 of the second gate 142 and surrounds the second gate 142.

[0036] The first gate 141 and the second gate 142 included in the gate 14 jointly realize the function of gate control. However, the effects produced by the first gate 141 and the second gate 142 are different. Among them, the material of the first gate 141 can mainly include conductive materials including titanium nitride (TiN), and is used to withstand the voltage applied to the gate 14 to form an electric field that can affect the heterojunction formed by the barrier layer 12 and the channel layer 11. The material of the second gate 142 can mainly include P-type gallium nitride, and is used to promote and control the flow of current applied to the first gate 141 in a specific direction, so as to form an electric field that can better control the formation of a two-dimensional electron gas at the interface between the barrier layer 12 and the channel layer 11.

[0037] Since the first gate 141 and the second gate 142 mainly play different roles, the effects of the etching scars on the first gate 141 and the second gate 142 are also different. Since the second gate 142 is mainly used to promote and control the flow of current applied to the first gate 141 in a specific direction, if there are etching scars on the second gate 142, the current is more likely to pass through the etching scars on the second gate 142 to generate leakage current, thereby causing the breakdown of the semiconductor structure 10. At the same time, since the thickness of the deposited material is controllable when the second gate 142 is generally prepared by depositing a whole layer of material and then etching, during etching, in order to obtain the second gate 142, the material other than the part used to form the second gate 142 is mainly etched, that is, the material around the part used to form the second gate 142 is etched. In this way, the etching scars of the second gate 142 will mainly exist on its side wall C1.

[0038] The insulating dielectric layer 13 contacts the side wall C1 of the second gate 142 and surrounds the second gate 142. The insulating dielectric layer 13 can effectively isolate the contact relationship between the second gate 142 and other structures in the semiconductor structure 10, so that the insulating dielectric layer 13 can effectively prevent leakage current generated by etching scars on the side wall C1 of the second gate 142, and further, the insulating dielectric layer 13 can effectively prevent the breakdown of the semiconductor structure 10 caused by leakage current generated by etching scars on the side wall C1 of the second gate 142.

[0039] In some embodiments, based on the aforementioned provision of the insulating dielectric layer 13, as Figure 1 As shown, the orthographic projection of the first grid 141 on the second grid 142 is located inside the second grid 142 .

[0040] The insulating dielectric layer 13 extends to a side of the second gate 142 facing away from the barrier layer 12 , and at least covers a portion of the second gate 142 that is outside the orthographic projection of the first gate 141 on the second gate 142 .

[0041] Specifically, the insulating dielectric layer 13 extends to the side of the second gate 142 facing away from the barrier layer 12 , that is, the insulating dielectric layer 13 is simultaneously located around the second gate 142 and on the side of the second gate 142 facing away from the barrier layer 12 .

[0042] Furthermore, the insulating dielectric layer 13 at least covers the portion of the second gate 142 that is located outside the orthographic projection of the first gate 141 on the second gate 142, that is, the insulating dielectric layer 13 covers at least a portion of the side of the second gate 142 that is facing away from the barrier layer 12, that is, the insulating dielectric layer 13 may cover a portion of the side of the second gate 142 that is facing away from the barrier layer 12, or the insulating dielectric layer 13 may cover the entire side of the second gate 142 that is facing away from the barrier layer 12. However, when the insulating dielectric layer 13 covers the side of the second gate 142 that is facing away from the barrier layer 12, it at least covers the portion of the second gate 142 that is located outside the orthographic projection of the first gate 141 on the second gate 142. Among them, the portion of the second gate 142 that is located outside the orthographic projection of the first gate 141 on the second gate 142, that is, Figure 1 As for the partial structure Q1 shown in FIG. 1 , the insulating dielectric layer 13 at least covers the partial structure Q1 .

[0043] Since the first gate 141 and the second gate 142 have different main functions, the orthographic projection of the first gate 141 on the second gate 142 is generally located inside the second gate 142, so that the second gate 142 can better play its role in promoting and controlling the current applied to the first gate 141 to flow in a specific direction. The second gate 142 is located outside the orthographic projection of the first gate 141 on it, that is, Figure 1 At the partial structure Q1, since it is also close to the side wall C1 of the second gate 142, this part of the structure of the second gate 142 is also prone to etching scars. The insulating dielectric layer 13 extends here and at least covers this part. The insulating dielectric layer 13 can better avoid the leakage current generated by the etching scars on the second gate 142. Furthermore, the insulating dielectric layer 13 can effectively prevent the breakdown of the semiconductor structure 10 caused by the leakage current generated by the etching scars on the second gate 142.

[0044] In some embodiments, on the basis that the aforementioned insulating dielectric layer 13 at least covers the portion of the second gate 142 located outside the orthographic projection of the first gate 141 on the second gate 142, as Figure 1 As shown, the semiconductor structure 10 further includes: a damage repair layer 15. The damage repair layer 15 is located on the side of the barrier layer 12 facing away from the channel layer 11, and is used to repair damage to the gate 14 and the barrier layer 12. The material of the damage repair layer 15 may include gallium nitride (GaN) or aluminum gallium nitride (AlGaN), but is not limited thereto.

[0045] The second gate 142 and the insulating dielectric layer 13 are both located between the damage repair layer 15 and the barrier layer 12. The first gate 141 is located on the side of the damage repair layer 15 facing away from the barrier layer 12. Since the damage repair layer 15 can repair the damage of the gate 14 and the barrier layer 12, and since the second gate 142 and the insulating dielectric layer 13 are both located between the damage repair layer 15 and the barrier layer 12, the gate 14 and the barrier layer 12 with less etching scars can be covered by the damage repair layer 15, and the etching scars can be repaired.

[0046] However, due to the limited repair ability of the damage repair layer 15, it is impossible to completely repair the etching scars. Therefore, by combining the damage repair layer 15 and the insulating dielectric layer 13, the parts of the second gate 142 with more and fewer etching scars can be repaired in a suitable manner at the same time, that is, while forming the insulating dielectric layer 13 for the part of the second gate 142 with more etching scars, the damage repair layer 15 is formed to repair it, so as to achieve a stronger effect of avoiding the generation of leakage current. The damage repair layer 15 is directly formed to repair the part with fewer etching scars, so that the leakage current generated by the etching scars on the second gate 142 can be better avoided by the insulating dielectric layer 13 and the damage repair layer 15, and further, the breakdown of the semiconductor structure 10 caused by the leakage current generated by the etching scars on the second gate 142 can be effectively prevented by the insulating dielectric layer 13 and the damage repair layer 15.

[0047] In some embodiments, the insulating dielectric layer 13 at least covers the portion of the second gate 142 that is outside the orthographic projection of the first gate 141 on the second gate 142. Figure 2 FIG. 1 is a schematic diagram of another semiconductor structure 10. Figure 2 As shown, the semiconductor structure 10 further includes a damage repair layer 15 . The damage repair layer 15 is located on the side of the barrier layer 12 facing away from the channel layer 11 and is used to repair damages of the gate 14 and the barrier layer 12 .

[0048] The second gate 142 and the insulating dielectric layer 13 are both located between the damage repair layer 15 and the barrier layer 12. The first gate 141 is in contact with the second gate 142, and the first gate 141 extends the damage repair layer 15 along the direction of the barrier layer 12 away from the channel layer 11. The insulating dielectric layer 13 located on the side of the second gate 142 away from the barrier layer 12 is in contact with the side wall C2 of the first gate 141 and surrounds the first gate 141. Among them, the insulating dielectric layer 13 located on the side of the second gate 142 away from the barrier layer 12 is in contact with the side wall C2 of the first gate 141, that is, the insulating dielectric layer 13 covers the part of the second gate 142 located outside the orthographic projection of the first gate 141 on the second gate 142.

[0049] By making the first gate 141 directly contact the second gate 142, the leakage current generated on the surface of the second gate 142 in contact with the first gate 141 can be limited. In addition, by forming the damage repair layer 15 for repair, the surface of the second gate 142 not covered by the insulating dielectric layer 13 can be repaired, so that the leakage current generated by the etching scar on the second gate 142 can be better avoided by the insulating dielectric layer 13 and the damage repair layer 15, and the leakage current that may be generated in the second gate 142 can be limited by using the existing structure of the first gate 141, and further, the breakdown of the semiconductor structure 10 caused by the leakage current generated by the etching scar on the second gate 142 can be effectively prevented by the insulating dielectric layer 13, the damage repair layer 15 and the first gate 141.

[0050] In some embodiments, the insulating dielectric layer 13 at least covers the portion of the second gate 142 that is outside the orthographic projection of the first gate 141 on the second gate 142. Figure 3 FIG. 1 is a schematic diagram of another semiconductor structure 10. Figure 3 As shown, the insulating dielectric layer 13 covers the side of the second gate 142 facing away from the barrier layer 12. The first gate 141 is located on the side of the insulating dielectric layer 13 facing away from the second gate 142 and is in direct contact with the insulating dielectric layer 13.

[0051] In this way, the second gate 142 can be completely covered by the insulating dielectric layer 13 to avoid leakage current generated through the etching scars of the second gate 142, the etching scars on the second gate 142 can be repaired by the damage repair layer 15, and the leakage current that may be generated by the second gate 142 can be further limited by the first gate 141. Therefore, the leakage current generated by the etching scars on the second gate 142 can be better avoided by the insulating dielectric layer 13 and the damage repair layer 15, and the leakage current that may be generated in the second gate 142 can be limited by using the existing structure of the first gate 141. Furthermore, the insulating dielectric layer 13, the damage repair layer 15 and the first gate 141 can effectively prevent the breakdown of the semiconductor structure 10 caused by the leakage current generated by the etching scars on the second gate 142.

[0052] In some embodiments, Figure 4 Another semiconductor structure 10 is shown. Figure 2 and Figure 4 As shown, the insulating dielectric layer 13 is arranged to extend to the side of the barrier layer 12 facing away from the channel layer 11 and is in contact with the barrier layer 12 .

[0053] The portion of the barrier layer 12 that is outside the orthographic projection of the second gate 142 on the barrier layer 12 is a damaged portion 121. The insulating dielectric layer 13 that is in contact with the barrier layer 12 covers at least a portion of the damaged portion 121.

[0054] Specifically, the insulating dielectric layer 13 in contact with the barrier layer 12 covers at least a portion of the damaged portion 121. The insulating dielectric layer 13 in contact with the barrier layer 12 may cover a portion of the damaged portion 121, or the insulating dielectric layer 13 in contact with the barrier layer 12 may cover all of the damaged portion 121. The two cases where the insulating dielectric layer 13 in contact with the barrier layer 12 covers a portion or all of the damaged portion 121 can be compared with reference to Figure 2 and Figure 4 The insulating dielectric layer 13 in contact with the barrier layer 12 covers the damaged portion 121, which can be referred to as Figure 2 As shown, the insulating dielectric layer 13 in contact with the barrier layer 12 covers the entire damaged portion 121. Figure 4 shown.

[0055] By providing the damage repair layer 15 , the surface state of the barrier layer 12 covered by the damage repair layer 15 can be optimized while repairing the damage on the surface of the barrier layer 12 covered by the damage repair layer 15 .

[0056] In some embodiments, on the basis that the insulating dielectric layer 13 covers at least a portion of the damaged portion 121, as Figure 2 and Figure 4 As shown, the semiconductor structure 10 further includes two electrodes 16 . The two electrodes 16 are in contact with the channel layer 11 and extend out of the barrier layer 12 in a direction from the barrier layer 12 to the channel layer 11 .

[0057] The insulating dielectric layer 13 contacts the sidewalls C3 of the two electrodes 16 and surrounds the two electrodes 16 respectively. The two electrodes 16 may be a source and a drain respectively.

[0058] In some embodiments, the material of the insulating dielectric layer 13 includes: a high-resistance compound of elements from Group III to Group V.

[0059] By selecting the aforementioned materials, the insulating dielectric layer 13 can better realize the insulating function, thereby effectively preventing the breakdown of the semiconductor structure 10 caused by leakage current generated through the etching scars on the sidewall C1 of the second gate 142 .

[0060] In some embodiments, the material of the insulating dielectric layer 13 includes: aluminum nitride, silicon nitride, aluminum gallium nitride or indium gallium nitride.

[0061] By selecting the aforementioned materials, the insulating dielectric layer 13 can better realize the insulating function, thereby more effectively preventing the breakdown of the semiconductor structure 10 caused by leakage current generated through the etching scars on the sidewall C1 of the second gate 142 .

[0062] In some embodiments, Figures 1 to 4 As shown, the semiconductor structure 10 further includes: a substrate 20 , a packaging layer 21 and a field plate structure 22 .

[0063] The substrate 20 is used for epitaxially producing other film structures of the semiconductor structure 10 thereon.

[0064] The encapsulation layer 21 is used to encapsulate the existing semiconductor structure 10 and protect other structures.

[0065] The field plate structure 22 is used to enhance the overall device performance of the semiconductor structure 10 and improve the gate-drain breakdown voltage.

[0066] In some embodiments, Figure 4 Taking the semiconductor structure 10 as an example, Figure 5 , Figure 6 and Figure 7 Shown is the preparation Figure 4 The semiconductor structure 10 is shown with several intermediate structures during the process.

[0067] First, if Figure 5 As shown, a channel layer 11 and a barrier layer 12 are sequentially epitaxially grown on a substrate 20 . Then, a second gate 142 is formed by deposition and etching on a side of the barrier layer 12 facing away from the substrate 20 .

[0068] Then, if Figure 6 As shown, on the side of the second gate 142 and the barrier layer 12 facing away from the substrate 20, an insulating dielectric layer 13 and a damage repair layer 15 are sequentially deposited and etched. Figure 6 In the intermediate structure shown, the damage repair layer 15 is not completely etched, and this is only to clearly show the repair process of the damage repair layer 15 on the portion located between the first gate 141 and the second gate 142 .

[0069] Then, if Figure 7 As shown, a first gate 141 and two electrodes 16 are formed by deposition and etching.

[0070] Finally, the encapsulation layer 21 and the field plate structure 22 are formed by deposition to obtain Figure 4 A semiconductor structure 10 is shown.

[0071] It should be noted that although Figure 5 , Figure 6 and Figure 7 Shown is the preparation Figure 4 The semiconductor structure 10 shown in the process has several intermediate structures, but Figure 1 , Figure 2 and Figure 3 The manufacturing process of the semiconductor structure 10 shown can also be referred to here.

[0072] The present application also provides an electronic device, comprising any one of the semiconductor structures 10 described above.

[0073] The above embodiments of the present application may complement each other if no conflict occurs.

[0074] It should be noted that in the accompanying drawings, the sizes of layers and regions may be exaggerated for clarity of illustration. It is also understood that when an element or layer is referred to as being "on" another element or layer, it may be directly on the other element, or there may be an intermediate layer. In addition, it is understood that when an element or layer is referred to as being "under" another element or layer, it may be directly under the other element, or there may be more than one intermediate layer or element. In addition, it is also understood that when a layer or element is referred to as being "between" two layers or two elements, it may be the only layer between the two layers or two elements, or there may also be more than one intermediate layer or element. Similar reference numerals throughout the text indicate similar elements.

[0075] The term "plurality" means two or more than two, unless expressly limited otherwise.

[0076] Those skilled in the art will readily appreciate other embodiments of the present application after considering the specification and practice. The present application is intended to cover any variations, uses or adaptations of the present application, which follow the general principles of the present application and include common knowledge or customary techniques in the art that are not disclosed in the present application. The specification and examples are intended to be exemplary only, and the true scope and spirit of the present application are indicated by the following claims.

[0077] It should be understood that the present application is not limited to the precise structures that have been described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present application is limited only by the appended claims.

Claims

1. A semiconductor structure, characterized in that: include: Channel layer, barrier layer, insulating dielectric layer and gate; The barrier layer is located between the channel layer and the gate, and the gate is located on a side of the barrier layer facing away from the channel layer; The gate includes a first gate and a second gate; the second gate is located between the first gate and the barrier layer, and the first gate is located on the side of the second gate facing away from the barrier layer; the insulating dielectric layer contacts the side wall of the second gate and surrounds the second gate.

2. The semiconductor structure according to claim 1, characterized in that: The orthographic projection of the first grid on the second grid is located inside the second grid; The insulating dielectric layer extends to a side of the second gate facing away from the barrier layer, and at least covers a portion of the second gate that is outside an orthographic projection of the first gate on the second gate.

3. The semiconductor structure according to claim 2, characterized in that: Also includes: Damage repair layer; The damage repair layer is located on a side of the barrier layer facing away from the channel layer and is used to repair damage to the gate and the barrier layer; The second gate and the insulating dielectric layer are both located between the damage repair layer and the barrier layer; and the first gate is located on a side of the damage repair layer facing away from the barrier layer.

4. The semiconductor structure according to claim 2, characterized in that: Also includes: Damage repair layer; The damage repair layer is located on a side of the barrier layer facing away from the channel layer and is used to repair damage to the gate and the barrier layer; The second gate and the insulating dielectric layer are both located between the damage repair layer and the barrier layer; the first gate is in contact with the second gate, and the first gate extends out of the damage repair layer along the barrier layer in a direction away from the channel layer; the insulating dielectric layer located on the side of the second gate facing away from the barrier layer is in contact with the side wall of the first gate and surrounds the first gate.

5. The semiconductor structure according to claim 2, characterized in that: The insulating dielectric layer covers the side of the second gate facing away from the barrier layer; the first gate is located on the side of the insulating dielectric layer facing away from the second gate and is in direct contact with the insulating dielectric layer.

6. The semiconductor structure according to claim 1, characterized in that The insulating dielectric layer extends to a side of the barrier layer facing away from the channel layer and contacts the barrier layer; The portion of the barrier layer that is outside the orthographic projection of the second gate on the barrier layer is a damaged portion; the insulating dielectric layer that is in contact with the barrier layer covers at least a portion of the damaged portion.

7. The semiconductor structure according to claim 6, characterized in that: Also includes: Two electrodes; the two electrodes are in contact with the channel layer and extend out of the barrier layer along a direction of the barrier layer facing away from the channel layer; The insulating medium layer contacts the side walls of the two electrodes and surrounds the two electrodes respectively.

8. The semiconductor structure according to claim 1, characterized in that: The material of the insulating dielectric layer is a high-resistance compound of elements from Group III to Group V.

9. The semiconductor structure according to claim 6, characterized in that: The material of the insulating dielectric layer is one of aluminum nitride, silicon nitride, aluminum gallium nitride or indium gallium nitride.

10. An electronic device, characterized in that: A semiconductor structure comprising any one of claims 1 to 9.

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