Wafer structure for manufacturing trench gate device
By setting gate trenches in the chip area of the wafer and setting stress correction trenches around the chip area in the scribe area, the problem of wafer warping during the trench gate device production is solved, and the effect of reducing stress and improving warpage is achieved, providing good conditions for subsequent processes.
Patent Information
- Application Number
- CN202421415317.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-06-19
- Publication Date
- 2025-03-28
- Estimated Expiration
- 2034-06-19
AI Technical Summary
During the process of making the trench gate device, the formation of the gate trench is likely to cause the wafer to warp, affecting the normal progress of the subsequent process.
A wafer structure for trench gate devices is designed. By setting a gate trench in the chip region of the wafer and setting a stress correction trench around the chip region in the scribe region, the opening shape of the stress correction trench is a square waveform or a triangular waveform, and the opening extension direction is different from the gate trench opening extension.
By adjusting the opening extension direction of the gate trench in the wafer and setting stress correction trench, the stress on the wafer is reduced, the warping problem of the wafer is improved, and good conditions are provided for subsequent processes and the consistency and performance of the process are improved.
Smart Images
Figure CN222692197U_ABST
Abstract
Description
Technical Field
[0001] The utility model belongs to the field of semiconductor integrated circuit manufacturing, and relates to a wafer structure used for manufacturing a trench gate device. Background Art
[0002] With the development of power semiconductors, IGBT (Insulated Gate Bipolar Transistor), one of the core components in modern power electronic circuits, has been widely used in transportation, energy, industry, household appliances and other fields. The power device IGBT is a switching device that controls strong electricity with weak electricity. The theme of device optimization is to minimize the loss of the device itself on the basis of achieving normal switching. In order to reduce the on-state voltage drop, mainstream IGBTs all use a trench gate structure (Trench), but the introduction of the trench destroys the surface structure of the wafer, and after the trench is formed, it undergoes sacrificial oxidation, gate oxidation, Poly silicon filling, and high-temperature thermal processes in the furnace tube, which can easily cause wafer warping. With the iteration of IGBT technology, the trench density is getting higher and higher, and the risk of wafer warping is getting greater and greater. For example Figure 1 As shown, it is an arrangement diagram of the gate grooves in the wafer, including wafer 01, chip area 011, dicing area 012, gate groove 013 and gate lead-out area 014. Such a gate groove arrangement is performed on the wafer (i.e., the gate grooves on the entire wafer are distributed along the horizontal direction). After the gate grooves are formed, accompanied by a large number of thermal processes in the power device production process, the direction perpendicular to the gate groove, i.e., longitudinal stress accumulation, causes the wafer to warp with the horizontal diameter as the axis. The warping causes the chips at the edge of the wafer to have a large alignment deviation, the chip process consistency becomes worse, and the severe warping even affects the normal progress of the subsequent processes.
[0003] Therefore, there is an urgent need to find a wafer structure for manufacturing trench gate devices that improves wafer warpage during the process of manufacturing trench gate devices. Utility Model Content
[0004] In view of the above-mentioned shortcomings of the prior art, the purpose of the present invention is to provide a wafer structure for manufacturing trench gate devices, which is used to solve the problem that the formation of gate trenches in the prior art of manufacturing trench gate devices easily causes wafer warping and affects subsequent processes.
[0005] To achieve the above-mentioned object and other related objects, the utility model provides a wafer structure for a trench gate device, comprising:
[0006] A wafer, comprising a plurality of chip regions and a dicing region located between two adjacent chip regions, wherein the chip region comprises at least one cell region;
[0007] A gate trench is located in the cell region;
[0008] A stress correction groove is located in the scribe area, the stress correction groove surrounds the chip area, the extension direction of the opening of the stress correction groove is different from that of the gate groove, and the opening shape of the stress correction groove is a square waveform or a triangular waveform.
[0009] Optionally, the gate trench in the same chip region includes a first trench and a second trench, and the openings of the first trench and the second trench extend in different directions.
[0010] Optionally, an extension direction of the first groove is perpendicular to an extension direction of an opening of the second groove.
[0011] Optionally, the openings of the first trenches in two adjacent chip regions extend in the same direction, and the openings of the second trenches in two adjacent chip regions extend in the same direction.
[0012] Optionally, in the same chip area, the openings of the first trench and the second trench extend in different directions, and in two adjacent chip areas, the openings of the first trench extend in different directions and the openings of the second trench extend in different directions.
[0013] Optionally, the openings of the gate trenches in two adjacent chip regions extend in different directions.
[0014] Optionally, the stress correction grooves surrounding the chip region are interconnected.
[0015] Optionally, the stress correction grooves surrounding the chip area are arranged at intervals in the scribe area around the chip area.
[0016] Optionally, the opening shape of the stress correction groove is a triangular waveform, and the angle between the stress correction grooves on both sides of the peak point of the triangular waveform and the extension direction of the stress correction groove between two adjacent chip areas is + / -45°.
[0017] Optionally, a gate lead-out region is further provided in the chip region, and the gates of the trench gate devices in the same chip region are all led to the gate lead-out region.
[0018] As described above, the wafer structure for manufacturing trench gate devices of the utility model adjusts the extension direction of the opening of the gate groove of each chip area in the wafer body through the structure of the wafer, so as to avoid the concentration of stress in the same direction in each chip area or the wafer body, thereby reducing the stress on each chip area or each part of the wafer body, and at the same time, a stress correction groove is set in the scribing area outside the chip area, and the stress generated in the chip area is further corrected by the stress correction groove surrounding the chip area, so that the stress on the wafer body is further reduced, and then the warpage of the wafer body is improved, providing good process conditions for the subsequent process of manufacturing trench gate devices, ensuring the normal progress of the subsequent process, reducing the error of the subsequent photolithography alignment, and improving the consistency of the process of the trench gate device. In addition, since the stress correction groove is set in the scribing area of the wafer body, it is avoided that the stress on the wafer is corrected while affecting the performance of the trench gate device, and the performance of the trench gate device is guaranteed, which has a high industrial utilization value. BRIEF DESCRIPTION OF THE DRAWINGS
[0019] Figure 1 Shown is the layout of the gate trenches in a trench gate device wafer.
[0020] Figures 2 to 11 Shown are several schematic diagrams of the arrangement of gate trenches and stress correction trenches of a wafer structure for manufacturing trench gate devices according to the present invention.
[0021] Description of Figure Numbers
[0022] 01 Wafer
[0023] 011 Chip Area
[0024] 012 Zoning
[0025] 013 Gate Trench
[0026] 014 Gate lead-out region
[0027] 1 Wafer body
[0028] 11 Chip Area
[0029] 111 Quarantine
[0030] 112 Gate lead-out region
[0031] 113 Terminal Area
[0032] 12. Zoning
[0033] 13 Gate trench
[0034] 131 First Groove
[0035] 132 Second Groove
[0036] 14 Stress correction groove DETAILED DESCRIPTION
[0037] The following is an explanation of the implementation of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific implementations, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.
[0038] See also Figures 2 to 11 It should be noted that the illustrations provided in this embodiment are only used to schematically illustrate the basic concept of the utility model, and the drawings only show the components related to the utility model rather than the number, shape and size of the components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.
[0039] Embodiment 1
[0040] This embodiment provides a wafer structure for manufacturing a trench gate device, such as Figures 2 to 11 As shown, several schematic diagrams of the arrangement of gate grooves and stress correction grooves of the wafer structure for manufacturing trench gate devices include a wafer body 1, a gate groove 13 and a stress correction groove 14, wherein the wafer body 1 includes a plurality of chip areas 11 and a dicing area 12 located between two adjacent chip areas 11, the chip area 11 includes at least one cell area 111; the gate groove 13 is located in the cell area 111; the stress correction groove 14 is located in the dicing area 12, the stress correction groove 14 surrounds the chip area 11, the extension direction of the opening of the stress correction groove 14 is different from that of the gate groove 13, and the opening shape of the stress correction groove 14 is a square waveform or a triangular waveform.
[0041] Specifically, the size and shape of the wafer body 1 are selected according to actual production needs and are not limited here; the number, size and shape of the chip areas 11 in the wafer body 1 can be selected according to actual production needs and are not limited here.
[0042] Specifically, the dicing area 12 is used as an area for cutting the wafer body 1 after the trench gate devices are manufactured in the wafer body 1, so as to avoid damaging the trench gate devices manufactured in the chip area 11 when dicing the wafer body 1 after the trench gate devices are manufactured in each chip area 11.
[0043] Specifically, under the condition that the trench gate device manufactured will not be damaged during the subsequent dicing process, the size of the dicing area 12 can be selected according to actual conditions and is not limited here.
[0044] Specifically, the cell region 111 is used to manufacture a trench gate device. Under the condition of ensuring the performance of the trench gate device, the size and shape of the cell region 111 can be selected according to actual conditions and are not limited here.
[0045] Specifically, the chip region 11 further includes a terminal region 113 surrounding the cell region 111 . The terminal region 113 is used as a terminal structure for manufacturing a semiconductor device to ensure the performance of the semiconductor device.
[0046] Specifically, while ensuring device performance, the size and shape of the terminal region 113 can be selected according to actual conditions and are not limited here.
[0047] Specifically, the method of forming the gate trench 13 includes dry etching, wet etching or other suitable methods; the method of forming the stress modification trench 14 includes dry etching, wet etching or other suitable methods.
[0048] Specifically, under the condition of ensuring the performance of the trench gate device, the opening size and depth of the gate trench 13 can be selected according to actual conditions and are not limited here.
[0049] As an example, the gate trench 13 in the same chip area 11 includes a first trench 131 and a second trench 132, and the openings of the first trench 131 and the second trench 132 extend in different directions, that is, in the gate trench 13 in the same chip area 11, the first trench 131 extends along a first direction, and the second trench 132 extends along a second direction, and the first direction and the second direction are at a preset angle and are not parallel. The preset angle here can be any angle between 0° and 90° (excluding 0° and including 90°).
[0050] Specifically, by utilizing the different extension directions of the openings of the first groove 131 and the second groove 132, the stress concentrated in the same direction caused by the formation of the gate groove 13 in the same chip area 11 can be reduced, and then the warping degree of the wafer 1 caused by the stress introduced by the formation of the gate groove 13 can be improved.
[0051] Specifically, while ensuring the performance of the manufactured trench gate device, the first trench 131, the second trench 132 and the stress correction trench 14 can be formed simultaneously or in steps. The step-by-step formation here can be that the first trench 131 and the second trench 132 are formed simultaneously, and the stress correction trench 14 is formed separately; the first trench 131 and the stress correction trench 14 are formed simultaneously, and the second trench 132 is formed separately; the second trench 132 and the stress correction trench 14 are formed simultaneously; the first trench 131 is formed separately, or the first trench 131, the second trench 132 and the stress correction trench 14 are formed separately.
[0052] Specifically, while ensuring the performance of the trench gate device, the opening size and depth of the first trench 131 can be selected according to actual conditions; the opening size and depth of the second trench 132 can be selected according to actual conditions; the opening size and depth of the stress correction groove 14 can be selected according to actual conditions, for example, the opening size and depth of the first trench 131 and the second trench 132 are the same, and the opening size and depth of the first trench 131 and the second trench 132 are different from the opening size and depth of the stress correction groove 14.
[0053] As an example, the extension direction of the first groove 131 is perpendicular to the extension direction of the opening of the second groove 132, that is, the angle between the first direction and the second direction is 90°. Figure 2 and Figure 5 shown.
[0054] Specifically, by arranging the first groove 131 and the second groove 132 orthogonally, the stress introduced after the formation of the first groove 131 and the second groove 132 can be more dispersed, so that the stress generated in various directions in the chip area 11 is more balanced, and the warping degree of the wafer body 1 caused by the formation of the first groove 131 and the second groove 132 is further reduced.
[0055] As an example, the openings of the first grooves 131 in two adjacent chip areas 11 extend in the same direction, and the openings of the second grooves 132 in two adjacent chip areas 11 extend in the same direction, that is, the openings of the first grooves 131 in each chip area 11 of the wafer body 1 extend along the first direction, and the openings of the second grooves 132 extend along the second direction. Figure 3 and Figure 5 shown.
[0056] Specifically, in the same chip area 11, the extension direction of the openings of the first groove 131 and the second groove 132 is the same, and in two adjacent chip areas 11, the extension direction of the opening of the first groove 131 is different, and the extension direction of the opening of the second groove 132 is different, that is, in two adjacent chip areas 11 of the wafer body 1, the opening of the first groove 131 in the first chip area 11 extends along the first direction, and the opening of the second groove 132 extends along the second direction, and the opening of the first groove 131 in the second chip area 11 extends along the third direction, and the opening of the second groove 132 extends along the fourth direction, the first direction is parallel to the second direction, the third direction is parallel to the fourth direction, the first direction is not parallel to the third direction, and the second direction is not parallel to the fourth direction, such as Figure 4 and Figure 6 shown.
[0057] Specifically, by making the extension directions of the first grooves 131 and the second grooves 132 in each chip area 11 of the wafer body 1 the same and the extension directions of the gate grooves 13 in two adjacent chip areas 11 different, the stress directions generated by the first grooves 131 and the second grooves 132 in different chip areas 11 in the wafer body 1 are different, thereby avoiding the stress concentration in the same direction generated by the different chip areas 11 in the wafer body 1, and then the warping of the wafer body 1 caused by the first grooves 131 and the second grooves 132 can be improved.
[0058] Specifically, in the same chip area 11, the extension directions of the openings of the first groove 131 and the second groove 132 are different, and in two adjacent chip areas 11, the extension directions of the openings of the first groove 131 are different, and the extension directions of the openings of the second groove 132 are different, that is, in two adjacent chip areas 11, the opening of the first groove 131 in the first chip area 11 extends along the first direction, and the opening of the second groove 132 extends along the second direction, and the opening of the first groove 131 in the second chip area 11 extends along the third direction, and the opening of the second groove 132 extends along the fourth direction, the first direction is not parallel to the second direction, the third direction is not parallel to the fourth direction, the first direction is not parallel to the third direction, and the second direction is not parallel to the fourth direction.
[0059] Specifically, by making the extension directions of the first grooves 131 of different chip areas 11 in the wafer body 1 different and the extension directions of the second grooves 132 also different, the stress generated by forming the first grooves 131 and the second grooves 132 in different chip areas 11 is more dispersed, avoiding the accumulation of stress in the same direction in different chip areas 11, and further improving the warping of the wafer body 1 caused by the formation of the gate grooves 13.
[0060] As an example, the extension directions of the openings of the gate trenches 13 in two adjacent chip areas 11 are different, that is, the gate trenches 13 in the two adjacent chip areas 11, the opening direction of the gate trench 13 in the first chip area 11 is along the first direction, and the opening direction of the gate trench 13 in the second chip area 11 is along the second direction, and the first direction is not parallel to the second direction, so that the directions of the stress introduced by the gate trenches 13 in different chip areas 11 are different, thereby reducing the stress accumulated in the wafer body 1 and improving the warping of the wafer body 1, such as Figure 7 shown.
[0061] As an example, the stress correction grooves 14 surrounding the chip regions 11 are interconnected, that is, the stress correction grooves 14 surround each chip region 11 in the scribe area 12 and are connected end to end. Figures 2 to 6 shown.
[0062] As an example, the stress correction grooves 14 surrounding the chip area 11 are arranged at intervals in the scribing area 12 around the chip area 11, that is, the stress correction grooves 14 in the scribing area 12 in all directions around the chip area 11 are arranged at intervals, for example, the stress correction groove 14 located above the chip area 11 is spaced apart from the stress correction groove 14 located on the left side of the chip area 11 by a preset distance, or the stress correction grooves 14 located on any one side or multiple sides of the chip area 11 are arranged in sections, such as Figures 7 to 11 shown.
[0063] Specifically, the stress correction groove 14 is used to correct the stress accumulated in various directions of the entire chip area 11 to further reduce the stress accumulated in various directions in the entire wafer body 1 and improve the warping problem of the wafer body 1 caused by forming gate grooves 13 in each chip area 11.
[0064] Specifically, since the stress correction groove 14 is used to correct the stress accumulated in various directions in each chip area 11 surrounded by it, the shape, size, depth and position of the stress correction groove 14 need to be adjusted according to the stress accumulated in various directions in each chip area 11. For example, the stress correction grooves 14 surrounding each chip area 11 can be symmetrically distributed or asymmetrically distributed; the stress correction grooves 14 surrounding each chip area 11 can be discontinuously segmented or continuously distributed; the opening shapes of each segment of the stress correction grooves 14 surrounding each chip area 11 can be the same or different.
[0065] As an example, the opening shape of the stress correction groove 14 is a triangular waveform, and the angle between the stress correction grooves 14 on both sides of the peak point of the triangular wave and the extension direction of the stress correction groove 14 between two adjacent chip areas 11 is + / -45°, that is, the stress correction grooves 14 on both sides of the peak point of the stress correction groove 14 are perpendicular to each other, so as to correct the stress generated after the mutually perpendicular gate grooves 13 are formed in the chip area 11.
[0066] Specifically, by setting a stress correction groove 14 in the dicing area 12, the stress generated in various parts of the wafer body 1 after the gate groove 13 is formed is more dispersed, and the stress generated in the dicing area 12 is offset by the stress in various directions generated in the chip area 11, thereby reducing the stress on the entire wafer body 1 and improving the warping problem of the wafer body 1.
[0067] As an example, a gate lead-out region 112 is further provided in the chip region 11 , and the gates of the trench gate devices in the same chip region 11 are all led to the gate lead-out region 112 .
[0068] Specifically, the gate lead-out region 112 is used to lead out the gate of the trench gate device in each chip region 11. Under the condition of ensuring the performance of the trench gate device, the size, shape and position of the gate lead-out region 112 can be selected according to actual conditions and are not limited here.
[0069] Specifically, when the gate trench 13 includes the first trench 131 and the second trench 132 , an isolation region 111 is further provided in the chip region 11 to prevent the trench gate device manufactured based on the first trench 131 and the trench gate device manufactured based on the second trench 132 from influencing each other.
[0070] Specifically, while ensuring the performance of the trench gate device, the size of the isolation region 111 can be selected according to actual conditions and is not limited here.
[0071] Specifically, the trench gate device manufactured based on the wafer body 1 may be a trench gate MOS device or a trench gate IGBT device. In this embodiment, the trench gate device manufactured based on the wafer body 1 is a trench gate IGBT device.
[0072] Specifically, the extension direction of the opening of the gate groove 13 in each chip area 11 of the wafer body 1 is adjusted to reduce the stress accumulated in the same direction in each chip area 11 or the entire wafer body 1. At the same time, the stress correction groove 14 surrounding each chip area 11 is used to correct the stress accumulated in each chip area 11, so as to further reduce the stress accumulated in various directions of the wafer body 1, improve the warping of the wafer body 1, facilitate improving the alignment accuracy of subsequent processes, and improve the process consistency of each trench gate device in the entire wafer body 1.
[0073] Specifically, since the stress correction groove 14 is disposed in the scribing area 12, it is avoided that the stress on the wafer body 1 is corrected while affecting the performance of the trench gate device.
[0074] The wafer structure for manufacturing trench gate devices of this embodiment adjusts the extension direction of the opening of the gate trench 13 in each chip area 11 in the wafer body 1 to avoid the concentration of stress in the same direction in each chip area 11 or the wafer body 1, so that the stress on each chip area 11 or the wafer 1 is reduced, and at the same time, the stress generated in each chip area 11 is corrected by the stress correction groove 14 surrounding the chip area 11, so that the stress on the entire wafer body 1 is further reduced, and then the warpage of the wafer body 1 is improved, which is convenient for improving the alignment accuracy of the subsequent process and improving the process consistency of each trench gate device in the entire wafer body 1. In addition, since the stress correction groove 14 is set in the scribe area 12, it is avoided that the stress on the wafer body 1 is corrected while affecting the performance of the trench gate device.
[0075] Embodiment 2
[0076] This embodiment provides a trench gate device, which is manufactured based on the wafer structure for manufacturing the trench gate device described in the first embodiment.
[0077] Specifically, since the trench gate device is manufactured by using the wafer structure for manufacturing the trench gate device described in the first embodiment, when the gate groove 13 is formed, the stress on the wafer body 1 is corrected by the stress correction groove 14 in the dicing area 12, thereby avoiding the warping of the wafer body 1, providing good process conditions for the subsequent photolithography alignment of the contact holes for leading out the gate and the emitter (source), reducing the error of the photolithography alignment, improving the consistency of the chip process, and ensuring the performance of the trench gate device.
[0078] Specifically, since the trench gate device is manufactured based on the wafer structure for manufacturing the trench gate device described in the first embodiment, the warping of the wafer body 1 is avoided, and the subsequent processes are guaranteed.
[0079] The trench gate device of this embodiment is manufactured based on the wafer structure for manufacturing the trench gate device described in the first embodiment, which avoids the warping of the wafer body 1, provides good process conditions for subsequent processes, ensures the normal progress of subsequent processes, reduces the error of lithography alignment, improves the process consistency of the chip, and ensures the performance of the trench gate device.
[0080] In summary, the wafer structure for manufacturing trench gate devices of the utility model adjusts the extension direction of the opening of the gate trench in each chip area of the wafer to avoid the accumulation of stress in the same direction in each chip area or wafer, so that the stress on each chip area or wafer is small, and at the same time, the stress correction groove surrounding the chip area is used to correct the stress generated in each chip area, so that the stress on the entire wafer is further reduced, thereby improving the warpage of the wafer, providing good process conditions for the subsequent process of manufacturing trench gate devices, ensuring the normal progress of subsequent processes, reducing the error of photolithography alignment, and improving the process consistency of trench gate devices. Moreover, the stress correction groove is formed in the dicing area, avoiding the influence of the formed stress correction groove on the performance of the trench gate device, and ensuring the performance of the trench gate device. Therefore, the utility model effectively overcomes various shortcomings in the prior art and has a high industrial utilization value.
[0081] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the technology may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed in the present invention shall still be covered by the claims of the present invention.
Claims
1. A wafer structure for manufacturing a trench gate device, characterized in that: include: A wafer body, comprising a plurality of chip areas and a dicing area between two adjacent chip areas, wherein the chip area comprises at least one cell area; A gate trench is located in the cell region; A stress correction groove is located in the scribing area, the stress correction groove surrounds the chip area, the extension direction of the opening of the stress correction groove is different from that of the gate groove, and the opening shape of the stress correction groove is square waveform or triangular waveform.
2. The wafer structure for manufacturing a trench gate device according to claim 1, characterized in that: The gate trenches in the same chip region include a first trench and a second trench, and the openings of the first trench and the second trench extend in different directions.
3. The wafer structure for manufacturing a trench gate device according to claim 2, characterized in that: An extending direction of the first groove is perpendicular to an extending direction of the opening of the second groove.
4. The wafer structure for manufacturing a trench gate device according to claim 2, characterized in that: The extension directions of the openings of the first trenches in two adjacent chip regions are the same, and the extension directions of the openings of the second trenches in two adjacent chip regions are the same.
5. The wafer structure for manufacturing a trench gate device according to claim 2, characterized in that: In the same chip area, the openings of the first trench and the second trench extend in different directions, and in two adjacent chip areas, the openings of the first trench extend in different directions and the openings of the second trench extend in different directions.
6. The wafer structure for manufacturing a trench gate device according to claim 1, characterized in that: The extension directions of the openings of the gate trenches in two adjacent chip regions are different.
7. The wafer structure for manufacturing a trench gate device according to claim 1, characterized in that: The stress correction grooves surrounding the chip area are connected to each other.
8. The wafer structure for manufacturing a trench gate device according to claim 1, characterized in that: The stress correction grooves surrounding the chip area are arranged at intervals in the scribe area around the chip area.
9. The wafer structure for manufacturing a trench gate device according to claim 1, characterized in that: The opening shape of the stress correction groove is a triangular waveform, and the angle between the stress correction grooves on both sides of the peak point of the triangular waveform and the extension direction of the stress correction groove between two adjacent chip areas is + / -45°.
10. The wafer structure for manufacturing a trench gate device according to claim 1, characterized in that: A gate lead-out region is also provided in the chip region, and the gates of the trench gate devices in the same chip region are all led to the gate lead-out region.