Vertical HEMT-LED integrated device

Abstract

The utility model relates to the technical field of semiconductors, in particular to a vertical HEMT-LED (High Electron Mobility Transistor-Light Emitting Diode) integrated device, in the device, an HEMT (High Electron Mobility Transistor) and an LED are respectively positioned on the front surface and the back surface of a substrate, so that the transverse area of the HEMT-LED integrated device is reduced, the HEMT comprises an HEMT epitaxial layer, a source electrode, a drain electrode and a grid electrode, the LED comprises an LED epitaxial layer, an N electrode and a P electrode, a first conductive hole or a second conductive hole is arranged in the substrate, and the first conductive hole or the second conductive hole is arranged in the substrate. And the source electrode of the HEMT is connected with the P electrode of the LED through the second conductive hole to form a common anode structure, or the drain electrode of the HEMT is connected with the N electrode of the LED through the first conductive hole to form a common cathode structure, so that the integration of the HEMT and the LED is realized, and in the integrated device, the HEMT has the advantages of high frequency and high electron mobility, and the high-frequency control requirement of the LED is favorably met.

Description

Technical Field

[0001] The utility model relates to the technical field of semiconductors, in particular to a vertical HEMT-LED integrated device. Background Art

[0002] At present, there are two main types of LED monolithic integrated structures: the integrated structure of HEMT (high electron mobility field effect transistor) and LED (light emitting diode) (HEMT-LED integrated device), and the integrated structure of MOSFET (metal oxide semiconductor field effect transistor) and LED (MOSFET-LED integrated device). MOSFET or HEMT is used to control LED and drive LED display or lighting.

[0003] The commonly used HEMT-LED integrated device is a lateral structure, that is, the HEMT and the LED are distributed on the same side of the substrate. For example, the prior art provides a HEMT and blue light LED monolithic integrated chip and a preparation method thereof (application number: 202210749251.4), but this structure occupies a large lateral area, which is not conducive to its promotion and application in products with limited lateral space (such as micro display screens).

[0004] The prior art provides a fully vertical MOSFET-LED monolithic integrated device and a preparation method thereof (application number: 202111524989.2). In the MOSFET-LED monolithic integrated device, the MOSFET and the LED are distributed on both sides of the substrate, which can effectively reduce the lateral area. However, compared with HEMT, the frequency and electron mobility of MOSFET are lower, and cannot meet the high-frequency control requirements of LED. Summary of the invention

[0005] In view of the above-mentioned deficiencies, the present application provides a vertical HEMT-LED integrated device, which can reduce the lateral area and meet the high-frequency control requirements of the LED.

[0006] To achieve the above objectives, this application is implemented through the following technical solutions:

[0007] A vertical HEMT-LED integrated device comprises a substrate, wherein a HEMT and an LED are arranged on the front and back sides of the substrate respectively, the HEMT comprises a HEMT epitaxial layer, a source electrode, a drain electrode and a gate electrode; the LED comprises an LED epitaxial layer, an N electrode and a P electrode; a first conductive hole or a second conductive hole is opened in the substrate, the HEMT and the LED are in a common anode structure, or the HEMT and the LED are in a common cathode structure;

[0008] The common anode structure means that the source is electrically connected to the P electrode through the corresponding second conductive hole, the drain is the input end of the HEMT-LED integrated device, and the N electrode is the output end of the HEMT-LED integrated device; the common cathode structure means that the drain is connected to the N electrode through the corresponding first conductive hole, the P electrode is the input end of the HEMT-LED integrated device, and the source is the output end of the HEMT-LED integrated device.

[0009] Furthermore, the HEMT epitaxial layer includes a buffer layer, a channel layer, a blocking layer, a barrier layer, and a cap layer distributed in sequence from bottom to top, and the LED epitaxial layer includes an N-type semiconductor layer, a quantum well layer, and a P-type semiconductor layer distributed in sequence from top to bottom.

[0010] Furthermore, the thickness of the buffer layer is greater than or equal to 2 μm, the thickness of the channel layer is 20 nm to 400 nm, the thickness of the barrier layer is 8 nm to 30 nm, and the thickness of the cap layer is 1 nm to 5 nm.

[0011] Furthermore, the thickness of the N-type semiconductor layer is 1.5 μm to 2.0 μm, the thickness of the quantum well layer is 130 nm to 140 nm, and the thickness of the P-type semiconductor layer is 0.9 μm to 1.2 μm.

[0012] Furthermore, the surface of the HEMT epitaxial layer is covered with a first insulating layer, the source, drain and gate are all located on the top of the first insulating layer, and the bottom local areas of the source, drain and gate respectively penetrate the first insulating layer and are electrically connected to the cap layer.

[0013] Furthermore, a current spreading layer is provided on the top of the LED epitaxial layer, and the current spreading layer is electrically connected to the P-type semiconductor layer.

[0014] Furthermore, the entire surface including the surface of the current spreading layer is covered with a second insulating layer.

[0015] Furthermore, the P electrode is located at the top of the second insulating layer, and a local area of ​​the bottom end of the P electrode penetrates through the second insulating layer and is electrically connected to the current spreading layer.

[0016] Furthermore, the N-electrode is located at the top of the second insulating layer, and a local area of ​​the bottom end of the N-electrode penetrates the second insulating layer and is electrically connected to the N-type semiconductor layer.

[0017] Furthermore, at least one lateral edge of the N-type semiconductor layer extends to form a step, and when the HEMT and the LED are in a common cathode structure, the N-electrode is arranged close to the step surface of the first conductive hole, and when the HEMT and the LED are in a common anode structure, the N-electrode is arranged away from the step surface of the second conductive hole.

[0018] Furthermore, a plurality of array-distributed HEMTs and LEDs are respectively arranged on the front and back sides of the substrate, the HEMTs and LEDs are arranged in one-to-one correspondence, two adjacent HEMTs are electrically isolated by the first insulating layer, and two adjacent LEDs are electrically isolated by the second insulating layer.

[0019] Compared with the prior art, the beneficial effects of the present application are as follows: the HEMT and the LED are located on the front and back sides of the substrate, respectively, thereby reducing the lateral area of ​​the HEMT-LED integrated device, and the HEMT and the LED are a common anode structure, or the HEMT and the LED are a common cathode structure, thereby realizing the integration of the HEMT and the LED. The integrated device is convenient for driving and controlling the LED by utilizing the HEMT with the advantages of high frequency and high electron mobility, thereby meeting the high-frequency control requirements of the LED. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 is a schematic cross-sectional structural diagram of Embodiment 1 of the present application;

[0021] Figure 2 is a schematic cross-sectional structural diagram of the second embodiment of the present application;

[0022] Figure 3 This is a schematic cross-sectional structure diagram of preparing a HEMT epitaxial layer and an LED epitaxial layer on the front and back sides of a substrate in the preparation method of Example 1 of the present application;

[0023] Figure 4 This is a schematic diagram of the cross-sectional structure after the first insulating layer is formed in the preparation method of Example 1 of the present application;

[0024] Figure 5 This is a schematic diagram of the cross-sectional structure after the second insulating layer is formed in the preparation method of Example 1 of the present application;

[0025] Figure 6 This is a schematic diagram of the cross-sectional structure after the first conductive hole is formed in the preparation method of Example 1 of the present application;

[0026] Figure 7 This is a schematic diagram of the cross-sectional structure after the first etching groove and the second etching groove are formed in the preparation method of Example 1 of the present application;

[0027] Figure 8This is a schematic diagram of the cross-sectional structure after forming a HEMT in the preparation method of Example 1 of the present application;

[0028] Fig. 9 This is a schematic diagram of the cross-sectional structure after the fourth etching groove and the fifth etching groove are formed in the preparation method of Example 1 of the present application;

[0029] Fig.10 This is a schematic cross-sectional structure diagram of preparing a HEMT epitaxial layer and an LED epitaxial layer on the front and back sides of a substrate, respectively, in the preparation method of Example 2 of the present application;

[0030] Fig.11 This is a schematic diagram of the cross-sectional structure after the first insulating layer is formed in the preparation method of Example 2 of the present application;

[0031] Fig.12 This is a schematic diagram of the cross-sectional structure after the second insulating layer is formed in the preparation method of Example 2 of the present application;

[0032] Fig.13 This is a schematic diagram of the cross-sectional structure after the second conductive hole is formed in the preparation method of Example 2 of the present application;

[0033] Fig.14 This is a schematic diagram of the cross-sectional structure after the sixth etching groove and the seventh etching groove are formed in the preparation method of Example 2 of the present application;

[0034] Fig.15 This is a schematic diagram of the cross-sectional structure after forming a HEMT in the preparation method of Example 2 of the present application;

[0035] Fig.16 This is a schematic diagram of the cross-sectional structure after the ninth etching groove and the tenth etching groove are formed in the preparation method of Example 2 of the present application;

[0036] Fig.17 This is the circuit schematic diagram of the HEMT-LED in the common cathode structure of the present application;

[0037] Fig.18 This is the circuit schematic diagram of the HEMT-LED in the common anode structure of the present application.

[0038] The meanings of the reference numerals are as follows: substrate 1, HEMT epitaxial layer 2, source 3, drain 4, gate 5, LED epitaxial layer 6, N electrode 7, P electrode 8, current spreading layer 9;

[0039] Buffer layer 21, channel layer 22, blocking layer 23, barrier layer 24, cap layer 25;

[0040] N-type semiconductor layer 61, quantum well layer 62, P-type semiconductor layer 63;

[0041] Buffer material 2001, channel material 2002, blocking material 2003, barrier material 2004, cap material 2005;

[0042] N-type semiconductor material 6001, quantum well material 6002, P-type semiconductor material 6003;

[0043] A first conductive via 101, a second conductive via 102, a first insulating layer 103, and a second insulating layer 104;

[0044] The first etching groove 201 , the second etching groove 202 , the third etching groove 203 , the fourth etching groove 204 , the fifth etching groove 205 , the sixth etching groove 206 , the seventh etching groove 207 , the eighth etching groove 208 , the ninth etching groove 209 , and the tenth etching groove 210 . DETAILED DESCRIPTION

[0045] In order to enable those skilled in the art to better understand the solution of the utility model, the technical solution in the embodiment of the utility model will be clearly and completely described below in conjunction with the drawings in the embodiment of the utility model. Obviously, the described embodiment is only a part of the embodiment of the utility model, not all of the embodiments. Based on the embodiment of the utility model, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the utility model.

[0046] It should be noted that the terms "including" and "having" and any variations thereof in the specification and claims of the present invention and the above-mentioned drawings are intended to cover non-exclusive inclusions. For example, a process, method, apparatus, product or equipment comprising a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or equipment.

[0047] The specific implementation of the present invention is further described in detail below in conjunction with the accompanying drawings and technical solutions. Embodiment 1

[0048] refer to Figure 1 A vertical HEMT-LED integrated device includes a substrate 1, the material of the substrate 1 is preferably Si. It should be noted that the present application does not specifically limit the material of the substrate 1. In another embodiment, the substrate 1 can be made of sapphire, SiC or GaN.

[0049] HEMT and LED are arranged on the front and back of the substrate respectively. HEMT includes HEMT epitaxial layer 2, source 3, drain 4 and gate 5. HEMT epitaxial layer 2 includes buffer layer 21, channel layer 22, blocking layer 23, barrier layer 24 and cap layer 25 which are sequentially distributed from bottom to top. Due to the polarization effect between barrier layer 24 and channel layer 22, the HEMT device forms a high-density and high-mobility two-dimensional electron gas on one side of channel layer 22. Gate 5 is a Schottky contact, which is conducive to controlling the concentration of two-dimensional electron gas. A positive voltage is applied between drain 4 and source 3 to form a gate-controlled leakage current.

[0050] In this embodiment, the material of the buffer layer 21 and the channel layer 22 is preferably GaN, the thickness of the buffer layer 21 is greater than or equal to 2μm, preferably 2μm, the thickness of the channel layer 22 is 20nm~400nm, preferably 200nm, the material of the blocking layer 23 is AlN, the material of the barrier layer 24 is AlGaN, the thickness is 8nm~30nm, preferably 25nm, wherein the Al content is 0.2at.%~0.3at.%, preferably 0.25at.%, and the material of the cap layer 25 is GaN, the thickness is 1nm~5nm, preferably 2nm.

[0051] It should be noted that the present application does not specifically limit the material of the buffer layer 21 . In another embodiment, the material of the buffer layer 21 is AlN or AlGaN.

[0052] The LED includes an LED epitaxial layer 6, an N electrode 7, and a P electrode 8. The LED epitaxial layer 6 includes an N-type semiconductor layer 61, a quantum well layer 62, and a P-type semiconductor layer 63, which are distributed in sequence from top to bottom. The N-type semiconductor layer 61 is made of N-type GaN with a thickness of 1.5μm to 2.0μm, preferably 1.7μm. The P-type semiconductor layer 63 is made of P-type GaN with a thickness of 0.9μm to 1.2μm, preferably 1.0μm. The thickness of the quantum well layer 62 is 130nm to 140nm, preferably 135nm.

[0053] The LED emits blue light or green light. The material of the N-type semiconductor layer 61 is N-type GaN, and the material of the P-type semiconductor layer 63 is P-type GaN.

[0054] In this embodiment, in order to facilitate the driving control of the HEMT to the LED, the HEMT and the LED are in a common cathode structure, and the common cathode structure means that the drain 4 is connected to the N electrode 7, the P electrode 8 is the input end of the HEMT-LED integrated device, and the source 3 is the output end of the HEMT-LED integrated device.

[0055] To facilitate the connection between the drain 4 and the N electrode 7, the present solution opens a first conductive hole 101 in the substrate 1. The filling metal in the first conductive hole 101 includes but is not limited to at least one of In, Sn, Au, Ta, and Cu. Cu is preferred in this embodiment. The drain 4 and the N electrode 7 are interconnected through the corresponding first conductive hole 101.

[0056] In the HEMT, the source 3, the drain 4 and the gate 5 are located in the HEMT epitaxial layer, the gate 5 and the source 3 are electrically connected to the cap layer 25 respectively, the drain 4 is electrically connected to the cap layer 25, and is electrically connected to the N electrode 7 in the LED through the first conductive hole 101, and the material of the gate 5, the source 3, and the drain 4 includes but is not limited to at least one of Cr, Al, Ti, Pt, Au, Ni, and W. In this embodiment, Ti and Al are preferred. The Ti layer and the Al layer are stacked in sequence from bottom to top, and the thicknesses are 50 nm and 110 nm respectively.

[0057] It should be noted that in another embodiment, the source 3 and the drain 4 can be made of Ti, Al, Ni, and Au, and the Ti layer, Al layer, Ni layer, and Au layer are stacked in sequence from bottom to top, with deposition thicknesses of 20nm, 20nm, 20nm, and 200nm, respectively. The material of the gate 5 is preferably Ni and Au, and the Ni layer and Au layer are stacked in sequence from bottom to top, with deposition thicknesses of 50nm and 300nm, respectively.

[0058] In the LED, the P electrode 8 is electrically connected to the P-type semiconductor layer 63 through the current expansion layer 9 at the top of the LED epitaxial layer. At least one side of the N-type semiconductor layer 61 extends to the edge to form a step. In this embodiment, both sides of the N-type semiconductor layer 61 extend to the edge respectively, so that the LED epitaxial layer 6 forms a "convex" shape, wherein the N electrode 7 is located on the step surface close to the first conductive hole 101 and is electrically connected to the N-type semiconductor layer 61. The material of the N electrode 7 and the P electrode 8 is at least one of Cr, Al, Ti, Pt, Au, Ni, and W, and Au is preferred in this embodiment. The surface where the P electrode of the LED is located is the light-emitting surface. Setting the LED epitaxial layer 6 to a "convex" shape facilitates the connection between the N electrode 7 and the N-type semiconductor layer 61, and at the same time avoids the N electrode 7 from blocking the light emitting of the LED, which is beneficial to improving the light emitting efficiency of the LED.

[0059] In addition, in the circuit composed of the above HEMT-LED integrated device, the P electrode 8 of the LED is a current input terminal for connecting the power supply V DD , the source 3 of HEMT is the current output terminal, reference Fig.17 .

[0060] A method for preparing the vertical HEMT-LED integrated device is provided below, and the preparation steps include:

[0061] S1. Provide a substrate 1, which is a double-polished Si substrate. The Si substrate is opaque, which is beneficial for further preventing the LED light from passing through the substrate and affecting the performance of the HEMT.

[0062] S2. Using metal organic chemical vapor deposition (ie MOCVD), photolithography and etching processes, a HEMT epitaxial layer 2 is prepared on the front side of the substrate 1, and using metal organic chemical vapor deposition (ie MOCVD), photolithography and etching processes, a LED epitaxial layer 6 is prepared on the reverse side of the substrate.

[0063] The specific preparation steps include:

[0064] S21, using a metal organic chemical vapor deposition process, sequentially depositing a buffer material 2001, a channel material 2002, a blocking material 2003, a barrier material 2004, and a cap layer material 2005 on the front side of the substrate; the buffer material is AlN, GaN or AlGaN, the channel material is GaN, the blocking material is AlN, the barrier material is AlGaN, and the cap layer material is GaN;

[0065] S22, using metal organic chemical vapor deposition process, depositing N-type semiconductor material 6001 and P-type semiconductor material 6003 on the back of the substrate in sequence, the area where the N-type semiconductor material 6001 and the P-type semiconductor material 6003 contact is the quantum well material 6002, reference Figure 3 ;

[0066] S23, using exposure, development, dry etching (such as ICP etching) or wet etching, the cap layer material 2005, the barrier material 2004, the blocking material 2003, the channel material 2002, and the buffer material 2001 are sequentially etched to a depth of the substrate to form a buffer layer 21, a channel layer 22, a blocking layer 23, a barrier layer 24, and a cap layer 25 distributed in sequence from bottom to top, and a plurality of array-distributed HEMT epitaxial layers 2 are obtained.

[0067] S24, using a plasma enhanced chemical vapor deposition process, depositing a first insulating material on the entire surface including the surface of the HEMT epitaxial layer to form a first insulating layer 103, wherein the first insulating material is preferably SiO 2 or Si 3 N 4 , the HEMT epitaxial layers 2 distributed in the array are electrically isolated from each other by the first insulating layer 103, referring to Figure 4 , which is helpful to further avoid the impact on the electrical performance of HEMT.

[0068] S25. Use exposure, development, dry etching (such as ICP etching) or wet etching to sequentially etch the P-type semiconductor material (such as P-GaN) and the N-type semiconductor material (such as N-GaN), and the etching depth reaches the top of the N-type semiconductor material or the inside of the N-type semiconductor material to form an N-type semiconductor layer 61, a quantum well layer 62, and a P-type semiconductor layer 63 distributed in sequence from top to bottom, and obtain a plurality of "convex" LED epitaxial layers 6 distributed in an array.

[0069] S26, using plasma enhanced chemical vapor deposition process (PECVD) to deposit current spreading material: ITO on the entire surface including the surface of the LED epitaxial layer;

[0070] S27, performing patterning etching on the current spreading material by exposure, development, dry etching (such as ICP etching) or wet etching to form a current spreading layer 9, wherein the current spreading layer 9 covers the surface of the P-type semiconductor layer 63 and is electrically connected to the P-type semiconductor layer 63;

[0071] S28, using a plasma enhanced chemical vapor deposition process, depositing a second insulating material on the entire surface including the surface of the current spreading layer to form a second insulating layer 104, wherein the second insulating material is preferably SiO 2 The second insulating layer 104 is used to electrically isolate the LED epitaxial layers 6 distributed in the array from each other, referring to Figure 5 .

[0072] S3, using photolithography, etching and deposition processes to prepare the drain 4, the source 3 and the gate 5, the specific preparation steps include:

[0073] S31, using exposure, development, dry etching (such as ICP etching) or wet etching to sequentially etch the edge local area of ​​the first insulating layer 103, the substrate local area, and the N-type semiconductor layer local area to form a first through hole;

[0074] S32, electroplating a first conductive metal: Cu in the first through hole to form a first conductive hole 101, reference Figure 6 ;

[0075] S33, using photolithography and etching process, deposition process, prepare drain 4, source 3, specifically including: S331, using exposure, development, dry etching (such as ICP etching) or wet etching, the first insulating layer 103 is patterned and etched, the etching depth is respectively to the top edge of both sides of the cap layer or the inside of the cap layer, to form a first etching groove 201 and a second etching groove 202, wherein the first etching groove 201 corresponds to the first conductive hole 101, refer to Figure 7 ;

[0076] S332, depositing metal materials in the first etching groove 201 and the second etching groove 202 respectively to form an ohmic contact drain 4 and a source 3, wherein the drain 4 is located at the top of the first conductive hole and is electrically connected to the cap layer 25 and the N-type semiconductor layer 61 through the first conductive hole 101, and the source 3 is electrically connected to the cap layer 25;

[0077] S333, performing patterned etching on the first insulating layer 103 by exposure, development, dry etching (such as ICP etching) or wet etching, and etching to a depth of a local area on the top of the cap layer or inside the cap layer to form a third etching groove 203;

[0078] S334, depositing metal materials such as Ni and Au in the third etching groove 203 to form a gate 5 of Schottky contact, and obtaining a HEMT, referring to Figure 8 .

[0079] S4, using photolithography and etching process, deposition process to prepare P electrode 8, N electrode 7, the specific preparation steps include:

[0080] S41, using exposure, development, and wet etching to perform patterned etching on the second insulating material, and the etching depth reaches the current spreading layer and the top or inside of the N-type semiconductor layer to form a fourth etching groove 204 and a fifth etching groove 206, respectively, Fig. 9 In this step, the etching solution is: HNO with a concentration of 70% 3 (i.e. nitric acid) and 50% HF (i.e. hydrogen fluoride) are mixed in a volume ratio of 10:1, the etching temperature is 40°C, and the corrosion time is 30 minutes.

[0081] S42, using a plasma chemical vapor deposition process, depositing metal materials in the fourth etching groove 204 and the fifth etching groove 206, respectively, wherein the metal materials are preferably Al or Pt, to form an N electrode 7 and a P electrode 8, wherein the N electrode 7 is located at the edge of the N-type semiconductor layer and is electrically connected to the cap layer 25 and the drain 4 through the first conductive hole 101, and the P electrode 8 is electrically connected to the P-type semiconductor layer 63 through the current spreading layer 9, to obtain an LED, reference Figure 1 .

[0082] To ensure the surface cleanliness and prevent dust and the like from contaminating the surface and affecting subsequent processes, before performing the above steps S24, S26, S28, S32, S332, S334, and S42, the overall structure obtained in the corresponding previous step is cleaned with ultrapure water and then dried with a spin dryer.

[0083] In addition, in the photolithography and etching processes of steps S23, S25, S27, S31, S331, S333, and S41, wet etching or dry etching is used for etching. During the photolithography process, the photoresist is coated as a whole, that is, the surface where the HEMT is located and the surface where the LED is located are coated with the photoresist. The main function is to prevent the etching solution (such as HNO 3 A mixed solution of HF and MgCl2) or etching gas (such as boron trichloride) etches the side that does not need to be etched, affecting the electrical properties of the device.

[0084] It should be noted that in the first embodiment, in the HEMT-LED integrated device prepared by the above method, the HEMT and the LED are respectively distributed in an array manner on the front and back sides of the substrate. In another embodiment, after the HEMT and the LED are prepared, the substrate can be cut to obtain a number of independent HEMT-LED integrated devices. Embodiment 2

[0085] refer to Figure 2 A vertical HEMT-LED integrated device includes a substrate 1, wherein the material of the substrate 1 is preferably Si, which has a light-proof effect, and is conducive to further preventing the light emitted by the LED from passing through the substrate 1 and affecting the performance of the HEMT. It should be noted that the present application does not specifically limit the material of the substrate 1. In another embodiment, the substrate 1 can be made of sapphire, SiC or GaN.

[0086] HEMT and LED are arranged on the front and back sides of the substrate respectively. The HEMT includes a HEMT epitaxial layer 2, a source electrode 3, a drain electrode 4 and a gate electrode 5. The HEMT epitaxial layer 2 includes a buffer layer 21, a channel layer 22, a blocking layer 23, a barrier layer 24 and a cap layer 25 which are sequentially distributed from bottom to top. In this embodiment, the materials of the buffer layer 21 and the channel layer 22 are preferably GaN. The thickness of the buffer layer 21 is greater than or equal to 2μm, preferably 5μm, the thickness of the channel layer 22 is 20nm~400nm, preferably 300nm, the material of the blocking layer 23 is AlN, the material of the barrier layer 24 is AlGaN, the thickness is 8nm~30nm, preferably 25nm, wherein the content of Al is 0.2at.%~0.3at.%, preferably 0.25at.%, and the material of the cap layer 25 is GaN, the thickness is 1nm~5nm, preferably 4nm.

[0087] It should be noted that the present application does not specifically limit the material of the buffer layer 21 . In another embodiment, the material of the buffer layer 21 is AlN or AlGaN.

[0088] The LED includes an LED epitaxial layer 6, an N electrode 7, and a P electrode 8. The LED epitaxial layer 6 includes an N-type semiconductor layer 61, a quantum well layer 62, and a P-type semiconductor layer 63, which are distributed in sequence from top to bottom. The N-type semiconductor layer 61 is made of N-type GaN with a thickness of 1.5μm to 2.0μm, preferably 1.8μm. The P-type semiconductor layer 63 is made of P-type GaN with a thickness of 0.9μm to 1.2μm, preferably 1.1μm. The thickness of the quantum well layer 62 is 130nm to 140nm, preferably 133nm.

[0089] In this embodiment, the HEMT and the LED have a common anode structure, which means that the source 3 is connected to the P electrode 8, the drain 4 is the input end of the HEMT-LED integrated device, and the N electrode 7 is the output end of the HEMT-LED integrated device.

[0090] To facilitate the connection between the source 3 and the P electrode 8, the present solution opens a second conductive hole 102 in the substrate 1. The filling metal in the second conductive hole 102 includes but is not limited to at least one of In, Sn, Au, Ta, and Cu. In the present embodiment, the filling metal in the second conductive hole 102 is preferably Cu. The source 3 and the P electrode 8 are interconnected through the corresponding second conductive hole 102.

[0091] The source 3, drain 4 and gate 5 are located in the HEMT epitaxial layer, the gate 5 and drain 4 are electrically connected to the cap layer 25, the source 3 is electrically connected to the cap layer 25, and is electrically connected to the P electrode 8 in the LED through the second conductive hole 102. The material of the source 3 and drain 7 includes but is not limited to at least one of Cr, Al, Ti, Pt, Au, Ni, and W. In this embodiment, Ti and Al are preferred. The Ti layer and the Al layer are stacked in sequence from bottom to top, and the thicknesses are 50nm and 110nm, respectively.

[0092] In the LED, at least one side of the N-type semiconductor layer 61 protrudes to form a step. In this embodiment, one side of the N-type semiconductor layer 61 extends to the edge to form a step, so that the LED epitaxial layer 6 forms an "L" shape, wherein the step is located on the side of the LED epitaxial layer 6 away from the second conductive hole 102, and the N electrode 7 is located on the surface of the step and is electrically connected to the N-type semiconductor layer 61. The P electrode 8 is electrically connected to the P-type semiconductor layer 63 through the current expansion layer 9. The material of the N electrode 7 and the P electrode 8 includes but is not limited to at least one of Cr, Al, Ti, Pt, Au, Ni, and W, and Al is preferred in this embodiment. Setting the LED epitaxial layer 6 to an "L" shape facilitates the connection between the N electrode 7 and the N-type semiconductor layer 61, while avoiding the N electrode 7 from blocking the light output of the LED, which is beneficial to improving the light output efficiency of the LED.

[0093] In the circuit composed of the above HEMT-LED integrated device, the drain 4 of the HEMT is a current input terminal for connecting the power supply V DD, the N electrode 7 of the LED is the current output terminal, refer to Fig.18 .

[0094] A method for preparing the vertical HEMT-LED integrated device is provided below, and the preparation steps include:

[0095] S1. Provide a substrate 1, which is a double-polished Si substrate.

[0096] S2. A HEMT epitaxial layer 2 is prepared on the front side of the substrate 1 by using metal organic chemical vapor deposition (ie MOCVD), photolithography and etching processes, and an LED epitaxial layer 6 is prepared on the reverse side of the substrate 1 by using metal organic chemical vapor deposition (ie MOCVD), photolithography and etching processes.

[0097] The specific preparation steps include:

[0098] S21, using a metal organic chemical vapor deposition process, sequentially depositing a buffer material 2001, a channel material 2002, a blocking material 2003, a barrier material 2004, and a cap layer material 2005 on the front side of the substrate; the buffer material is AlN, GaN or AlGaN, the channel material is GaN, the blocking material is AlN, the barrier material is AlGaN, and the cap layer material is GaN;

[0099] S22, using metal organic chemical vapor deposition process, depositing N-type semiconductor material 6001 and P-type semiconductor material 6003 on the back of the substrate in sequence, the area where the N-type semiconductor material 6001 and the P-type semiconductor material contact is the quantum well material 6002, reference Fig.10 ;

[0100] S23, using exposure, development, dry etching (such as ICP etching) or wet etching, the cap layer material 2005, the barrier material 2004, the blocking material 2003, the channel material 2002, and the buffer material 2001 are sequentially etched to a depth of the substrate to form a first etched groove and a buffer layer 21, a channel layer 22, a blocking layer 23, a barrier layer 24, and a cap layer 25 sequentially distributed from bottom to top, to obtain a plurality of array-distributed HEMT epitaxial layers 2.

[0101] S24, using a plasma enhanced chemical vapor deposition process, depositing a first insulating material on the entire surface including the surface of the HEMT epitaxial layer to form a first insulating layer 103, wherein the first insulating material is preferably SiO 2 or Si 3 N 4 , the HEMT epitaxial layers 2 distributed in the array are electrically isolated from each other by the first insulating layer 103, referring to Fig.11 .

[0102] S25. Use exposure, development, dry etching (such as ICP etching) or wet etching to sequentially etch the P-type semiconductor material (such as P-GaN) and the N-type semiconductor material (such as N-GaN). The etching depth on one side is to the top of the N-type semiconductor material or the inside of the N-type semiconductor material, and the etching depth on the other side is to the substrate, forming an N-type semiconductor layer 61, a quantum well layer 62, and a P-type semiconductor layer 63 distributed in sequence from top to bottom, and obtaining a plurality of "L"-shaped LED epitaxial layers 6 distributed in an array.

[0103] S26, using plasma enhanced chemical vapor deposition process (PECVD) to deposit current spreading material: ITO on the entire surface including the surface of the LED epitaxial layer;

[0104] S27, performing patterning etching on the current spreading material by exposure, development, dry etching (such as ICP etching) or wet etching to form a current spreading layer 9, wherein the current spreading layer 9 covers the surface of the P-type semiconductor layer and is electrically connected to the P-type semiconductor layer 63;

[0105] S28, depositing a second insulating material on the entire surface including the surface of the current spreading layer to form a second insulating layer 104, wherein the second insulating material is preferably SiO 2 ,refer to Fig.12 The second insulating layer 104 is used to electrically isolate the array-distributed LED epitaxial layers 6 from each other.

[0106] S3, using photolithography and etching process, deposition process to prepare drain 4, source 3, gate 5, the specific preparation steps include:

[0107] S31, using exposure, development, dry etching (such as ICP etching) or wet etching to sequentially etch the edge local area of ​​the first insulating layer 103 and the substrate local area to form a second through hole;

[0108] S32, electroplating the first conductive metal: Cu in the second through hole to form a second conductive hole 102, reference Fig.13 ;

[0109] S33, using photolithography, etching and deposition processes to prepare the drain 4 and the source 3, specifically including:

[0110] S331, using exposure, development, dry etching (such as ICP etching) or wet etching, the first insulating layer 103 is patterned and etched to a depth of the top of the second conductive hole and the cap layer and a local area of ​​the cap layer at its periphery, to form a sixth etching groove 206 and a seventh etching groove 207, with reference to Fig.14 ;

[0111] S332, depositing metal materials in the sixth etching groove 206 and the seventh etching groove 207 respectively to form an ohmic contact source 3 and a drain 4, wherein the source 3 is located at the top of the second conductive hole and is electrically connected to the cap layer 25 through the second conductive hole 102, and the drain 4 is electrically connected to the cap layer 25;

[0112] S333, performing patterned etching on a local area of ​​the first insulating layer 103 by exposure, development, dry etching (such as ICP etching) or wet etching, and etching to a depth of a local area of ​​the cap layer to form an eighth etching groove 208;

[0113] S334, depositing metal materials such as Ni and Au in the eighth etching groove 208 to form a gate of Schottky contact to obtain a HEMT, referring to Fig.15 .

[0114] S4, using photolithography and etching process, deposition process to prepare P electrode 8, N electrode 7, the specific preparation steps include:

[0115] S41, using exposure, development, and wet etching, the second insulating material is patterned and etched to a depth of the current spreading layer 9 close to the edge of the second conductive hole 102 and the bottom of the second conductive hole, and the top or the inside of the step of the N-type semiconductor layer 61 away from the second conductive hole 102, to form a ninth etching groove 209 and a tenth etching groove 210, respectively. Fig.16 In this step, wet etching is used, and the etching solution is: HNO with a concentration of 70% 3 (i.e. nitric acid) and 50% HF (i.e. hydrogen fluoride) are mixed in a volume ratio of 10:1, the etching temperature is 40°C, and the corrosion time is 30 minutes.

[0116] S42, using a plasma chemical vapor deposition process, depositing metal materials in the ninth etching groove 209 and the tenth etching groove 210 respectively, wherein the metal material is preferably Al or Pt, to form a P electrode and an N electrode, wherein the N electrode 7 is located at a step on one side of the N-type semiconductor layer 61, and the P electrode 8 is L-shaped, located at the top edge of the current spreading layer 9 and extending to the bottom of the second conductive hole 102, and the source 3 of the HEMT is electrically connected to the P-type semiconductor layer 63 through the second conductive hole 102, the P electrode 8, and the current spreading layer 9, to obtain an LED, and referring to Figure 2 .

[0117] To ensure the surface cleanliness and prevent dust and the like from contaminating the surface and affecting subsequent processes, before performing the above steps S24, S26, S28, S32, S332, S334, and S42, the structure obtained in the previous step is cleaned with ultrapure water and then dried with a spin dryer.

[0118] In addition, in the photolithography and etching processes of steps S23, S25, S27, S31, S331, S333, and S41, wet etching or dry etching is used for etching. During the photolithography process, the photoresist is coated as a whole, that is, the surface where the HEMT is located and the surface where the LED is located are coated with the photoresist. The main function is to prevent the etching solution (such as HNO 3 A mixed solution of HF and MgCl2) or etching gas (such as boron trichloride) etches the side that does not need to be etched, affecting the electrical properties of the device.

[0119] It should be noted that in the first embodiment, in the HEMT-LED integrated device prepared by the above method, the HEMT and the LED are respectively distributed in an array manner on the front and back sides of the substrate. In another embodiment, after the HEMT and the LED are prepared, the substrate can be cut to obtain a number of independent HEMT-LED integrated devices.

[0120] In the above-mentioned first and second embodiments, the light emitting surface of the LED is located on the side away from the substrate 1. When the source 3 and the drain 4 of the HEMT are conducting, the gate voltage of the HEMT can control the conduction current of the HEMT. Specifically, the gate 5 of the HEMT controls whether the drain 4 and the source 3 are conducting or not. When the drain 4 and the source 3 are not conducting or the current is lower than the LED light-emitting threshold, the LED does not emit light. When the drain 4 and the source 3 are conducting or the current is higher than the LED light-emitting threshold, the LED emits light. The gate 5 of the HEMT can control the conduction current between the drain 4 and the source 3. The conduction current is large, and the current flowing through the LED increases, thereby controlling the current flowing through the LED and realizing the control of the LED light intensity. The wire bonding connection method has a large pad volume and is easy to occupy more space, which is not conducive to reducing the size of the overall device. The present application uses the first conductive hole or the second conductive hole connection method, which is not only conducive to saving space and simplifying the overall structure of the HEMT-LED integrated device, but also conducive to reducing the heat loss caused by the external lead. If the electrical connection between HEMT and LED is achieved through wires, the Joule heat generated by the wire resistance will increase the heat loss.

[0121] In the present application, the HEMT and LED are located on the front and back sides of the substrate respectively, forming a HEMT-LED integrated device with a vertical structure, which effectively reduces the lateral area, meets the use requirements of limited lateral space, and is conducive to the application of HEMT-LED integrated devices in the field of LED micro-display.

[0122] In addition, in traditional LED display screens, LEDs are controlled by Si-based field effect transistors (such as MOSFET). If HEMT is used as a driver to control the brightness and refresh rate of the LED, the refresh rate can be higher due to the advantage of high operating frequency of HEMT, thereby improving the display quality of the LED display screen.

[0123] When HEMT and LED integrated devices are applied to sensors, especially when the substance to be detected is a photosensitive substance (such as tetracycline), LED illumination can easily cause changes in the properties of the substance, affecting the accuracy of the biosensor detection results. The HEMT-LED integrated device of the present application is used as a biosensor, and the gate of the HEMT is the sensing signal input terminal of the biosensor. The HEMT-LED integrated device can effectively reduce the influence of LED light on the substance to be detected, ensuring the stability of the properties of the substance to be detected, thereby ensuring the accuracy of the sensor detection results.

[0124] It is understandable that the above specific description of the utility model is only used to illustrate the utility model and is not limited to the technical solution described in the embodiment of the utility model. Those skilled in the art should understand that the utility model can still be modified or replaced by equivalents to achieve the same technical effect; as long as the use requirements are met, they are within the protection scope of the utility model.

Claims

1. A vertical HEMT-LED integrated device, comprising a substrate (1), characterized in that: A HEMT and an LED are arranged on the front and back sides of the substrate respectively, the HEMT comprising a HEMT epitaxial layer (2), a source electrode (3), a drain electrode (4) and a gate electrode (5); the LED comprising an LED epitaxial layer (6), an N electrode (7) and a P electrode (8); a first conductive hole (101) or a second conductive hole (102) is arranged in the substrate (1), the first conductive hole (101) or the second conductive hole (102) passing through the substrate (1); the HEMT and the LED are in a common anode structure, or the HEMT and the LED are in a common cathode structure; The common anode structure means that the source electrode (3) is electrically connected to the P electrode (8) through the corresponding second conductive hole (102), the drain electrode (4) is the input end of the HEMT-LED integrated device, and the N electrode (7) is the output end of the HEMT-LED integrated device; the common cathode structure means that the drain electrode (4) is connected to the N electrode (7) through the corresponding first conductive hole (101), the P electrode (8) is the input end of the HEMT-LED integrated device, and the source electrode (3) is the output end of the HEMT-LED integrated device.

2. The vertical HEMT-LED integrated device according to claim 1, characterized in that: The HEMT epitaxial layer (2) comprises a buffer layer (21), a channel layer (22), a blocking layer (23), a barrier layer (24), and a cap layer (25) which are sequentially distributed from bottom to top, and the LED epitaxial layer (6) comprises an N-type semiconductor layer (61), a quantum well layer (62), and a P-type semiconductor layer (63) which are sequentially distributed from top to bottom.

3. The vertical HEMT-LED integrated device according to claim 2, characterized in that: The thickness of the buffer layer (21) is greater than or equal to 2 μm, the thickness of the channel layer (22) is 20 nm to 400 nm, the thickness of the barrier layer (24) is 8 nm to 30 nm, and the thickness of the cap layer (25) is 1 nm to 5 nm.

4. The vertical HEMT-LED integrated device according to claim 3, characterized in that: The thickness of the N-type semiconductor layer (61) is 1.5 μm to 2.0 μm, the thickness of the quantum well layer (62) is 130 nm to 140 nm, and the thickness of the P-type semiconductor layer (63) is 0.9 μm to 1.2 μm.

5. The vertical HEMT-LED integrated device according to claim 4, characterized in that: The surface of the HEMT epitaxial layer is covered with a first insulating layer (103); the source electrode (3), the drain electrode (4), and the gate electrode (5) are all located at the top of the first insulating layer (103); and local areas at the bottom ends of the source electrode (3), the drain electrode (4), and the gate electrode (5) respectively penetrate the first insulating layer (103) and are electrically connected to the cap layer (25).

6. The vertical HEMT-LED integrated device according to claim 5, characterized in that: A current spreading layer (9) is provided on the top of the LED epitaxial layer, and the current spreading layer (9) is electrically connected to the P-type semiconductor layer (63).

7. The vertical HEMT-LED integrated device according to claim 6, characterized in that: The entire surface including the surface of the current spreading layer (9) is covered with a second insulating layer (104); the N electrode (7) and the P electrode (8) are both located at the top of the second insulating layer (104); a local area at the bottom end of the P electrode (8) passes through the second insulating layer (104) and is electrically connected to the current spreading layer (9); and a local area at the bottom end of the N electrode (7) passes through the second insulating layer (104) and is electrically connected to the N-type semiconductor layer (61).

8. The vertical HEMT-LED integrated device according to claim 7, characterized in that: At least one lateral edge of the N-type semiconductor layer (61) extends to form a step; when the HEMT and the LED are in a common cathode structure, the N-electrode (7) is arranged close to the step surface of the first conductive hole (101); when the HEMT and the LED are in a common anode structure, the N-electrode (7) is arranged away from the step surface of the second conductive hole (102).

9. The vertical HEMT-LED integrated device according to claim 1 or 8, characterized in that: A plurality of array-distributed HEMTs and LEDs are respectively arranged on the front and back sides of the substrate, the HEMTs and LEDs are arranged in one-to-one correspondence, two adjacent HEMTs are electrically isolated by a first insulating layer (103), and two adjacent LEDs are electrically isolated by a second insulating layer (104).

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