A low voltage drop linear regulator and a single chip microcomputer

Abstract

The utility model provides a low voltage difference linear regulator and a single chip microcomputer, wherein the low voltage difference linear regulator includes: an operational amplifier, a first power switch tube, a negative feedback circuit and a bias current supply circuit, the negative feedback circuit includes a resistor voltage divider unit and a transmission gate unit; the first input end of the operational amplifier is used to be electrically connected to an external reference voltage generation circuit, the second input end is electrically connected to the resistor voltage divider unit, the output end is electrically connected to the first power switch tube, the bias current supply circuit is electrically connected to the first power switch tube and the resistor voltage divider unit respectively, the bias current supply circuit and the first common connection end of the resistor voltage divider unit are used to be electrically connected to an external load, and the transmission gate unit is electrically connected to the resistor voltage divider unit. Through the implementation of the utility model, the transmission gate unit adjusts the resistance value of the resistor voltage divider unit, so that the LDO can output voltages of different levels, effectively reducing the static power consumption of the LDO itself.

Description

Technical Field

[0001] The utility model relates to the technical field of circuits, in particular to a low voltage difference linear regulator and a single chip microcomputer. Background Art

[0002] At present, a large number of digital and analog resources are integrated inside the MCU with relatively complete functions. For different functional modules, the operating voltage is also different. In particular, the IO ports of many chips generally support a wide voltage range, which is wider than the voltage range of the digital core. Therefore, it is necessary to add a low dropout linear regulator (Low DropOutregulator, LDO) conversion voltage design inside the chip to power the digital core. When the MCU is in low power mode, the static power consumption of the LDO dominates the power consumption of the entire MCU chip. Under normal circumstances, the LDO inside the chip will be designed according to the maximum power consumption of the system to adapt to the maximum load driving capability, but the larger the driving voltage output by the LDO, the larger the static current and static power consumption will be, resulting in a larger overall power consumption of the chip in low power mode. Utility Model Content

[0003] The utility model provides a low voltage difference linear regulator and a single chip microcomputer, aiming to solve the problem of large overall power consumption of the single chip microcomputer caused by large static power consumption of LDO in the related technology.

[0004] In order to solve the above technical problems, the first aspect of the utility model provides a low voltage difference linear regulator, including: an operational amplifier, a first power switch tube, a negative feedback circuit and a bias current supply circuit, the negative feedback circuit includes a resistor voltage divider unit and a transmission gate unit; the first input end of the operational amplifier is used to be electrically connected to an external reference voltage generation circuit, the second input end is electrically connected to the resistor voltage divider unit, and the output end is electrically connected to the first power switch tube, the bias current supply circuit is electrically connected to the first power switch tube and the resistor voltage divider unit respectively, the bias current supply circuit and the first common connection end of the resistor voltage divider unit are used to be electrically connected to an external load, and the transmission gate unit is electrically connected to the resistor voltage divider unit.

[0005] Further, the resistor divider unit includes a first resistor, a second resistor and a third resistor; the first end of the first resistor is electrically connected to the bias current supply circuit, and the second end is electrically connected to the first end of the second resistor, the first end of the third resistor is electrically connected to the second end of the second resistor, and the second end is grounded, the second common connection end of the second resistor and the third resistor is electrically connected to the second input end of the operational amplifier, and the transmission gate unit is electrically connected to the first end of the first resistor and the second end of the second resistor, respectively.

[0006] Further, the transmission gate unit includes a first transmission gate and a second transmission gate; the first end of the first transmission gate is electrically connected to the first end of the first resistor, the second end is electrically connected to the second end of the first resistor, and the third end and the fourth end are both used to be electrically connected to an external control signal generator; the first end of the second transmission gate is electrically connected to the first end of the second resistor, the second end is electrically connected to the second end of the second resistor, and the third end and the fourth end are both used to be electrically connected to an external control signal generator.

[0007] Furthermore, the bias current supply circuit includes a second power switch tube and a third power switch tube, the source electrodes of the second power switch tube and the third power switch tube are electrically connected to a power supply, the gate electrode of the second power switch tube and the gate electrode of the third power switch tube are interconnected, the drain electrode of the second power switch tube is electrically connected to the drain electrode of the first power switch tube and the gate electrode of the second power switch tube respectively, the drain electrode of the third power switch tube is electrically connected to the resistance voltage divider unit, the gate electrode of the first power switch tube is electrically connected to the operational amplifier, and the source electrode is grounded.

[0008] Furthermore, the low voltage dropout linear regulator further includes a bias current compensation circuit, and the bias current compensation circuit is electrically connected to the bias current supply circuit and the third common connection terminal of the first power switch tube.

[0009] Furthermore, the bias current compensation branch includes a third transmission gate, a fourth resistor and a fifth power switch tube; the first end of the third transmission gate is electrically connected to the power supply, the second end is electrically connected to the fourth resistor, the third end and the fourth end are both used to be electrically connected to an external control signal generator, the source of the fifth power switch tube is electrically connected to the fourth resistor, and the drain of the fifth power switch tube is electrically connected to the gate of the fifth power switch tube and the third common connection end respectively.

[0010] A second aspect of the present invention provides a single chip microcomputer, comprising the low voltage dropout linear regulator as described in the first aspect of the present invention.

[0011] From the above description, it can be seen that the operational amplifier circuit of the utility model is connected to the resistor voltage divider unit, and the resistance value of the resistor in the resistor voltage divider unit can be adjusted through the transmission gate unit, so that the LDO can output a variety of voltages to meet different driving requirements. There is no need to provide the output voltage according to the maximum power consumption requirement, which effectively reduces the static power consumption of the LDO itself. Therefore, when the system works in, for example, a low power consumption mode, the output voltage can be reduced by adjusting the resistance value of the negative feedback circuit, so that the system power consumption can be reduced as the operating voltage decreases. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1This is a circuit schematic diagram of a first low voltage drop linear regulator according to an embodiment of the utility model;

[0013] Figure 2 It is a circuit schematic diagram of a second low voltage drop linear regulator according to an embodiment of the utility model;

[0014] Figure 3 This is a circuit schematic diagram of a third low voltage difference linear regulator according to an embodiment of the utility model. DETAILED DESCRIPTION

[0015] In order to make the purpose, technical scheme and advantages of the utility model clearer, the utility model is further described in detail below in conjunction with the accompanying drawings and embodiments, wherein the same or similar reference numerals throughout represent the same or similar elements or elements with the same or similar functions. It should be understood that the specific embodiments described herein are only used to explain the utility model and are not used to limit the utility model. In addition, the technical features involved in the various embodiments of the utility model described below can be combined with each other as long as they do not conflict with each other.

[0016] In the related art, the low power consumption mode of the single chip microcomputer can be divided into standby mode and shutdown mode: in standby mode, the chip core stops working, and the other peripheral interfaces remain active, and can be awakened by the peripheral interface interrupt to continue working; in shutdown mode, the whole chip stops working, and the chip enters the lowest power consumption mode, and can only be awakened by hard reset to work again. Therefore, when the chip does not need to work a lot, by configuring the chip to enter standby or shutdown mode, different degrees of energy consumption can be saved. In addition, the power consumption of the chip will also change with the change of operating frequency and voltage. The lower the frequency and voltage, the lower the power consumption. The LDO inside the chip is generally designed according to the maximum power consumption of the system to adapt to the maximum driving load, but the LDO driving current is large, the static current is large, and the resistance of the negative feedback loop of the LDO is usually fixed and cannot be adjusted, which will cause the overall power consumption of the chip in low power consumption mode to be large. To this end, the embodiment of the utility model provides a low voltage difference linear regulator.

[0017] like Figure 1The figure shows a circuit schematic diagram of a first low voltage difference linear regulator provided by an embodiment of the utility model, wherein the low voltage difference linear regulator comprises: an operational amplifier 100, a first power switch tube 200, a negative feedback circuit 300 and a bias current supply circuit 400, wherein the negative feedback circuit 300 comprises a resistor voltage divider unit 310 and a transmission gate unit 320; the first input terminal of the operational amplifier 100 is used to be electrically connected to an external reference voltage generating circuit 500, the second input terminal is electrically connected to the resistor voltage divider unit 310, and the output terminal is electrically connected to the first power switch tube 200, the bias current supply circuit 400 is electrically connected to the first power switch tube 200 and the resistor voltage divider unit 310 respectively, the first common connection terminal of the bias current supply circuit 400 and the resistor voltage divider unit 310 is used to be electrically connected to an external load 600, and the transmission gate unit 320 is electrically connected to the resistor voltage divider unit 310.

[0018] Specifically, in this embodiment, the negative input terminal of the operational amplifier 100 is connected to the resistor voltage divider unit 310, which is used to obtain the sampled voltage and compare it with the reference voltage, and then amplify the voltage difference between the two and output it to the first power switch tube 200, so as to adjust the input-output characteristics of the first power switch tube 200 to achieve the effect of adjusting the output voltage, and the bias current supply circuit 400 can be used to provide a stable bias current to control the stability of the output voltage. Since the voltages of the two input terminals of the operational amplifier 100 of the LDO are equal, the output voltage of the LDO is in a resistor voltage division relationship with the reference input voltage of the operational amplifier 100. The resistor voltage divider unit 310 can adjust the resistance through the transmission gate, so that the LDO can output a variety of voltages to meet different driving requirements, and there is no need to provide the output voltage according to the highest power consumption requirement, which effectively reduces the static power consumption of the LDO itself and ensures that the power consumption of the entire chip under each driving requirement is reduced; for example, when the single-chip microcomputer works in a low power consumption mode, the voltage divider resistance can be adjusted to reduce the output voltage, so that the power consumption of the entire chip is reduced as the output voltage is reduced.

[0019] like Figure 2 The circuit schematic diagram of the second low voltage drop linear regulator provided by this embodiment is shown in FIG. Figure 2 The resistor divider unit 310 includes a first resistor R1, a second resistor R2 and a third resistor R3; a first end of the first resistor R1 is electrically connected to the bias current supply circuit 400, and a second end is electrically connected to a first end of the second resistor R2; a first end of the third resistor R3 is electrically connected to a second end of the second resistor R2, and a second end is grounded; a second common connection end of the second resistor R2 and the third resistor R3 is electrically connected to a second input end of the operational amplifier EA (100); and a transmission gate unit 320 is electrically connected to a first end of the first resistor R1 and a second end of the second resistor R2, respectively.

[0020] For further information, see Figure 2The transmission gate unit 320 includes a first transmission gate T1 and a second transmission gate T2; the first end of the first transmission gate T1 is electrically connected to the first end of the first resistor R1, the second end is electrically connected to the second end of the first resistor R1, and the third end and the fourth end are both used to be electrically connected to an external control signal generator; the first end of the second transmission gate T2 is electrically connected to the first end of the second resistor R2, the second end is electrically connected to the second end of the second resistor R2, and the third end and the fourth end are both used to be electrically connected to an external control signal generator.

[0021] Specifically, in this embodiment, the output voltage is described by taking the negative feedback circuit 300 consisting of three resistors and two transmission gates as an example. Among them, the VS signals and N_VS signals of the two control terminals of the two transmission gates are mutually inverted. When the VS_1 signal of the first transmission gate T1 is a high level 1, the first transmission gate T1 is opened and the first resistor R1 is short-circuited; when the VS_2 signal of the second transmission gate T2 is a high level 1, the second transmission gate T2 is opened and the second resistor R2 is short-circuited. Therefore, VS_1 and VS_2 can realize four resistance combinations by configuring different signal types to obtain four output voltages Vout, that is, when VS_1=VS_2=0, the voltage ratio is: Vout / VREF=(R1+R2+R3) / R3, Vout=(R1+R2+R3)*VREF / R3; when VS_1=1, VS_2=0, the voltage ratio is: Vout / VREF=(R2+R3) / R3, Vout=(R2+R3)*VREF / R3; when VS_1=0, VS_2=1, the voltage ratio is: Vout / VREF=(R1+R3) / R3, Vout=(R1+R3)*VREF / R3; when VS_1=VS_2=1, the voltage ratio is: Vout / VREF=1, Vout=VREF. Therefore, by configuring VS_1 and VS_2 signals to select different voltage divider resistors and change the output voltage, the system power consumption is reduced as the operating voltage decreases. The number of adjustable resistors can be adjusted according to actual needs, for example, using a negative feedback circuit 300 structure such as four voltage divider resistors and three transmission gates.

[0022] Further, see Figure 2The bias current supply circuit 400 includes a second power switch tube MP2 and a third power switch tube MP3. The sources of the second power switch tube MP2 and the third power switch tube MP3 are both electrically connected to the power supply. The gate of the second power switch tube MP2 and the gate of the third power switch tube MP3 are interconnected. The drain of the second power switch tube MP2 is electrically connected to the drain of the first power switch tube MN1 (200) and the gate of the second power switch tube MP2 respectively. The drain of the third power switch tube MP3 is electrically connected to the resistor voltage divider unit 310. The gate of the first power switch tube MN1 is electrically connected to the operational amplifier EA, and the source is grounded. Among them, the first power switch tube MN1 is an NMOS tube, and the second power switch tube MP2 and the third power switch tube MP3 are both PMOS tubes.

[0023] Specifically, in this embodiment, the bias current supply circuit 400 adopts a current mirror structure, which can copy a known stable current to the output branch to generate a stable reference current. The reference current is used to compare with the output current to control the output voltage of the LDO and ensure the stability of the output voltage.

[0024] like Figure 3 The third circuit schematic diagram of the low voltage drop linear regulator provided by this embodiment is shown in FIG. Figure 3 The low voltage dropout linear regulator further includes a bias current compensation circuit 700, and the bias current compensation circuit 700 is electrically connected to the bias current supply circuit 400 and the third common connection terminal of the first power switch tube MN1.

[0025] Specifically, the bias current compensation circuit 700 includes a plurality of bias current compensation branches, and the bias current compensation branches are electrically connected to the power supply and the third common connection terminal, respectively. The bias current compensation branch includes a third transmission gate (ST1 / ST2 / ST3 / ST4), a fourth resistor (SR1 / SR2 / SR3 / SR4) and a fifth power switch tube (MSP1 / MSP2 / MSP3 / MSP4); the first end of the third transmission gate is electrically connected to the power supply, the second end is electrically connected to the fourth resistor, and the third end and the fourth end are both used to be electrically connected to the external control signal generator, the source of the fifth power switch tube is electrically connected to the fourth resistor, and the drain of the fifth power switch tube is electrically connected to the gate of the fifth power switch tube and the third common connection terminal, respectively. Among them, the fifth power switch tube is a PMOS tube.

[0026] Specifically, in this embodiment, when the system operates in a low power consumption mode, sufficient driving capability can be provided by the bias current supply circuit 400, and the branch current of the second power switch tube MP2 and the first power switch tube MN1 is designed in proportion to the second power switch tube MP2 and the third power switch tube MP3, which occupies very little static current and has ultra-low power consumption characteristics. When the working state of the system begins to switch to a higher power consumption state, an additional bias circuit path can be set to provide a stronger load driving capability. Therefore, this embodiment is also provided with a bias current compensation circuit, which includes multiple bias current compensation branches, such as Figure 3 There are four bias current compensation branches in the circuit, and the number of branches can be adjusted according to actual needs. According to the voltage and frequency requirements under different conditions, each bias current compensation branch can be turned on accordingly, so that the overall bias current of the LDO increases, and stronger driving capability and transient response are provided in stages. Among them, the bias current compensation branch is controlled by the transmission gate for start and stop. Taking the transmission gate ST1 as an example, the signals S1 and N_S1 at its two control ends are mutually reversed, and the opening and closing of the transmission gate ST1 are controlled by S1. When S1 is a high level 1, the transmission gate is turned on, so that the bias current compensation branch is turned on. The more branches that are turned on, the greater the bias current, and the stronger the driving capability of the LDO. When the chip operates at the highest frequency and runs at the maximum power consumption, all the bias current compensation branches of the LDO can be turned on to provide the maximum load capacity to meet the working requirements of the chip. In addition, the diode connection formed by the second power switch tube MP2 greatly reduces the gate impedance of the third power switch tube MP3, so that under heavy load conditions, the gate frequency of the third power switch tube MP3 is at a high frequency position, thereby improving the frequency stability under different loads.

[0027] The low-dropout linear regulator provided by the embodiment of the utility model adopts a method of adjusting the resistance value of the negative feedback loop, so that the LDO can achieve a variety of voltage outputs and adapt to the power consumption requirements in different scenarios. In addition, by setting a bias current compensation circuit, the LDO can reduce the overall power consumption under light load conditions. At the same time, it can also open an additional bias current path according to actual load requirements and configure the control signal of the transmission gate to dynamically adjust the LDO driving capability, thereby reducing the static power consumption of the LDO itself and the overall power consumption of the single-chip microcomputer, and ensuring that the system's load driving capability meets the requirements of different scenarios.

[0028] The embodiment of the utility model further provides a single chip microcomputer, which includes the above-mentioned low voltage difference linear regulator.

[0029] It should be noted that the various embodiments in the present invention are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same and similar parts between the various embodiments can be referenced to each other.

[0030] It should also be noted that, in the present invention, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise one..." do not exclude the presence of other identical elements in the process, method, article or device including the elements.

[0031] The above description of the disclosed embodiments enables those skilled in the art to implement or use the present invention. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined in the present invention may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to the embodiments shown in the present invention, but will conform to the widest range consistent with the principles and novel features disclosed in the present invention.

Claims

1. A low voltage dropout linear regulator, characterized in that: include: An operational amplifier, a first power switch tube, a negative feedback circuit and a bias current supply circuit, wherein the negative feedback circuit includes a resistor voltage divider unit and a transmission gate unit; The first input terminal of the operational amplifier is used to be electrically connected to an external reference voltage generating circuit, the second input terminal is electrically connected to the resistance voltage divider unit, and the output terminal is electrically connected to the first power switch tube. The bias current supply circuit is electrically connected to the first power switch tube and the resistance voltage divider unit respectively. The bias current supply circuit and the first common connection terminal of the resistance voltage divider unit are used to be electrically connected to an external load, and the transmission gate unit is electrically connected to the resistance voltage divider unit.

2. The low voltage dropout linear regulator according to claim 1, characterized in that: The resistor voltage dividing unit includes a first resistor, a second resistor and a third resistor; A first end of the first resistor is electrically connected to the bias current supply circuit, and a second end of the first resistor is electrically connected to a first end of the second resistor. A first end of the third resistor is electrically connected to a second end of the second resistor, and a second end of the third resistor is grounded. A second common connection end of the second resistor and the third resistor is electrically connected to a second input end of the operational amplifier. The transmission gate unit is electrically connected to a first end of the first resistor and a second end of the second resistor, respectively.

3. The low voltage dropout linear regulator according to claim 2, characterized in that: The transmission gate unit includes a first transmission gate and a second transmission gate; The first end of the first transmission gate is electrically connected to the first end of the first resistor, the second end is electrically connected to the second end of the first resistor, and the third end and the fourth end are both used to be electrically connected to an external control signal generator; the first end of the second transmission gate is electrically connected to the first end of the second resistor, the second end is electrically connected to the second end of the second resistor, and the third end and the fourth end are both used to be electrically connected to an external control signal generator.

4. The low voltage dropout linear regulator according to claim 1, characterized in that: The bias current supply circuit includes a second power switch tube and a third power switch tube, the source electrodes of the second power switch tube and the third power switch tube are both electrically connected to a power supply, the gate electrode of the second power switch tube and the gate electrode of the third power switch tube are interconnected, the drain electrode of the second power switch tube is electrically connected to the drain electrode of the first power switch tube and the gate electrode of the second power switch tube respectively, the drain electrode of the third power switch tube is electrically connected to the resistance voltage divider unit, the gate electrode of the first power switch tube is electrically connected to the operational amplifier, and the source electrode is grounded.

5. The low voltage dropout linear regulator according to claim 4, characterized in that: The first power switch tube is an NMOS tube, and the second power switch tube and the third power switch tube are both PMOS tubes.

6. The low voltage dropout linear regulator according to claim 1, characterized in that: It also includes a bias current compensation circuit, which is electrically connected to the bias current supply circuit and the third common connection terminal of the first power switch tube.

7. The low voltage dropout linear regulator according to claim 6, characterized in that: The bias current compensation circuit includes a plurality of bias current compensation branches, and the bias current compensation branches are electrically connected to a power source and the third common connection terminal respectively.

8. The low voltage dropout linear regulator according to claim 7, characterized in that: The bias current compensation branch includes a third transmission gate, a fourth resistor and a fifth power switch tube; The first end of the third transmission gate is electrically connected to the power supply, the second end is electrically connected to the fourth resistor, and the third end and the fourth end are both used to be electrically connected to an external control signal generator. The source of the fifth power switch tube is electrically connected to the fourth resistor, and the drain of the fifth power switch tube is electrically connected to the gate of the fifth power switch tube and the third common connection end respectively.

9. The low voltage dropout linear regulator according to claim 8, characterized in that: The fifth power switch tube is a PMOS tube.

10. A single chip microcomputer, characterized in that: The invention comprises a low voltage drop linear regulator as claimed in any one of claims 1 to 9.

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