A 4K matte control circuit and matte device

Abstract

The utility model discloses a 4K matting control circuit and matting device, including an FPGA main processing module, a power management module, an image sensor module, a first video signal input module, a first video signal processing module, a first program video signal output module and a multi-screen output module; the power management module is connected with the FPGA main processing module, the image sensor module, the first video signal input module, the first video signal processing module, the first program video signal output module and the multi-screen output module; the image sensor module is connected with the FPGA main processing module, the first video signal input module is connected with the first video signal processing module, the first video signal processing module is connected with the FPGA main processing module, and the FPGA main processing module is connected with the first program video signal output module and the multi-screen output module. The present application can effectively reduce the uncertain factors of video signal input acquisition by an external camera and improve the operation stability of the matting device.

Description

Technical Field

[0001] The utility model relates to the technical field of video streaming, and in particular to a 4K keying control circuit and a keying device. Background Art

[0002] With the development and popularization of high-definition video and ultra-high-definition video, the application of virtual technology is becoming more and more extensive, and virtual live broadcast is one of the more common applications. Compared with the construction of real scenes, the cost of virtual studios is relatively low, but it can achieve the same effect as real scenes, so it has a higher cost performance. Virtual studio is a technology that uses the layout of blue cloth and green cloth on site to produce live or recorded video, and then pushes it to the network platform. In addition, this network push streaming platform can also add station logos, scrolling subtitles, etc. It is powerful and can meet the use needs of various video live broadcast fields.

[0003] In the prior art, the signal input of 4K matte is generally collected by an external camera. The video input signal is input from the HDMI port to the HDMI chip for processing, and then transmitted to the FPGA for processing; or, the video input signal is input from the SD I port to the SD I chip for processing, and then transmitted to the FPGA for processing; or, the video input signal is input from the network port to the network port chip for processing, and then transmitted to the FPGA for processing. Therefore, the existing video sources need to be converted multiple times before being processed by the FPGA, which leads to many uncertain factors in the source of the collected video. For example, some are not true 4K inputs, and the clarity and color difference of the matte output processing are not balanced; the video source is converted several times, and the color depth is damaged; after the input processed video source passes through the Limited Range, the actual color depth range is 16 to 235, the precision of the matte is greatly different, and the video output of the matte does not look delicate and the effect is poor; some cameras do not handle the SENSOR power supply well, and the noise is too large, which will also affect the effect of the matte; the external camera is inconvenient to operate and the cost is high. Therefore, inventing a new and reliable 4K keying control circuit and keying device is an urgent problem to be solved by technicians in this field. Utility Model Content

[0004] The purpose of this application is to provide a 4K matting control circuit and a matting device. In this solution, it is possible to effectively reduce the uncertainty factors of video signal input acquisition by an external camera, improve the various performance parameters of the matting device, and improve the operating stability of the matting device.

[0005] In order to solve the above technical problems, the present application provides a 4K matting control circuit, including an FPGA main processing module, a power management module, an image sensing module, a first video signal input module, a first video signal processing module, a first program video signal output module and a multi-screen output module; the image sensing module has a built-in 4K camera;

[0006] The power management module is electrically connected to the FPGA main processing module, the image sensing module, the first video signal input module, the first video signal processing module, the first program video signal output module and the multi-screen output module respectively;

[0007] The image sensing module is electrically connected to the FPGA main processing module, the first video signal input module is electrically connected to the first video signal processing module, the first video signal processing module is electrically connected to the FPGA main processing module, and the FPGA main processing module is electrically connected to the first program video signal output module and the multi-screen output module respectively.

[0008] Preferably, the 4K keying control circuit further includes a second video signal input module and a second video signal processing module;

[0009] The power management module is electrically connected to the second video signal input module and the second video signal processing module respectively;

[0010] The second video signal input module is electrically connected to the second video signal processing module, and the second video signal processing module is electrically connected to the FPGA main processing module.

[0011] Preferably, the 4K keying control circuit further includes a third video signal input module and a third video signal processing module;

[0012] The power management module is electrically connected to the third video signal input module and the third video signal processing module respectively;

[0013] The third video signal input module is electrically connected to the third video signal processing module, and the third video signal processing module is electrically connected to the FPGA main processing module.

[0014] Preferably, the 4K keying control circuit further includes a second program video signal output module;

[0015] The second program video signal output module is electrically connected to the power management module and the FPGA main processing module respectively.

[0016] Preferably, the image sensing module includes an image sensing unit and a brightness adjustment unit;

[0017] The brightness adjustment unit is electrically connected to the power management module, the image sensing unit and the 4K camera respectively, and the image sensing unit is electrically connected to the FPGA main processing module and the power management module respectively.

[0018] Preferably, the brightness adjustment unit includes a left lens brightness adjustment subunit and a right lens brightness adjustment subunit;

[0019] The left lens brightness adjustment subunit is electrically connected to the power management module, the image sensing unit and the 4K camera respectively;

[0020] The lens right brightness adjustment subunit is electrically connected to the power management module, the image sensing unit and the 4K camera respectively.

[0021] Preferably, the first program video signal output module includes a first program video signal output interface unit and a first electrostatic protection unit;

[0022] The first program video signal output interface unit is electrically connected to the power management module, the FPGA main processing module and the first electrostatic protection unit respectively, and the first electrostatic protection unit is electrically connected to the display device.

[0023] Preferably, the multi-image output module includes a multi-image output interface unit and a second electrostatic protection unit;

[0024] The multi-screen output interface unit is electrically connected to the power management module, the FPGA main processing module and the second electrostatic protection unit respectively, and the two electrostatic protection units are electrically connected to the display device.

[0025] Preferably, the FPGA main processing module includes an FPGA main processor and a FLASH storage unit;

[0026] The FPGA main processor is electrically connected to the first video signal processing module, the first program video signal output module, the multi-screen output module, the power management module and the FLASH storage unit respectively.

[0027] In order to solve the above technical problems, the present application provides a matting device, including the above-mentioned 4K matting control circuit.

[0028] The utility model of a 4K matting control circuit and matting device has the following beneficial effects: the utility model discloses a 4K matting control circuit including an FPGA main processing module, a power management module, an image sensor module, a first video signal input module, a first video signal processing module, a first program video signal output module and a multi-screen output module; the power management module is electrically connected to the FPGA main processing module, the image sensor module, the first video signal input module, the first video signal processing module, the first program video signal output module and the multi-screen output module; the image sensor module is electrically connected to the FPGA main processing module, the first video signal input module is electrically connected to the first video signal processing module, the first video signal processing module is electrically connected to the FPGA main processing module, and the FPGA main processing module is electrically connected to the first program video signal output module and the multi-screen output module. Therefore, the present application can effectively reduce the uncertain factors of video signal input acquisition by an external camera and improve the operation stability of the matting device. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] In order to more clearly illustrate the embodiments of the utility model or the technical solutions in the prior art, the utility model will be further described below in conjunction with the accompanying drawings and embodiments. The drawings described below are only some embodiments of the utility model. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work:

[0030] Figure 1 This is a structural schematic diagram of a 4K keying control circuit in a preferred embodiment of the utility model;

[0031] Figure 2 This is a structural schematic diagram of a 4K keying control circuit in a preferred embodiment of the utility model;

[0032] Figure 3 This is a circuit schematic diagram of an image sensing unit of a 4K matting control circuit in a preferred embodiment of the utility model;

[0033] Figure 4 This is a circuit schematic diagram of a brightness adjustment unit of a 4K keying control circuit in a preferred embodiment of the utility model;

[0034] Figure 5 This is a circuit schematic diagram of a first program video signal output interface unit of a 4K keying control circuit in a preferred embodiment of the utility model;

[0035] Figure 6 This is a circuit schematic diagram of a first electrostatic protection unit of a 4K keying control circuit in a preferred embodiment of the utility model;

[0036] Figure 7The present invention is a circuit diagram of a FLASH storage unit of a 4K matting control circuit according to a preferred embodiment of the present invention. DETAILED DESCRIPTION

[0037] The core of this application is to provide a 4K matting control circuit and a matting device. In this solution, it can effectively reduce the uncertainty factors of video signal input and acquisition by an external camera, improve the various performance parameters of the matting device, and improve the operating stability of the matting device.

[0038] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0039] See also Figure 1 , Figure 1 A structural schematic diagram of a 4K matting control circuit provided in the present application, comprising an FPGA main processing module 1, a power management module 2, an image sensor module 3, a first video signal input module 4, a first video signal processing module 5, a first program video signal output module 6 and a multi-screen output module 7; the image sensor module 3 has a built-in 4K camera;

[0040] The power management module 2 is electrically connected to the FPGA main processing module 1, the image sensing module 3, the first video signal input module 4, the first video signal processing module 5, the first program video signal output module 6 and the multi-screen output module 7 respectively;

[0041] The image sensing module 3 is electrically connected to the FPGA main processing module 1, the first video signal input module 4 is electrically connected to the first video signal processing module 5, the first video signal processing module 5 is electrically connected to the FPGA main processing module 1, and the FPGA main processing module 1 is electrically connected to the first program video signal output module 6 and the multi-screen output module 7 respectively.

[0042] In the prior art, the video sources need to be converted multiple times before they are processed by FPGA, which leads to many uncertainties in the video sources. For example, some are not true 4K inputs, and the clarity and color difference of the cutout output processing are not balanced; the color depth is damaged in the video sources that have been converted several times; after the input processed video source passes through the Limited Range, the actual color depth range is 16 to 235, and the accuracy of the cutout varies greatly, and the cutout output video does not look delicate and the effect is poor; some cameras do not handle the SENSOR power supply well, and the noise is too large, which will also affect the cutout effect; the external camera is inconvenient to operate and the cost is high.

[0043] In view of the above shortcomings, the present application uses an FPGA main processing module 1, a power management module 2, an image sensor module 3, a first video signal input module 4, a first video signal processing module 5, a first program video signal output module 6 and a multi-screen output module 7; the image sensor module 3 is equipped with a built-in 4K camera to achieve reliable and stable cutout data output display.

[0044] Specifically, in this embodiment, the image sensor module 3 has a built-in 4K camera, and no external camera is needed to collect video signals, thus avoiding the operational inconvenience caused by the external camera; in addition, the image sensor module 3 has good photosensitivity, convenient operation and low cost.

[0045] Specifically, in this embodiment, compared with the damage to the video color depth after multiple conversion processing of the external camera, the image sensor module 3 of the built-in 4K camera is used to collect video signals in this application, and the video signal line directly sends the video signal to the FPGA main processing module 1 for keying processing, which effectively utilizes the original Full Range 0~255 color depth, and the video effect after keying processing is natural and delicate.

[0046] Specifically, in this embodiment, the first video signal input module 4 is used to receive the first video signal, the first video signal processing module 5 is used to transmit the first video signal to the FPGA main processing module 1 after transmission processing, and the FPGA main processing module 1 performs cutout, overlay, and merge video processing on the first video signal and the video signal collected by the image sensor module 3.

[0047] Specifically, on the one hand, the FPGA main processing module 1 outputs the video picture after cutting out and splicing through the first program video signal output module 6 to broadcast the program; on the other hand, the FPGA main processing module 1 performs multi-screen processing on the video picture after cutting out and splicing, and outputs it for display through the multi-screen output module 7.

[0048] It is understandable that the first video signal input module 4 can be set as an HDMI input interface, and the first video signal processing module 5 is correspondingly set as an HDMI processing chip. In addition, the first video signal input module 4 can also be set as an SDI interface, and the first video signal processing module 5 is correspondingly set as an SDI processing chip, which is not specifically limited here.

[0049] Specifically, in this embodiment, the built-in camera uses 4K input, and the cutout video source RGB and YCBCR are directly input into the FPGA main processing module 1 for processing, and the video effect is good.

[0050] In summary, the present application provides a 4K matte control circuit, which includes an FPGA main processing module 1, a power management module 2, an image sensor module 3, a first video signal input module 4, a first video signal processing module 5, a first program video signal output module 6 and a multi-screen output module 7; the power management module 2 is electrically connected to the FPGA main processing module 1, the image sensor module 3, the first video signal input module 4, the first video signal processing module 5, the first program video signal output module 6 and the multi-screen output module 7 respectively; the image sensor module 3 is electrically connected to the FPGA main processing module 1, the first video signal input module 4 is electrically connected to the first video signal processing module 5, the first video signal processing module 5 is electrically connected to the FPGA main processing module 1, and the FPGA main processing module 1 is electrically connected to the first program video signal output module 6 and the multi-screen output module 7 respectively. Therefore, the present application can effectively reduce the uncertain factors of video signal input acquisition by an external camera and improve the operation stability of the matte device.

[0051] Based on the above embodiments:

[0052] Please refer to Figure 2 , Figure 2 A schematic diagram of the structure of another 4K keying control circuit provided in this application.

[0053] As a preferred embodiment, a 4K keying control circuit further includes a second video signal input module 8 and a second video signal processing module 9;

[0054] The power management module 2 is electrically connected to the second video signal input module 8 and the second video signal processing module 9 respectively;

[0055] The second video signal input module 8 is electrically connected to the second video signal processing module 9 , and the second video signal processing module 9 is electrically connected to the FPGA main processing module 1 .

[0056] Specifically, in this embodiment, the second video signal input module 8 is used to receive the second video signal, the second video signal processing module 9 is used to transmit the second video signal to the FPGA main processing module 1 after transmission processing, and the FPGA main processing module 1 performs cutout, superposition, and splicing video processing on the second video signal and the video signal collected by the image sensor module 3 and the first video signal.

[0057] It is understandable that the second video signal input module 8 can be set as an HDMI input interface, and the second video signal processing module 9 is correspondingly set as an HDMI processing chip. In addition, the second video signal input module 8 can also be set as an SDI interface, and the second video signal processing module 9 is correspondingly set as an SDI processing chip, which is not specifically limited here.

[0058] As a preferred embodiment, a 4K keying control circuit further includes a third video signal input module 10 and a third video signal processing module 11;

[0059] The power management module 2 is electrically connected to the third video signal input module 10 and the third video signal processing module 11 respectively;

[0060] The third video signal input module 10 is electrically connected to the third video signal processing module 11 , and the third video signal processing module 11 is electrically connected to the FPGA main processing module 1 .

[0061] Specifically, in this embodiment, the third video signal input module 10 is used to receive the third video signal, the third video signal processing module 11 is used to transmit the third video signal to the FPGA main processing module 1 after transmission processing, and the FPGA main processing module 1 performs cutout, overlay, and merge video processing on the third video signal and the video signal collected by the image sensor module 3, the first video signal, and the second video signal.

[0062] It is understandable that the third video signal input module 10 can be set as an HDMI input interface, and the third video signal processing module 11 is correspondingly set as an HDMI processing chip. In addition, the third video signal input module 10 can also be set as an SD I interface, and the third video signal processing module 11 is correspondingly set as an SD I processing chip, which is not specifically limited here.

[0063] It is worth noting that, in this embodiment, the number of video signal input sources can be set according to the desired splicing effect, and is not specifically limited here.

[0064] As a preferred embodiment, a 4K keying control circuit further includes a second program video signal output module 12;

[0065] The second program video signal output module 12 is electrically connected to the power management module 2 and the FPGA main processing module 1 respectively.

[0066] Please refer to Figure 3 , Figure 3 A circuit schematic diagram of an image sensing unit provided in this application.

[0067] Please refer to Figure 4 , Figure 4 A circuit schematic diagram of a brightness adjustment unit provided in this application.

[0068] As a preferred embodiment, the image sensing module 3 includes an image sensing unit 31 and a brightness adjustment unit 32;

[0069] The brightness adjustment unit 32 is electrically connected to the power management module 2 , the image sensor unit 31 and the 4K camera respectively, and the image sensor unit 31 is electrically connected to the FPGA main processing module 1 and the power management module 2 respectively.

[0070] Specifically, in this embodiment, the brightness adjustment unit 32 is used to adjust the brightness of the strong light to improve the clarity of the video signal collected by the image sensing unit 31 .

[0071] As a preferred embodiment, the brightness adjustment unit 32 includes a lens left brightness adjustment subunit and a lens right brightness adjustment subunit;

[0072] The left brightness adjustment subunit of the lens is electrically connected to the power management module 2, the image sensing unit and the 4K camera respectively;

[0073] The lens right brightness adjustment subunit is electrically connected to the power management module 2, the image sensing unit and the 4K camera respectively.

[0074] Specifically, the left lens brightness adjustment subunit and the right lens brightness adjustment subunit are respectively used to realize the brightness adjustment of the left and right sides of the 4K camera.

[0075] Please refer to Figure 5 , Figure 5 A circuit schematic diagram of a first program video signal output interface unit provided in the present application.

[0076] Please refer to Figure 6 , Figure 6 A circuit schematic diagram of a first electrostatic protection unit provided in the present application.

[0077] As a preferred embodiment, the first program video signal output module 6 includes a first program video signal output interface unit and a first electrostatic protection unit;

[0078] The first program video signal output interface unit is electrically connected to the power management module 2, the FPGA main processing module 1 and the first electrostatic protection unit respectively, and the first electrostatic protection unit is electrically connected to the display device.

[0079] Specifically, the first electrostatic protection unit can be set to a BTR04F15 ESD diode, or set to a BTRD10A02ESD diode, which is not specifically limited here.

[0080] As a preferred embodiment, the multi-image output module 7 includes a multi-image output interface unit and a second electrostatic protection unit;

[0081] The multi-screen output interface unit is electrically connected to the power management module 2, the FPGA main processing module 1 and the second electrostatic protection unit respectively, and the second electrostatic protection unit is electrically connected to the display device.

[0082] Specifically, the second electrostatic protection unit can be set to a BTR04F15 ESD diode, or set to a BTRD10A02ESD diode, which is not specifically limited here.

[0083] As a preferred embodiment, the FPGA main processing module 1 includes an FPGA main processor and a FLASH storage unit;

[0084] The FPGA main processor is electrically connected to the first video signal processing module 5, the first program video signal output module 6, the multi-image output module 7, the power management module 2 and the FLASH storage unit respectively.

[0085] Please refer to Figure 7 , Figure 7 A circuit diagram of a FLASH storage unit provided in this application.

[0086] Specifically, in this embodiment, the program of the 4K camera is stored in the FLASH storage unit of the FGPA and can be directly called by the FGPA, which has high flexibility.

[0087] The present application also provides a matte matte device, including a 4K matte matte control circuit.

[0088] For an introduction to a 4K matting control circuit provided in the present application, please refer to the above-mentioned embodiment, and the present application will not go into details here.

[0089] It should be noted that, in this specification, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "includes a ..." does not exclude the existence of other identical elements in the process, method, article or device including the element.

[0090] The above description of the disclosed embodiments enables those skilled in the art to implement or use the present application. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present application. Therefore, the present application will not be limited to the embodiments shown herein, but will conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A 4K keying control circuit, characterized in that: It includes an FPGA main processing module, a power management module, an image sensing module, a first video signal input module, a first video signal processing module, a first program video signal output module and a multi-screen output module; the image sensing module has a built-in 4K camera; The power management module is electrically connected to the FPGA main processing module, the image sensing module, the first video signal input module, the first video signal processing module, the first program video signal output module and the multi-screen output module respectively; The image sensing module is electrically connected to the FPGA main processing module, the first video signal input module is electrically connected to the first video signal processing module, the first video signal processing module is electrically connected to the FPGA main processing module, and the FPGA main processing module is electrically connected to the first program video signal output module and the multi-screen output module respectively.

2. A 4K keying control circuit according to claim 1, characterized in that: The 4K keying control circuit further includes a second video signal input module and a second video signal processing module; The power management module is electrically connected to the second video signal input module and the second video signal processing module respectively; The second video signal input module is electrically connected to the second video signal processing module, and the second video signal processing module is electrically connected to the FPGA main processing module.

3. A 4K keying control circuit according to claim 2, characterized in that: The 4K keying control circuit further includes a third video signal input module and a third video signal processing module; The power management module is electrically connected to the third video signal input module and the third video signal processing module respectively; The third video signal input module is electrically connected to the third video signal processing module, and the third video signal processing module is electrically connected to the FPGA main processing module.

4. The 4K keying control circuit according to claim 1, characterized in that: The 4K keying control circuit further includes a second program video signal output module; The second program video signal output module is electrically connected to the power management module and the FPGA main processing module respectively.

5. The 4K keying control circuit according to claim 1, characterized in that: The image sensing module includes an image sensing unit and a brightness adjustment unit; The brightness adjustment unit is electrically connected to the power management module, the image sensing unit and the 4K camera respectively, and the image sensing unit is electrically connected to the FPGA main processing module and the power management module respectively.

6. The 4K keying control circuit according to claim 5, characterized in that: The brightness adjustment unit includes a left lens brightness adjustment subunit and a right lens brightness adjustment subunit; The left lens brightness adjustment subunit is electrically connected to the power management module, the image sensing unit and the 4K camera respectively; The lens right brightness adjustment subunit is electrically connected to the power management module, the image sensing unit and the 4K camera respectively.

7. The 4K keying control circuit according to claim 1, characterized in that: The first program video signal output module includes a first program video signal output interface unit and a first electrostatic protection unit; The first program video signal output interface unit is electrically connected to the power management module, the FPGA main processing module and the first electrostatic protection unit respectively, and the first electrostatic protection unit is electrically connected to the display device.

8. The 4K keying control circuit according to claim 1, characterized in that: The multi-image output module includes a multi-image output interface unit and a second electrostatic protection unit; The multi-screen output interface unit is electrically connected to the power management module, the FPGA main processing module and the second electrostatic protection unit respectively, and the two electrostatic protection units are electrically connected to the display device.

9. The 4K keying control circuit according to claim 1, characterized in that: The FPGA main processing module includes an FPGA main processor and a FLASH storage unit; The FPGA main processor is electrically connected to the first video signal processing module, the first program video signal output module, the multi-screen output module, the power management module and the FLASH storage unit respectively.

10. A matting device, characterized in that: A 4K keying control circuit comprising any one of claims 1 to 9.

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