Semiconductor structure

Abstract

One example semiconductor structure includes a fin structure formed from a substrate and extending longitudinally in a direction, an isolation feature over the substrate and around the fin structure, a gate structure wrapping a channel region of the fin structure, a first gate spacer extending along a sidewall of the gate structure, a second gate spacer over the first gate spacer, a semiconductor device includes a fin structure, a second gate spacer over the fin structure, a filler dielectric layer over the second gate spacer, an epitaxial feature disposed over a source / drain region of the fin structure, a portion of the epitaxial feature disposed over the filler dielectric layer, a contact etch stop layer over the epitaxial feature and the filler dielectric layer, and an interlayer dielectric layer over the contact etch stop layer. A portion of the contact etch stop layer extends in a direction between the epitaxial feature and a sidewall of the gate structure.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor structure. Background Art

[0002] The semiconductor industry has experienced rapid growth. Technological advances in semiconductor materials and design have produced generations of semiconductor devices, each with smaller and more complex circuits than the previous generation. In the development of integrated circuits (ICs), functional density (i.e., the number of interconnected devices per wafer area) has generally increased, while geometry size (i.e., the smallest component (or line) that can be made using a manufacturing process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and reducing associated costs. However, these advances have also increased the complexity of processing and manufacturing semiconductor devices.

[0003] The shrinking size of semiconductor structures has shortened the distance between conductive features (such as gate structures, source / drain features, and contact features) and has brought challenges to parasitic capacitance reduction and response time increase. Various methods have been proposed to reduce parasitic capacitance. Therefore, existing parasitic capacitance reduction methods are generally sufficient for their intended purposes, but they are not satisfactory in various aspects. Utility Model Content

[0004] The present disclosure provides a semiconductor structure. The semiconductor structure includes a fin structure formed from a substrate and extending longitudinally in a direction, an isolation feature disposed above the substrate and around the fin structure, a gate structure wrapping a channel region of the fin structure and disposed above the isolation feature, a first gate spacer extending along the sidewall of the gate structure and the top surface of the isolation feature, a second gate spacer disposed above the first gate spacer, a filling dielectric layer disposed above the second gate spacer, an epitaxial feature disposed above the source / drain region of the fin structure, a contact etch stop layer disposed above the epitaxial feature and the filling dielectric layer, and an interlayer dielectric layer disposed above the contact etch stop layer. A portion of the epitaxial feature is disposed above the filling dielectric layer. A portion of the contact etch stop layer extends between the epitaxial feature and the sidewall of the gate structure along the direction.

[0005] The present disclosure provides a semiconductor structure. The semiconductor structure includes a fin structure formed from a substrate and extending longitudinally in one direction, an isolation feature disposed above the substrate and around the fin structure, a gate structure wrapping a channel region of the fin structure and disposed above the isolation feature, a first gate spacer extending along the sidewall of the gate structure and the top surface of the isolation feature, a second gate spacer disposed above the first gate spacer, a filling dielectric layer disposed above the second gate spacer, an epitaxial feature disposed above the source / drain region of the fin structure, a contact etch stop layer disposed above the epitaxial feature and the filling dielectric layer, and an interlayer dielectric layer disposed above the contact etch stop layer. A portion of the epitaxial feature is disposed above the filling dielectric layer. The top surface of the second gate spacer is higher than the top surface of the filling dielectric layer.

[0006] The present disclosure provides a semiconductor structure. The semiconductor structure includes a fin structure formed from a substrate and extending longitudinally in one direction, an isolation feature disposed above the substrate and around the fin structure, a gate structure wrapping a channel region of the fin structure and disposed above the isolation feature, a first gate spacer extending along the sidewall of the gate structure and the top surface of the isolation feature, a second gate spacer disposed above the first gate spacer, a filling dielectric layer disposed above the second gate spacer, an epitaxial feature disposed above the source / drain region of the fin structure, a contact etch stop layer disposed above the epitaxial feature and the filling dielectric layer, and an interlayer dielectric layer disposed above the contact etch stop layer. A portion of the epitaxial feature is disposed above the filling dielectric layer. The epitaxial feature includes a first portion and a second portion overhanging the isolation feature, and the first portion and the second portion are separated from the gate structure by the filling dielectric layer and the contact etch stop layer along the direction. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The present disclosure can be more fully understood by reading the detailed description of the following embodiments and referring to the accompanying drawings. It should be emphasized that, according to standard practice in the industry, the various features are not drawn to scale. In fact, the size of various features can be arbitrarily increased or reduced for clarity of discussion.

[0008] Figure 1 A flowchart illustrating an example method of fabricating a semiconductor device on a workpiece according to various embodiments of the present disclosure;

[0009] Figures 2 to 23 For various embodiments according to the present disclosure, Figure 1 A cross-sectional view and a top view of a portion of a workpiece are shown.

[0010]

Explanation of symbols

[0011] 100: Methods

[0012] 102: Box

[0013] 104: Box

[0014] 106: Box

[0015] 108: Box

[0016] 110: Box

[0017] 112: Box

[0018] 114: Box

[0019] 116: Box

[0020] 118: Box

[0021] 120: Box

[0022] 122: Box

[0023] 124: Box

[0024] 126: Box

[0025] 200: Artifacts

[0026] 202: Substrate

[0027] 204: Fin structure

[0028] 204C: Channel area

[0029] 204SD: Source / Drain Region

[0030] 206: Isolation Features

[0031] 207: Virtual gate dielectric layer

[0032] 208: Virtual Gate Stack

[0033] 209: Virtual electrode layer

[0034] 210: Gate top hard mask layer

[0035] 212: first gate spacer layer

[0036] 214: Second gate spacer layer

[0037] 216: Virtual sidewall layer

[0038] 2160: The remainder

[0039] 218: Source / drain groove

[0040] 220: Source / Drain Characteristics

[0041] 222: Contact Etch Stop Layer

[0042] 224: Interlayer dielectric layer

[0043] 232: Gate dielectric layer

[0044] 234: Work function layer

[0045] 236: Covering layer

[0046] 238: Metal filling layer

[0047] 240: Gate structure

[0048] 242: Gate top groove

[0049] 244: Metal cover

[0050] 246: Dielectric cap layer

[0051] T1: Thickness

[0052] T2: Thickness

[0053] T3: Thickness DETAILED DESCRIPTION

[0054] The following disclosure provides many different embodiments or embodiments for realizing the different features of the disclosure. In order to simplify the disclosure, specific examples of components and configurations are described below. Of course, these are just examples and are not meant to be restrictive. For example, the formation of the first feature on the second feature in the following description may include an embodiment in which the first and second features are directly in contact, and may also include an embodiment in which additional features are formed between the first and second features, so that the first and second features may not directly contact. In addition, the disclosure may repeat component numbers and / or symbols in various embodiments. This repetition is for simplicity and clarity, and does not limit the relationship between the various embodiments and / or configurations discussed.

[0055] In addition, for ease of description, spatially relative terms, such as "below", "beneath", "below", "above", "above", etc., may be used herein to describe the relationship of one (or some) element or feature to another (or some) element or feature shown in the figure. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figure. The device may be oriented in other orientations (rotated 90 degrees or other orientations), and the spatially relative descriptive symbols used herein may be interpreted accordingly.

[0056] In addition, when a number or range of numbers is described using "about," "approximately," etc., the term is intended to include numbers within a reasonable range that takes into account variations inherent in the manufacturing process, as understood by those skilled in the art. For example, a number or range of numbers includes a reasonable range that includes the described number, such as within + / -10% of the described number, based on known manufacturing tolerances associated with manufacturing the features associated with the number. For example, a material layer with a thickness of "about 5nm" may include a size range of 4.25nm to 5.75nm, where the manufacturing tolerance associated with the deposited material layer is known to be + / -15% by those skilled in the art. Further, the present disclosure may repeat component numbers and / or symbols in various embodiments. This repetition is for simplicity and clarity and does not limit the relationship between the various embodiments and / or configurations discussed.

[0057] As semiconductor devices move toward smaller technology nodes, closely spaced gate structures and source / drain features drive a continued quest to reduce parasitic capacitance to improve switching speeds and device performance. In order to reduce or minimize parasitic capacitance, insulating (or dielectric) materials with relatively low dielectric constants (k), such as low-k dielectrics and / or air (e.g., by forming air gaps), have been explored to insulate the conductive structures of semiconductor devices. While low-k dielectrics are ideal for reducing parasitic capacitance, they tend to etch quickly and are susceptible to accidental damage.

[0058] The present disclosure provides a structure and method for reducing parasitic capacitance between a gate structure and adjacent source / drain features. In an exemplary process, after forming a dummy gate stack on a channel region of a fin structure on a substrate, a gate spacer layer is conformally deposited on the dummy gate group and the substrate. A sacrificial dielectric layer is then conformally deposited above the gate spacer layer. The substrate is subjected to an anisotropic etching process to form a source / drain groove on a source / drain region of the fin structure adjacent to the channel region. The source / drain features are formed above the source / drain features. After the source / drain features are formed, an isotropic etch back process is performed to etch a sacrificial dielectric layer disposed between the source / drain features and the gate spacer layer extending along the sidewalls of the dummy gate stack. After etching, a contact etch stop layer (CESL) is deposited on the source / drain features and the etched sacrificial dielectric layer. The source / drain features are separated from the gate structure by a sacrificial dielectric layer and a contact etch stop layer. The sacrificial dielectric layer has a dielectric constant that is less than the dielectric constant of the contact etch stop layer.

[0059] Various aspects of the disclosure will now be described in more detail with reference to these drawings. Figure 1 A flow chart of a method 100 for forming a semiconductor structure from a workpiece is shown. The method 100 is merely an example and is not intended to limit the present disclosure to that expressly recited in the claims. Additional operations may be provided before, during, and after the method 100, and some of the operations described may be replaced, eliminated, or moved for additional embodiments of the method. The method 100 is described below in conjunction with the accompanying drawings. Figures 2 to 23 , each of which shows a segmented cross-sectional view or a top view of a workpiece 200 during various operations of method 100. Workpiece 200 may be an intermediate structure manufactured during the manufacture of a semiconductor device or structure. The present disclosure is not limited to any particular number of devices or device areas, or any particular device configuration. For example, although the workpiece 200 shown includes fin-type field effect transistors (FinFETs), the present disclosure may also be applied to other types of transistors. Additional features may be added to the semiconductor device manufactured on the workpiece 200, and some of the features described below may be replaced, modified, or eliminated in other embodiments of the semiconductor device to be manufactured on the workpiece 200. Because the semiconductor device or semiconductor structure is formed by the workpiece 200 when completing the process described in the present disclosure, the workpiece 200 may be referred to as a semiconductor device or semiconductor structure as the context requires.

[0060] refer to Figure 1 and Figure 2 , the method 100 includes a block 102, forming a fin structure 204 on a substrate 202. The fin structure 204 is formed on the substrate 202. The substrate 202 may include a base (single element) semiconductor, such as silicon (Si), germanium (Ge), and / or other suitable materials; a compound semiconductor (i.e., an alloy semiconductor), such as silicon carbide (SiC), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs), indium antimonide (InSb), silicon ammonium (SiGe), gallium arsenic phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), gallium indium arsenide (GaInAs), gallium indium phosphide (GaInAs), and / or other suitable materials. The substrate 202 may be a single layer of material having a uniform composition. Optionally, the substrate 202 may include multiple material layers having similar or different compositions suitable for IC device manufacturing. In one example, substrate 202 may be a silicon-on-insulator (SOI) substrate having a silicon layer formed on a buried silicon oxide (BOX) layer. In some embodiments, substrate 202 includes various doped regions, such as n-type dopants or p-type dopants. Depending on design requirements, the doped regions may be doped with n-type dopants, such as phosphorus (P) or arsenic (As) and / or p-type dopants, such as boron (B) or BF2. The doped regions may be formed by implanting doping atoms, in-situ doped epitaxial growth, and / or other suitable techniques.

[0061] In order to form the fin structure 204 from the substrate 202, a fin-top hard mask layer (not explicitly shown in the figure) can be deposited above the substrate 202. In some embodiments, the fin structure 204 is patterned from the substrate 202 using a combination of lithography and etching processes. For patterning purposes, a hard mask layer can be deposited above the substrate 202. The hard mask layer can be a single layer or multiple layers. In one example, the hard mask layer includes a silicon oxide layer and a silicon nitride layer on the silicon oxide layer. The fin structure 204 can be patterned using a suitable process, including a double patterning or multi-patterning process. Typically, a double patterning or multi-patterning process combines lithography and self-alignment processes to produce a pattern with a pitch smaller than that obtainable using a single direct lithography process. For example, in one embodiment, a material layer is formed on a substrate and patterned using a lithography process. Spacers are formed next to the patterned material layer using a self-alignment process. The material layer is then removed, and the remaining spacers or mandrels may then be used as an etching mask to etch the substrate 202 to form the fin structure 204. The etching process may include dry etching, wet etching, reactive ion etching (RIE), and / or other suitable processes. Figure 2 As shown, the fin structure 204 is vertically formed continuously from the substrate 202. The fin structure 204 extends longitudinally along the Y direction.

[0062] refer to Figure 1 and Figure 3 The method 100 includes block 104 of forming an isolation feature 206 around the fin structure 204. Figure 3 As shown, the isolation feature 206 separates the fin structure 204 from another fin structure (omitted for simplicity). In the exemplary process, a dielectric material is first deposited all over the substrate 202 to fill the space between the fin structure 204 and the other fin structure. The dielectric material may include silicon oxide, which may be deposited by a chemical vapor deposition (CVD) or spin-on-glass (SOG) process. A planarization process, such as a chemical mechanical polishing (CMP) process, is then performed. The planarized dielectric material is then selectively etched back to form the isolation feature 206.

[0063] refer to Figure 1 and Figure 4, the method 100 includes a block 106 of forming a dummy gate stack 208 over the channel region 204C of the fin structure 204. In the illustrated embodiment, a replacement gate process is employed, wherein the dummy gate stack is formed as a placeholder to be subjected to a process that is detrimental to the metal gate structure, and the dummy gate stack is subsequently replaced by a functional metal gate structure. In the depicted embodiment, the dummy gate stack formed at block 106 includes the dummy gate stack 208 located over the channel region 204C of the fin structure 204. In some embodiments, the dummy gate stack 208 includes a dummy electrode layer 209 over the dummy gate dielectric layer 207. The dummy gate dielectric layer 207 is first formed on the fin structure 204 using thermal oxidation, atomic layer deposition (ALD), or chemical vapor deposition, and the dummy electrode layer 209 is formed on the dummy gate dielectric layer 207 using chemical vapor deposition. In some embodiments, the dummy gate dielectric layer 207 includes silicon oxide, and the dummy electrode layer 209 includes polysilicon.

[0064] The deposited dummy gate dielectric layer 207 and dummy electrode layer 209 are then patterned using a combination of lithography and etching processes. In some embodiments, a dual patterning or multi-patterning process may be used to pattern the dummy gate stack 208. In order to pattern the dummy gate dielectric layer 207 and the dummy electrode layer 209, a gate top hard mask layer 210 is deposited over the dummy electrode layer 209 and patterned. The gate top hard mask layer 210 may be a single layer or multiple layers and may include silicon oxide or silicon nitride. The patterned gate top hard mask layer 210 is used as an etching mask to etch the underlying dummy gate dielectric layer 207 and dummy electrode layer 209 to form the dummy gate stack 208. As Figure 4 As shown, the fin structure 204 extends longitudinally along the Y direction, while the dummy gate stack 208 extends longitudinally along the X direction.

[0065] refer to Figure 1 and Figure 5, the method 100 includes a box 108, depositing a first gate spacer layer 212 (also referred to as a first gate spacer) and a second gate spacer layer 214 (also referred to as a second gate spacer) over the substrate 202 and the dummy gate stack 208, respectively. In some embodiments shown in the figure, the first gate spacer layer 212 includes silicon oxycarbide (SiOC) or silicon oxycarbon nitride (SiCON), and can be conformally deposited along the sidewalls of the dummy gate stack 208 and the fin structure 204 by atomic layer deposition (ALD), chemical vapor deposition (CVD), or a suitable conformal deposition method. The first gate spacer layer 212 is intended to etch slower than semiconductor materials and silicon oxide, and to define and protect the gate structure during the gate replacement process. The second gate spacer layer 214 can also include silicon oxycarbon nitride (SiCON), and the second gate spacer can be conformally deposited over the first gate spacer layer 212 using ALD, CVD, or a suitable conformal deposition method. Unlike the first gate spacer layer 212, the second gate spacer layer 214 has a lower dielectric constant and provides additional distance between the gate structure to be formed and the source / drain features to be formed. Although both the first gate spacer layer 212 and the second gate spacer layer 214 can include silicon (Si), carbon (C), oxygen and nitrogen (N), they have different compositions. For example, the carbon content of the first gate spacer layer 212 is greater than the carbon content of the second gate spacer layer 214. In some embodiments, the carbon content of the first gate spacer layer 212 is at least twice that of the second gate spacer layer 214. In addition, the second gate spacer layer 214 includes more oxygen content than the first gate spacer layer 212 to reduce the dielectric constant. As will be further described below, the second gate spacer layer 214, which is more like silicon oxide, acts as an etch stop layer (ESL) during the selective removal of the dummy sidewall (DSW) layer 216.

[0066] like Figure 5 As shown, the first gate spacer layer 212 has a first thickness T1, and the second gate spacer layer 214 has a second thickness T2. In order to reduce parasitic capacitance, the second thickness T2 is greater than the first thickness T1, thereby maximizing the thickness of the second gate spacer layer 214, and the second gate spacer layer has a smaller dielectric constant than the first gate spacer layer. In some cases, the first thickness T1 can be between about 1.8 nm and about 2.4 nm, and the second thickness T2 can be between about 2.4 nm and about 3.2 nm.

[0067] refer to Figure 1 and Figure 6 to Figure 7, the method 100 includes box 110, conformally depositing a dummy sidewall layer 216 over the second gate spacer layer 214. The composition and thickness of the dummy sidewall layer 216 make it more etch-resistant than the first gate spacer layer 212 and the second gate spacer layer 214. However, unlike the first gate spacer layer 212 and the second gate spacer layer 214, a large portion of the dummy sidewall layer 216 is removed after it successfully performs its protective function. For this reason, the dummy sidewall layer 216 can also be referred to as a sacrificial dielectric layer or a filler dielectric layer. In some embodiments, the dummy sidewall layer 216 includes silicon oxynitride (SiON), and the dummy sidewall layer can be conformally deposited over the second gate spacer layer 214 using atomic layer deposition, chemical vapor deposition, or a suitable conformal deposition method. To protect the sidewalls of the dummy gate stack 208 during source / drain recessing, the dielectric constant of the dummy sidewall layer 216 is greater than the dielectric constants of the first gate spacer layer 212 and the second gate spacer layer 214, and the dummy sidewall layer has a greater thickness than the first gate spacer layer 212 and the second gate spacer layer 214. In some embodiments, the dielectric constant of the dummy sidewall layer 216 is between about 6.4 and about 7. In comparison, the dielectric constant of the first gate spacer layer 212 is between about 4.4 and about 5.1, and the dielectric constant of the second gate spacer layer 214 is between about 3.5 and about 4.4. Figure 6 As shown, the dummy sidewall layer 216 has a third thickness T3, which is greater than the first thickness T1 of the first gate spacer layer 212 or the second thickness T2 of the second gate spacer layer 214. In some cases, the third thickness T3 may be between about 3.3 nm and about 4.4 nm. In terms of etching selectivity, the dummy sidewall layer 216 remains more similar to silicon nitride, so that the method of selectively etching silicon nitride can selectively etch the dummy sidewall layer 216 without substantially damaging the second gate spacer layer 214.

[0068] Figure 7 FIG. 2 shows a top view of a portion of the workpiece 200 after conformal deposition of the dummy sidewall layer 216. The fin structure 204 extends longitudinally along the Y direction. The dummy gate stack 208 wraps around the channel region 204C of the fin structure 204 and extends longitudinally along the X direction. Figure 7 As shown, line AA' passes through the fin structure 204 along the longitudinal direction of the fin structure, line BB' passes through a portion of the dummy gate stack 208 that does not overlap with the fin structure 204, line CC' passes through the source / drain region 204SD along the X direction, and line DD' passes through the transition region between the channel region 204C and the source / drain region 204SD along the X direction. Figure 8 , Fig.10 , Fig.12 , Fig.14 , Fig.16 , Fig.18and Fig. 20 It is a cross-sectional view of the portion along line AA'. Fig. 9 , Fig.11 , Fig.13 , Fig.15 , Fig.17 , Fig.19 and Fig.21 It is a cross-sectional view of the portion along line BB'. Fig. 22 is a cross-sectional view of the portion along line CC', albeit after some subsequent processes have been performed. Fig.23 is a cross-sectional view of the portion along line DD', albeit after some subsequent processes have been performed.

[0069] refer to Figure 1 and Figures 8 to 9 , the method 100 includes a block 112 of recessing the source / drain region 204SD to form a source / drain recess 218. In some embodiments, the source / drain region 204SD is anisotropically etched using dry etching or a suitable etching process to form the source / drain recess 218. For example, the dry etching process may use oxygen (O2), oxygen-containing gas, fluorine-containing gas (e.g., CF4, SF6, CH2F2, CHF3, and / or C2F6), chlorine-containing gas (e.g., Cl2, CHCl3, CCl4, and / or BCl3), bromine-containing gas (e.g., HBr and / or CHBr3), iodine-containing gas, other suitable gases and / or plasma, and / or combinations thereof. Figure 8 As shown, after forming the source / drain recesses 218, the first gate spacer layer 212, the second gate spacer layer 214 and the dummy sidewall layer 216 may remain disposed above the channel region along the sidewalls of the dummy gate stack 208. Referring now to Fig. 9 Because the dry etching process etches the fin structure 204 faster than the dummy sidewall layer 216, the dummy sidewall layer 216 that is not directly above the fin structure 204 can remain above the top surface of the isolation feature 206. Fig. 9 As shown, the dummy sidewall layer 216 is vertically spaced apart from the isolation feature 206 by vertical portions of the first gate spacer layer 212 and the second gate spacer layer 214 .

[0070] refer to Figure 1 and Figure 10 to Figure 11The method 100 includes forming a source / drain feature 220 (also referred to as an epitaxial feature) on the source / drain region 204SD at block 114. A source / drain recess 218 is formed above the source / drain region 204SD using an epitaxial process. The epitaxy process may use a CVD deposition technique (e.g., vapor-phase epitaxy (VPE), ultra-high vacuum CVD (UHV-CVD), low pressure chemical vapor deposition (LPCVD and / or plasma enhanced CVD (PECVD), molecular beam epitaxy (MBE), other suitable selective epitaxial growth (SEG) processes, or a combination thereof. The source / drain feature 220 may be n-type or p-type. When the source / drain feature 220 is p-type, it includes silicon germanium (SiGe) and a p-type dopant, such as boron (B). When the source / drain feature 220 is n-type, it includes silicon (Si) and an n-type dopant, such as phosphorus (P). Fig.10 As shown, since the formation of the source / drain features 220 in block 114 is selective to the semiconductor surface, the semiconductor surface exposed by the source / drain features 220 from the source / drain recesses 218 becomes thicker. Fig.11 As shown, the overgrowth of the source / drain feature 220 in the lateral direction (ie, the X direction) may result in a portion of the source / drain feature 220 extending beyond the sidewall of the fin structure 204 and overhanging a portion of the dummy sidewall layer 216 . Fig. 22 Also shown are source / drain features 220 that overhang the dummy sidewall layer 216 .

[0071] refer to Figure 1 and Figure 12 to Figure 13 , method 100 includes box 116, isotropically etching back the dummy sidewall layer 216. After box 112 recesses the source / drain region 204SD and box 114 forms the source / drain feature 220, the dummy sidewall layer 216 performs its function. In order to reduce the impact of the dummy sidewall layer 216 on the parasitic capacitance, the dummy sidewall layer 216 is selectively etched. In some embodiments, etching back the dummy sidewall layer 216 includes using a hot phosphoric acid solution and a process temperature between 140°C and approximately 180°C. As described above, although the dummy sidewall layer 216 may include oxygen, its etching performance remains similar to that of silicon nitride. In these embodiments, the hot phosphoric acid solution that selectively etches silicon nitride also selectively etches the dummy sidewall layer 216 without damaging the second gate spacer layer 214, which is similar to silicon oxide. As Fig.12As shown, above the channel region 204C, the dummy sidewall layer 216 above the second gate spacer layer 214 can be completely removed at block 116. Fig.13 , the dummy sidewall layer 216 is selectively etched back until a gap 221 is formed along the Y direction between the source / drain features 220 and the second gate spacer layer 214 (along the sidewalls of the dummy gate stack 208). Figure 7 As shown along line BB′, the top surface of the dummy sidewall layer 216 is lower than the top surface of the source / drain features 220 .

[0072] refer to Figure 1 and Figure 14 to Figure 15 The method 100 includes block 118 of depositing a contact etch stop layer 222 and an interlayer dielectric (ILD) layer over the source / drain features 220. Fig.14 and Fig.15 As shown, a contact etch stop layer 222 is formed on the source / drain feature 220, and an interlayer dielectric layer 224 is formed on the contact etch stop layer 222. The interlayer dielectric layer 224 is separated from the second gate spacer layer 214, the dummy sidewall layer 216 and the source / drain feature 220 by the contact etch stop layer 222. In some embodiments, the contact etch stop layer 222 includes silicon nitride, silicon oxynitride and / or other materials known in the art. The contact etch stop layer 222 can be deposited using ALD, plasma enhanced chemical vapor deposition (PECVD) process and / or other suitable deposition process. Then the interlayer dielectric layer 224 is deposited on the contact etch stop layer 222. In some embodiments, the interlayer dielectric layer 224 includes materials such as tetraethylorthosilicate (TEOS) oxide, undoped silicate glass or doped silicon oxide such as borophosphosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), boron doped silicon glass (BSG) and / or other suitable dielectric materials. The interlayer dielectric layer 224 can be deposited by a spin-on process or other suitable deposition techniques. In some embodiments, after forming the interlayer dielectric layer 224, the workpiece 200 can be annealed to improve the integrity of the interlayer dielectric layer 224.

[0073] Still reference Fig.14 and Fig.15After depositing the interlayer dielectric layer 224, the workpiece 200 is planarized to expose the dummy gate stack 208. At the end of the planarization process, the top surfaces of the interlayer dielectric layer 224, the contact etch stop layer 222, the dummy gate stack 208, and the first gate spacer layer 212 are coplanar. Fig.15 , a portion of the contact etch stop layer 222 may be deposited into the gap 221. That is, a portion of the contact etch stop layer 222 may be located between the sidewall of the second gate spacer layer 214 and the source / drain feature 220 along the Y direction. The contact etch stop layer 222 extends downward into the gap 221 to protect the sidewall of the source / drain feature 220 during the formation of the source / drain contact opening.

[0074] refer to Figure 1 and Figure 16 to Figure 17, the method 100 includes a block 120, replacing the dummy gate stack 208 with a gate structure 240. A gate replacement operation is performed at block 120 to replace the dummy gate stack 208 (including the dummy gate dielectric layer 207 and the dummy electrode layer 209) with the gate structure 240. First, the dummy gate stack 208 (including the dummy gate dielectric layer 207 and the dummy electrode layer 209) is selectively removed to form a gate trench defined by a first gate spacer layer 212. Then, the gate structure is deposited in the gate trench. In some embodiments, the gate structure 240 may include a work function layer 234 above the gate dielectric layer 232, a cap layer 236 above the work function layer 234, and a metal fill layer 238 on the cap layer 236. In some embodiments, the gate dielectric layer 232 may include a high-k dielectric layer. The high-k dielectric layer is formed of a dielectric material having a high dielectric constant, such as a dielectric constant greater than that of silicon oxide (k≈3.9). Exemplary high-k dielectric materials include cesium, aluminum, zirconium, lanthanum, titanium, titanium, yttrium, oxygen, nitrogen, other suitable components or combinations thereof. In some embodiments, the high-k dielectric layer may include, for example, HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, ZrO2, Al2O3, HfO2-Al2O3, TiO2, Ta2O5, La2O3, Y2O3, other suitable high-k dielectric materials or combinations thereof. The work function layer 234 may be a p-type work function layer or an n-type work function layer. When the work function layer 234 is an n-type work function layer, it may include Ti, Al, Ag, Mn, Zr, TiAl, TiAlC, TaC, TaCN, TaSiN, TaAl, TaAlC, TiAlN, other n-type work function materials. When the work function layer 234 is a p-type work function layer, it may include TiN, TaN, Ru, Mo, Al, WN, ZrSi2, MoSi2, TaSi2, NiSi2, WN, other p-type work function materials or combinations thereof. The function of the cap layer 236 is to prevent oxidation of the elements in the work function layer 234. The cap layer 236 may include a metal nitride, such as titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (W2N), titanium silicon nitride (TiSiN), tantalum silicon nitride (TaSiN) or a combination thereof. The metal fill layer 238 may include a suitable conductive material, such as tungsten (W), ruthenium (Ru) or copper (Cu). The layers in the gate structure 240 may be deposited using physical vapor deposition (PVD) or ALD. After depositing the gate structure 240, the workpiece 200 is planarized, for example, using a CMP process to remove excess material. The gate structure 240 wraps around the channel region 204C, a portion of which falls on the top surface of the gate structure 240 (such as Fig.16 ), and another portion thereof extends along the sidewall of the gate structure 240 to fall on the isolation feature 206 (as shown in Fig.17Although not explicitly shown in the figure, a silicon oxide interfacial layer may be formed on the top surface and sidewalls of the channel region 204C before depositing the gate dielectric layer 232. Because the gate structure 240 includes metal and is not formed of polysilicon like the dummy gate stack 208, the gate structure 240 may also be referred to as a metal gate structure.

[0075] refer to Figure 1 and Figure 18 to Figure 19 , the method 100 includes block 122, recessing the gate structure 240. In some embodiments, Fig.18 and Fig.19 Representatively, lithography and etching processes are performed at block 122 to selectively recess gate structure 240, first gate spacer layer 212, second gate spacer layer 214, and contact etch stop layer 222, respectively. For example, a patterned etching mask may be formed over workpiece 200 to cover interlayer dielectric layer 224 while exposing all structures between two adjacent patches of interlayer dielectric layer 224. Recessing may be performed at block 122 using dry etching, wet cleaning, or a combination thereof. An example dry etching process may include fluorocarbons (e.g., CF4, SF6, NF3, CH2F2, CHF3, and / or C2F6), chlorine-containing gases (e.g., Cl2, CHCl3, CCl4, and / or BCl3), oxygen (O2), hydrogen (H2), argon (Ar), or a combination thereof. An example wet cleaning process may include the use of ammonium hydroxide (NH4OH), hydrogen peroxide (H2O2), hot deionized water (DIW), isopropyl alcohol (IPA) or ozone (O3). The recess in block 122 may form a gate top recess 242. The gate top recess 242 is defined between two adjacent blocks of the interlayer dielectric layer 224 along the Y direction, and the bottom surface of the gate top recess 242 is defined by the contact etch stop layer 222, the first gate spacer layer 212, the second gate spacer layer 214 and the top surface of the gate structure 240.

[0076] refer to Figure 1 and Figure 20 to Figure 21, the method 100 includes a block 124, selectively depositing a metal capping layer 244 over the gate structure 240. In some embodiments, the metal capping layer 244 may include a metal that is more conductive than the capping layer 236 and the work function layer 234. In some embodiments, the metal capping layer 244 may include tungsten (W), cobalt (Co), nickel (Ni), molybdenum (Mo), or ruthenium (Ru). The metal capping layer 244 may be selectively deposited on a conductive surface using ALD, plasma-enhanced ALD (PEALD), metalorganic CVD (MOCVD), or a suitable deposition process. In one embodiment, the metal capping layer 244 may include tungsten (W). The formation of the metal capping layer 244 reduces the gate contact resistance.

[0077] refer to Figure 1 and Figure 20 to Figure 21 , the method 100 includes box 126, forming a self-aligned dielectric capping layer 246 above the metal capping layer 244. After depositing the metal capping layer 244, the dielectric capping layer 246 is deposited all over the workpiece 200. The dielectric capping layer 246 may include silicon oxide, silicon nitride, silicon carbonitride, silicon oxycarbon nitride, aluminum oxide, zirconium silicate (ZrSiO), helium silicate (HfSiO), helium oxide, or zirconium oxide, and the dielectric capping layer may be deposited using CVD or ALD. In one embodiment, the dielectric capping layer 246 includes silicon nitride. The dielectric capping layer 246 may also be referred to as a self-aligned contact (SAC) dielectric layer. After depositing the dielectric capping layer 246, the workpiece 200 is planarized, for example using a chemical mechanical polishing process, to provide a dielectric layer such as a SAC. Fig. 20 and Fig.21 Flat top surface shown.

[0078] At block 116, the unremoved dummy sidewall layer 216 plays an important role in reducing parasitic capacitance. Fig.21 , the portion of the gate structure 240 that is not directly above the channel region 204C is separated from the source / drain feature 220 by the remaining portion 2160 of the dummy sidewall layer 216. The parasitic capacitance between the gate structure 240 and one of the source / drain features 220 can be modeled as a parallel plate capacitor. The remaining portion 2160 of the dummy sidewall layer 216 is directly disposed between the gate structure 240 and the source / drain feature 220 and directly affects the effective capacitance of such a modeled parallel plate capacitor. The performance of the semiconductor element can be evaluated using a ring oscillator (RO). According to experiments and computer simulations, the RO performance of the semiconductor structure (workpiece 200) can be improved by about 0.7% to about 2.2% by reducing the dielectric constant of the dummy sidewall layer 216 by about 10%.

[0079] Fig. 22 Shows Fig.21 FIG. 2 is a cross-sectional view of a portion of FIG. 2 along line CC'. Line CC' passes through one of the source / drain features 220. Fig. 22 As shown, the multi-faceted growth of the source / drain feature 220 extends not only in the Z direction but also in the X direction. Therefore, a portion of the source / drain feature 220 extends beyond the sidewall of the fin structure 204 and overhangs the isolation feature 206. The contact etch stop layer 222 extends substantially conformally along the surface of the source / drain feature 220, and the interlayer dielectric layer 224 fills the space and void left by the contact etch stop layer 222. A portion of the dummy sidewall layer 216 is vertically separated from the top surface of the isolation feature 206 by the first gate spacer layer 212 and the second gate spacer layer 214.

[0080] Fig.23 Shows Fig.21 The cross-sectional view of the portion along the line D-D' in FIG. The line D-D' passes through the remaining dummy sidewall layer 216 extending along the sidewall of the gate structure 240 between the source / drain features 220 and the second gate spacer layer 214. Fig.23 As shown, the lateral overgrowth of the source / drain feature 220 is separated from the gate structure 240 (outside the line and indicated by dashed lines) along the Y direction by the contact etch stop layer 222 and the remaining portion 2160 of the dummy sidewall layer 216. Although the contact etch stop layer 222 also contributes to the parasitic capacitance between the gate structure 240 and the source / drain feature 220, its dielectric constant may not be reduced as much as the dummy sidewall layer 216 without other arrangements. For example, when the contact etch stop layer 222 has a smaller dielectric constant, the formation of the source / drain contact opening may laterally destroy the contact etch stop layer 222 and cause an electrical short.

[0081] Therefore, in one embodiment, a semiconductor structure is provided. The semiconductor structure includes a fin structure formed from a substrate and extending longitudinally in one direction, an isolation feature disposed above the substrate and around the fin structure, a gate structure wrapping a channel region of the fin structure and disposed above the isolation feature, a first gate spacer extending along the sidewall of the gate structure and the top surface of the isolation feature, a second gate spacer disposed above the first gate spacer, a filling dielectric layer disposed above the second gate spacer, an epitaxial feature disposed above the source / drain region of the fin structure, a contact etch stop layer disposed above the epitaxial feature and the filling dielectric layer, and an interlayer dielectric layer disposed above the contact etch stop layer. A portion of the epitaxial feature is disposed above the filling dielectric layer. A portion of the contact etch stop layer extends between the epitaxial feature and the sidewall of the gate structure along the direction.

[0082] In some embodiments, a portion of the filler dielectric layer is disposed between the epitaxial feature and the sidewall of the gate structure along the direction. In some embodiments, the composition of the first gate spacer is different from the composition of the second gate spacer or the composition of the filler dielectric layer, and the composition of the second gate spacer is different from the composition of the filler dielectric layer. In some embodiments, the dielectric constant of the filler dielectric layer is greater than the dielectric constant of the first gate spacer, and the dielectric constant of the first gate spacer is greater than the dielectric constant of the second gate spacer. In some embodiments, the first gate spacer includes silicon oxycarbon nitride or silicon carbide. The filler dielectric layer includes silicon oxynitride. The second gate spacer includes silicon oxide or silicon carbide. The oxygen content of the second gate spacer is greater than the oxygen content of the first gate spacer. In some instances, the top surface of the epitaxial feature is higher than the top surface of the filler dielectric layer. In some instances, the top surface of the first gate spacer and the second gate spacer is higher than the top surface of the filler dielectric layer. In some embodiments, the first gate spacer has a first thickness, the second gate spacer has a second thickness, and the filler dielectric layer has a third thickness greater than the first thickness or the second thickness.

[0083] In another embodiment, a semiconductor structure is provided. The semiconductor structure includes a substrate, a fin structure formed from the substrate and extending longitudinally in one direction, an isolation feature disposed above the substrate and around the fin structure, a gate structure that wraps the channel region of the fin structure and is disposed on the isolation feature, a first gate spacer extending along the sidewall of the gate structure and the top surface of the isolation feature, and an epitaxial feature disposed above the source / drain region of the fin structure. The epitaxial feature includes a first portion and a second portion overhanging the isolation feature. The first portion and the second portion are separated from the gate structure along the direction by a filler dielectric layer and a contact etch stop layer. The contact etch stop layer is disposed above the filler dielectric layer. The filler dielectric layer includes silicon oxynitride and has a dielectric constant between about 5 and about 6.4, and the contact etch stop layer includes silicon nitride and has a dielectric constant between about 6.4 and about 7.

[0084] In some embodiments, the filler dielectric layer is separated from the sidewalls and isolation features of the source / drain region of the fin structure by the first gate spacer and the second gate spacer. In some embodiments, the thickness of the filler dielectric layer is greater than the thickness of the first gate spacer or the thickness of the second gate spacer. In some embodiments, the dielectric constant of the filler dielectric layer is less than the dielectric constant of the contact etch stop layer. In some embodiments, the filler dielectric layer includes silicon oxynitride and the contact etch stop layer includes silicon nitride.

[0085] In yet another embodiment, a method for forming a semiconductor structure is provided. The method includes: forming a fin structure on a substrate, the fin structure including a channel region and a source / drain region adjacent to the channel region. Forming an isolation feature above the substrate and around the fin structure. Forming a dummy gate stack above the channel region of the fin structure. Depositing a first gate spacer layer and a second gate spacer layer on the substrate, including above the dummy gate stack and the fin structure. Depositing a filler dielectric layer on the second gate spacer layer. After depositing the filler dielectric layer, anisotropically etching the fin structure to form a source / drain recess above the source / drain region, epitaxially growing a source / drain feature on the source / drain recess. Isotropically etching the filler dielectric layer. After isotropically etching, depositing a contact etch stop layer over the source / drain feature and the filler dielectric layer.

[0086] In some embodiments, the isotropic etching includes forming a groove extending along the sidewall of the dummy gate stack between the source / drain features and the second gate spacer layer. In some embodiments, depositing the contact etch stop layer includes depositing the contact etch stop layer in the groove. In some embodiments, depositing the filler dielectric layer includes conformally depositing the filler dielectric layer on the second gate spacer layer. In some cases, the isotropic etching includes using a phosphoric acid solution at a temperature between about 140°C and about 180°C. In some embodiments, the first gate spacer layer includes silicon oxycarbon nitride or silicon oxycarbide, and the second gate spacer layer includes silicon oxide or silicon carbide. In some embodiments, the filler dielectric layer includes silicon oxynitride.

[0087] In another embodiment, a semiconductor structure is provided. The semiconductor structure includes a fin structure formed from a substrate and extending longitudinally in a direction, an isolation feature disposed above the substrate and around the fin structure, a gate structure wrapping a channel region of the fin structure and disposed on the isolation feature, a first gate spacer extending along a sidewall of the gate structure and a top surface of the isolation feature, a second gate spacer disposed above the first gate spacer, a filling dielectric layer disposed above the second gate spacer, an epitaxial feature disposed above a source / drain region of the fin structure, a contact etch stop layer disposed above the epitaxial feature and the filling dielectric layer, and an interlayer dielectric layer disposed above the contact etch stop layer. The top surface of the second gate spacer is higher than the top surface of the filling dielectric layer, and a portion of the epitaxial feature is disposed above the filling dielectric layer.

[0088] In some embodiments, the filler dielectric layer is separated from the sidewalls and isolation features of the source / drain region of the fin structure by the first gate spacer and the second gate spacer. In some embodiments, the thickness of the filler dielectric layer is greater than the thickness of the first gate spacer. In some embodiments, the thickness of the filler dielectric layer is greater than the thickness of the second gate spacer.

[0089] In yet another embodiment, a semiconductor structure is provided. The semiconductor structure includes a fin structure formed from a substrate and extending longitudinally in a direction, an isolation feature disposed above the substrate and around the fin structure, a gate structure wrapping a channel region of the fin structure and disposed on the isolation feature, a first gate spacer extending along a sidewall of the gate structure and a top surface of the isolation feature, a second gate spacer disposed above the first gate spacer, a filling dielectric layer disposed above the second gate spacer, an epitaxial feature disposed above a source / drain region of the fin structure, a contact etch stop layer disposed above the epitaxial feature and the filling dielectric layer, and an interlayer dielectric layer disposed above the contact etch stop layer. The epitaxial feature includes a first portion and a second portion overhanging the isolation feature, and the first portion and the second portion are separated from the gate structure by the filling dielectric layer and the contact etch stop layer in a direction.

[0090] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art will appreciate that they can easily use the present disclosure as a basis for designing or modifying other processes and structures to perform the same purposes and / or achieve the same advantages of the embodiments described herein. Those skilled in the art will also appreciate that such equivalent structures do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions, and modifications herein without departing from the spirit and scope of the present disclosure.

Claims

1. A semiconductor structure, characterized in that: include: a fin structure formed from a substrate and extending longitudinally in a direction; an isolation feature disposed above the substrate and around the fin structure; a gate structure wrapping a channel region of the fin structure and disposed on the isolation feature; a first gate spacer extending along a sidewall of the gate structure and a top surface of the isolation feature; a second gate spacer disposed above the first gate spacer; a filler dielectric layer disposed above the second gate spacer; an epitaxial feature disposed over a source / drain region of the fin structure, wherein a portion of the epitaxial feature is disposed over the filler dielectric layer; a contact etch stop layer disposed over the epitaxial feature and the filler dielectric layer; as well as an interlayer dielectric layer disposed above the contact etch stop layer, A portion of the contact etching stop layer extends along the direction between the epitaxial feature and a sidewall of the gate structure.

2. The semiconductor structure according to claim 1, wherein: A portion of the filling dielectric layer is disposed along the direction between the epitaxial feature and the sidewall of the gate structure.

3. The semiconductor structure according to claim 1, wherein: The thickness of the filling dielectric layer is greater than the thickness of the first gate spacer.

4. The semiconductor structure according to claim 1, wherein: The thickness of the filling dielectric layer is greater than the thickness of the second gate spacer.

5. The semiconductor structure according to claim 1, wherein: A top surface of the epitaxial feature is higher than a top surface of the filling dielectric layer.

6. A semiconductor structure, characterized in that: include: a fin structure formed from a substrate and extending longitudinally in a direction; an isolation feature disposed above the substrate and around the fin structure; a gate structure wrapping a channel region of the fin structure and disposed on the isolation feature; a first gate spacer extending along a sidewall of the gate structure and a top surface of the isolation feature; a second gate spacer disposed above the first gate spacer; a filler dielectric layer disposed above the second gate spacer, wherein a top surface of the second gate spacer is higher than a top surface of the filler dielectric layer; an epitaxial feature disposed over a source / drain region of the fin structure, wherein a portion of the epitaxial feature is disposed over the filler dielectric layer; a contact etch stop layer disposed over the epitaxial feature and the filler dielectric layer; as well as An interlayer dielectric layer is disposed above the contact etch stop layer.

7. The semiconductor structure according to claim 6, wherein: The filling dielectric layer is separated from the sidewalls of the source / drain region of the fin structure and the isolation feature by the first gate spacer and the second gate spacer.

8. The semiconductor structure according to claim 6, wherein: The thickness of the filling dielectric layer is greater than the thickness of the first gate spacer.

9. The semiconductor structure according to claim 6, wherein: The thickness of the filling dielectric layer is greater than the thickness of the second gate spacer.

10. A semiconductor structure, characterized in that: include: a fin structure formed from a substrate and extending longitudinally in a direction; an isolation feature disposed above the substrate and around the fin structure; a gate structure wrapping a channel region of the fin structure and disposed on the isolation feature; a first gate spacer extending along a sidewall of the gate structure and a top surface of the isolation feature; a second gate spacer disposed above the first gate spacer; a filler dielectric layer disposed above the second gate spacer; an epitaxial feature disposed above a source / drain region of the fin structure; a contact etch stop layer disposed over the epitaxial feature and the filler dielectric layer, wherein the epitaxial feature includes a first portion and a second portion overhanging the isolation feature, the first portion and the second portion being separated from the gate structure by the filler dielectric layer and the contact etch stop layer along the direction; as well as An interlayer dielectric layer is disposed above the contact etch stop layer.

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