A root mean square detector and electronic device

Abstract

The present application provides a root mean square detector and an electronic device, wherein the root mean square detector comprises a squaring module, which outputs a first signal and a second signal; a plurality of current mirror units, each of which outputs a third signal and a fourth signal based on the first signal and the second signal; different third signals belong to different power ranges, and different fourth signals belong to different power ranges; a plurality of limiting amplifiers, each of which receives and performs subtraction and limiting processing on the third signal and the fourth signal, and outputs a fifth signal; a plurality of logarithmic amplifiers, each of which receives and performs logarithmic conversion on the fifth signal to generate a sixth signal, the output ends of all the logarithmic amplifiers are connected together, and all the sixth signals are superimposed to generate a target output signal, so that the design difficulty of the logarithmic amplifier can be reduced through segmented output, and the correctness of the result of the root mean square detector can be improved.

Description

Technical Field

[0001] The present application relates to the field of integrated circuits, and in particular to a root mean square detector and an electronic device. Background Art

[0002] Detectors are usually used to measure the amplitude or power of a signal and are widely used in wireless systems. They can be simply divided into two categories: logarithmic amplifier detectors (or envelope detectors) and root mean square (RMS) detectors. For the root mean square detector, it is necessary to perform three operations on the signal: root (Root)-average (Mean)-square (Square). Since the absolute value of the input signal may be relatively small, the absolute value and dynamic range of the output signal change very little, which is not conducive to post-stage detection; therefore, the RMS detector will also process the output signal into a logarithmic value before outputting it. At present, since the post-stage logarithmic amplifier needs to have a good logarithmic conversion function for the output signal of the full dynamic range, the design of the logarithmic amplifier is difficult, and the accuracy of the output signal after logarithmic conversion cannot be guaranteed. Utility Model Content

[0003] The present application provides a root mean square detector and an electronic device.

[0004] The technical solution of this application is implemented as follows:

[0005] In a first aspect, an embodiment of the present application provides a root mean square detector, comprising:

[0006] A squaring module; configured to receive a bias voltage and an AC signal, square the bias voltage and the AC signal as a whole to output a first signal, and square the bias voltage to output a second signal;

[0007] A plurality of current mirror units; each of the current mirror units is connected to the square module, and is configured to receive and copy the first signal and the second signal respectively, and output a third signal and a fourth signal; different third signals belong to different power ranges, and different fourth signals belong to different power ranges;

[0008] A plurality of limiting amplifiers; each of the limiting amplifiers is connected to the corresponding current mirror unit, and is configured to receive and perform subtraction and limiting processing on the third signal and the fourth signal, and output a fifth signal; wherein different limiting amplifiers have different limiting thresholds;

[0009] Multiple logarithmic amplifiers; each of the logarithmic amplifiers is connected to the corresponding limiting amplifier and is configured to receive and perform logarithmic conversion on the fifth signal to generate a sixth signal; wherein the output ends of all the logarithmic amplifiers are connected together, and all the sixth signals are superimposed to generate a target output signal.

[0010] In a second aspect, an embodiment of the present application provides an electronic device, which includes the root mean square detector as described in the first aspect.

[0011] The embodiment of the present application provides a root mean square detector and an electronic device, which introduces multiple current mirror units, multiple limiting amplifiers and multiple logarithmic amplifiers; the multiple current mirror units are used to copy the first signal into multiple third signals, and copy the second signal into multiple fourth signals; at the same time, because the copy ratios of different current mirror units are different, different third signals belong to different power ranges, and different fourth signals belong to different power ranges. For each group of third signals and fourth signals, a limiting amplifier is used to perform subtraction and limiting processing on them to obtain multiple fifth signals, so that different fifth signals belong to different power ranges. In this way, segmented output is achieved through multiple current mirror units, and each logarithmic amplifier only needs to perform logarithmic conversion processing on the fifth signal in a small power range, which reduces the dynamic range of the input signal of each logarithmic amplifier, significantly reduces the design difficulty of the logarithmic amplifier, and improves the accuracy of the output signal; at the same time, different limiting amplifiers are independent of each other and do not need to be cascaded, and their respective mismatches will not be superimposed and affect each other, which also reduces the mismatch requirements for the limiting amplifiers; the output ends of all the logarithmic amplifiers are connected together, all the sixth signals are superimposed to generate a target output signal, and multiple outputs are combined together to easily form a complete logarithmic curve, which is conducive to achieving a high dynamic range of the root mean square detector. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 It is a schematic diagram of the results of an envelope detector and an RMS detector;

[0013] Figure 2 It is a structural schematic diagram of an RMS detector;

[0014] Figure 3 It is a structural diagram of another RMS detector;

[0015] Figure 4 It is a structural schematic diagram of another mirror square unit;

[0016] Figure 5 It is a structural schematic diagram of another square unit;

[0017] Figure 6A schematic diagram of the structure of a root mean square detector provided in an embodiment of the present application Figure 1 ;

[0018] Figure 7 A schematic diagram of the working curves of the limiting amplifier and the logarithmic amplifier provided in the embodiment of the present application;

[0019] Figure 8 A schematic diagram of the structure of a root mean square detector provided in an embodiment of the present application Figure 2 ;

[0020] Fig. 9 A schematic diagram of the structure of a root mean square detector provided in an embodiment of the present application Figure 3

[0021] Fig.10 A schematic diagram of the structure of a root mean square detector provided in an embodiment of the present application Figure 4 ;

[0022] Fig.11 A schematic diagram of the structure of a root mean square detector provided in an embodiment of the present application Figure 5 ;

[0023] Fig.12 A schematic diagram of the structure of a current mirror provided in an embodiment of the present application;

[0024] Fig.13 Schematic diagram of the structure of the root mean square detector provided in the embodiment of the present application Figure 6 . DETAILED DESCRIPTION

[0025] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. It is understood that the specific embodiments described herein are only used to explain the relevant application, not to limit the application. It should also be noted that, for the convenience of description, only the parts related to the relevant application are shown in the drawings. Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those generally understood by technicians in the technical field of the present application. The terms used herein are only for the purpose of describing the embodiments of the present application and are not intended to limit the present application. In the following description, "some embodiments" are involved, which describe a subset of all possible embodiments, but it is understood that "some embodiments" can be the same subset or different subsets of all possible embodiments, and can be combined with each other without conflict. It should be pointed out that the terms "first\second\third" involved in the embodiments of the present application are only used to distinguish similar objects, and do not represent a specific order for the objects. It is understandable that "first\second\third" can be interchanged with a specific order or sequence where permitted, so that the embodiments of the present application described here can be implemented in an order other than that shown or described.

[0026] MOS (Metal-Oxide-Semiconductor Field-Effect Transistor): Metal-Oxide Semiconductor Field-Effect Transistor;

[0027] NMOS: N-type doped metal-oxide semiconductor field effect transistor;

[0028] PMOS: P-type doped metal-oxide semiconductor field effect transistor;

[0029] CMOS (Complementary Metal Oxide Semiconductor): Complementary Metal Oxide Semiconductor;

[0030] BJT (Bipolar Junction Transistor): Bipolar junction transistor;

[0031] DC (Direct Current): direct current;

[0032] LDO (Low Dropout Regulaor): low dropout linear regulator;

[0033] dB(decibel): decibel;

[0034] dBm (decibel relative to one milliwatt): decibel milliwatt;

[0035] nA (Nanoampere): nanoampere;

[0036] mA (milliampere): milliampere;

[0037] uV (microvolt): microvolt;

[0038] mV (millivolt): millivolt;

[0039] Ω(ohm): Ohm;

[0040] kΩ: kiloohm;

[0041] Dynamic range: The ratio between the maximum and minimum amplitudes of the input signal during logarithmic conversion.

[0042] Detectors can be divided into envelope detectors and RMS detectors, see Figure 1 , which shows the detection results of the envelope detector and the RMS detector for the same RF signal. Figure 1As shown, the RF signal is a high-frequency sine wave whose amplitude / phase changes with time. The envelope detector will detect the envelope output of the input signal, usually its logarithmic value, that is, the output result 1 in the figure; the RMS detector will detect the root mean square value (or power value) of the input signal and output it, that is, the output result 2 in the figure, and its output voltage does not change with the shape or peak-to-average ratio of the signal. The peak-to-average ratio refers to the peak-to-average power ratio (PAPR), such as Figure 1 As shown, for the signal value of the RF input signal, the amplitude of the high-frequency sinusoidal wave oscillation is not fixed, and the ratio of the power corresponding to the peak value to the power corresponding to the average value is the peak-to-average ratio.

[0043] See also Figure 2 , which shows a structure of an RMS detector. Figure 2 As shown, the RMS detector includes a square unit, a mirror square unit, an operation module, an average capacitor, a logarithmic converter and a driver. The square unit and the mirror square unit have the same structure. The square unit receives a mixed signal formed by a bias voltage DC Bias (used to drive the square unit to work) and an RF input signal RFInput. The mirror square unit receives a bias voltage DC Bias or a bias voltage DC Bias+feedback voltage Feedback. The feedback voltage Feedback can be generated by the operation module or the driver. The output signals of the square unit and the mirror square unit are subtracted after passing through the operation module, and then averaged by the average capacitor, and logarithm conversion is performed by the logarithmic converter, thereby outputting a detection result signal, which is equivalent to Figure 1 The logarithmic form of the RMS value (or power value) output. See Figure 3 , the location of the average capacitor can also be placed at the output end of the square unit.

[0044] Combination Figure 2 or Figure 3 For the RMS detector, its working process includes performing three operations on the signal: Root-Mean-Square, that is, the output voltage or current is:

[0045]

[0046] Where Y is the output current or voltage, X is the input current or voltage, and s is the slope.

[0047] Since the absolute value of the input signal X may be relatively small, usually in dBm units, for the above formula (1), the absolute value of the output signal Y is also small. For example, when the input power changes from -40dBm to -20dBm, when s=1, the voltage corresponding to Y only changes from 2.24mV to 22.4mV, and the absolute value and dynamic range are extremely small, which is not conducive to post-stage detection. Therefore, the RMS detector usually processes the result Y into a logarithmic value before outputting it:

[0048]

[0049] Where Z is the actual output current or voltage of the RMS detector, k is the logarithmic slope, b is the logarithmic intercept, k' is the logarithmic slope after the combined square root operation, and b' is the logarithmic intercept after the combined linear slope s. The logarithm in the formula can also be other bases as long as there is a logarithmic relationship.

[0050] When the subsequent stage adds the logarithmic conversion function, the square root operation in the RMS detector can be directly removed from the logarithm and become part of the slope, without the need for hardware implementation. The slope s in the previous article will be added to the logarithmic intercept here to form a new logarithmic intercept, which will no longer affect the slope of the output signal Z. The following descriptions are all based on this.

[0051] At the same time, for the RMS detector, the definition of dBm is as shown in equation (3):

[0052]

[0053] The definition of current dB is shown in formula (4):

[0054] dB(I)=20log(I)……………………(4)

[0055] Due to the characteristics of the square unit itself, the output current is proportional to the square of the input voltage, as shown in formula (5):

[0056]

[0057] If the intercept b1 is ignored, then

[0058] dB(I SQ )=2dBm(V rms )=2[10log(I SQ )+b2]+b3=20log(I SQ )+b4…………(6)

[0059] That is, when the input of the RMS detector V rms The dynamic range is 60dBm, the square unit output current I SQIt will reach 120dB, which requires an extremely high dynamic range for the subsequent logarithmic-to-linear circuit, making the design more difficult.

[0060] At present, since the post-stage logarithmic amplifier needs to have a good logarithmic conversion function for the output signal of the full dynamic range, the design of the logarithmic amplifier is difficult, and the accuracy of the output signal after logarithm conversion cannot be guaranteed; in one solution, a cascaded differential amplifier chain can be added to provide output signals of different power ranges, and then each logarithmic amplifier only performs logarithmic conversion on the output signal of the corresponding range, but the mismatch of each differential amplifier in the cascaded differential amplifier chain will accumulate and affect each other, so that the mismatch requirements of the differential amplifier are very high, and the accuracy of the result cannot be guaranteed.

[0061] In addition to the above issues, see Figure 4 , which shows a square circuit based on a triode. Figure 4 As shown, the square circuit includes: four transistors Q1, Q2, Q3 and Q4, and four resistors R connected to the four transistors respectively. E , capacitor C L , resistor R L1 and resistor R L2 , where: The base of transistors Q3 and Q4 receives bias voltage V CM (i.e. the aforementioned bias voltage DCBias), the bases of transistors Q1 and Q2 receive the bias voltage V CM (Squaring circuit has no input, see Figure 4 ) or input signal (the square circuit has input, see Figure 5 ), where the input signals are differential inputs, respectively and (Wherein, V CM is the bias voltage, and are the negative phase signal and positive phase signal of the AC signal RF Input respectively), capacitor C L One end of the resistor R L1 One end of the transistor Q1, the collector of the transistor Q2 are connected as the positive phase output end of the square circuit, and the positive phase output voltage V OUT+ ; Among them, I OUT is the positive phase output current, the resistor R L1 Convert it into a positive output voltage V OUT+ . Resistance R L2 One end of the transistor Q3, the collector of the transistor Q4 are connected as the inverting output end of the square circuit, and the inverted output voltage V is output. OUT-The square current obtained is based on the two transistors being in a completely consistent state. However, in reality, due to process deviations and other reasons, the two transistors Q1 / Q2 and Q3 / Q4 cannot be completely consistent, and there must be a certain mismatch.

[0062] like Figure 4 As shown, when there is no input to the square circuit, the bases of the four transistors all receive the bias voltage V CM , the output current of the square unit formed by transistors Q1 and Q2 is I B +I OS , the output current of the mirror square unit formed by transistors Q3 and Q4 is I B , there is already an I between the two currents in the square circuit OS As an example, the offset circuit is equivalent to the positive output terminal. Figure 5 As shown, when the square circuit has an input, the output current of the square unit formed by transistors Q1 and Q2 is I B +I SQ +I OS , the output current of the mirror square unit formed by transistors Q3 and Q4 is I B The difference between the two currents contains not only the useful square current I SQ , also includes the offset current I OS Because of the existence of offset current, the sensitivity of the square circuit will be limited. For example, if the offset current is equivalent to the input offset voltage, this value will usually reach several millivolts (mV) or even tens of mV. For signals with amplitudes less than 10mV or at the level of 10mV, the square current value obtained will be very inaccurate. B is the inverting output current, is the quiescent current, and the resistor R L2 Convert it into an inverting output voltage V OUT- According to the three-stage tube formula, I OUT with I B Subtracting the input voltage signal, we can get the current I which is in square relationship with the input voltage signal. SQ .

[0063] From the above, it can be seen that since the square unit and the mirror square unit include transistors, due to process deviations of the transistors, the difference between the output currents of the square unit and the mirror square unit after subtracting them not only includes the square current I SQ , and the offset current I OS . Because the offset current I OS The presence of , the sensitivity of the square circuit will be limited. In addition, the offset current I OS It will also change with temperature, and the changing offset current cannot be well suppressed. Therefore, even at a single temperature point, the offset current Ios Even without calibration, the accuracy of detection after temperature changes cannot be guaranteed.

[0064] The embodiments of the present application will be described in detail below with reference to the accompanying drawings.

[0065] In one embodiment of the present application, see Figure 6 , which is a schematic diagram of the structure of the RMS detector 10 provided in an embodiment of the present application.

[0066] like Figure 6 As shown, the RMS detector 10 includes a square module 11; configured to receive a bias voltage DC Bias and an AC signal RF Input, square the bias voltage DC Bias and the AC signal RF Input as a whole to output a first signal I1, and square the bias voltage to output a second signal I2. Here, the first signal at least includes the aforementioned quiescent current I B and square current I SQ , the second signal is the static current I B (i.e., a DC signal), and at the same time, the first signal or the second signal may also include a mismatch current I OS .

[0067] Specifically, see Figure 6 The square module 11 includes a square unit 111 and a mirror square unit 112. The square unit 111 receives a bias voltage DC Bias and an AC signal RF Input and outputs a first signal. The mirror square unit 112 is used to receive the bias voltage DC Bias and output a second signal. The structure of the mirror square unit 112 is consistent with that of the square unit 111. Exemplarily, the structure of the square unit 111 may include Figure 4 As shown in FIG. 1 and FIG. 2 , the structure of the mirror square unit 112 may include Figure 4 Transistors Q3 and Q4 are shown.

[0068] See also Figure 6 The RMS detector 10 further includes a plurality of current mirror units 121, 122, ..., 12N; each current mirror unit is connected to the square module 11, and is configured to receive and respectively copy the first signal I1 and the second signal I2, and output a third signal and a fourth signal, that is, the current mirror unit 121 copies the first signal I1 and the second signal I2 to generate a third signal I31 and a fourth signal I41, the current mirror unit 122 copies the first signal I1 and the second signal I2 to generate a third signal I32 and a fourth signal I42... The current mirror unit 12N copies the first signal I1 and the second signal I2 to generate a third signal I3N and a fourth signal I4N, and the value of N is a positive integer.

[0069] It should be noted that different third signals belong to different power ranges, different fourth signals belong to different power ranges, and the power ranges to which the third signal and the fourth signal output by the same current mirror unit belong are the same, so as to segment the outputs of different current mirror units. In other words, the power ranges of the third signal I31 and the fourth signal I41 are the same, the power ranges of the third signal I32 and the fourth signal I42 are the same... the power ranges of the third signal I3N and the fourth signal I4N are the same, but the power ranges of the third signal I31, the third signal I32... the third signal I3N are different, and the power ranges of the fourth signal I41, the fourth signal I42... the fourth signal I4N are different. The specific power range to which each signal belongs can be selected according to the actual application scenario.

[0070] In an optional embodiment, in order to reasonably design the output power range of each current mirror unit, the output power ranges of multiple current mirror units can be connected end to end, that is, the power ranges of multiple current mirror units are spliced ​​to form a continuous target power range. In some embodiments, the output power ranges of multiple current mirror units do not overlap with each other, which can avoid power waste. For example, the power range of the third signal I31 and the fourth signal I41 is 0dBm~30dBm, the power range of the third signal I32 and the fourth signal I42 is 30dBm~60dBm, the power range of the third signal I33 and the fourth signal I43 is 60dBm~90dBm, the power range of the third signal I34 and the fourth signal I44 is 90dBm~120dBm... At the same time, in the above examples, the power range corresponding to each current mirror unit is the same, but this does not constitute a specific limitation.

[0071] See also Figure 6, the RMS detector 10 also includes a plurality of limiting amplifiers 131, 132...13N; each limiting amplifier is connected to a corresponding current mirror unit; each limiting amplifier is configured to receive and perform subtraction and limiting processing on the third signal and the fourth signal, and output a fifth signal; wherein different limiting amplifiers have different voltage limiting thresholds (or current limiting thresholds). Here, when the voltage (or current) of the input signal is lower than the voltage limiting threshold (or current limiting threshold), the limiting amplifier linearly amplifies the input signal and outputs the fifth signal; when the voltage (or current) of the input signal is higher than the voltage limiting threshold (or current limiting threshold), the limiting amplifier outputs the fifth signal with an upper limit value of power, that is, the fifth signal no longer presents a linear relationship with the power of the input signal, thereby achieving a limiting effect. Specifically, the limiting amplifier 131 receives the third signal I31 and the fourth signal I41 and outputs the fifth signal I51, the limiting amplifier 132 receives the third signal I32 and the fourth signal I42 and outputs the fifth signal I52, ... the limiting amplifier 13N receives the third signal I3N and the fourth signal I4N and outputs the fifth signal I5N. In this way, the limiting amplifier has two functions: (1) a subtractor function, that is, performing a subtraction operation on the two input signals, similar to Figure 2 and Figure 3 (2) a limiting function for limiting the output signal. Thus, the power ranges of different fifth signals are also different, and can be more accurately located in the corresponding power range.

[0072] See also Figure 6 , the RMS detector 10 also includes a plurality of logarithmic amplifiers 141, 142, ... 14N; each logarithmic amplifier is connected to a corresponding limiting amplifier, and is configured to receive and perform logarithmic conversion on the fifth signal to generate a sixth signal. Because the voltage limiting threshold of the limiting amplifier corresponding to each logarithmic amplifier is different, the power ranges (specifically, voltage ranges or current ranges) of different sixth signals are different. For example, the power range of the sixth signal I61 is -90dBm to -60dBm, the power range of the sixth signal I62 is -60dBm to -30dBm, and the power range of the sixth signal I63 is -30dBm to 0dBm ... wherein the output ends of all logarithmic amplifiers are connected together to superimpose all sixth signals to generate a target output signal. That is, the logarithmic amplifier 141 receives the fifth signal I51 and outputs the sixth signal I61, the logarithmic amplifier 142 receives the fifth signal I52 and outputs the sixth signal I62... The logarithmic amplifier 14N receives the fifth signal I5N and outputs the sixth signal I6N, and the sixth signal I61, the sixth signal I62... The sixth signal I6N are superimposed (or called splicing) to form the target output signal Iout.

[0073] It is also necessary to note that see Figure 7 In a, the limiting amplifier 131 is used as an example to illustrate the working curve of the limiting amplifier. For the limiting amplifier, it behaves as a linear amplifier within the limiting amplitude range (i.e., the input voltage is lower than the voltage limiting threshold, or the input current is lower than the current limiting threshold). When the output reaches the designed limiting amplitude, the output will remain unchanged, that is, the dynamic range is limited. Therefore, if (the fourth signal I41-the third signal I31) is within 0~Limit1, the fifth signal I51 changes linearly with (the fourth signal I41-the third signal I31); if (the fourth signal I41-the third signal I31)>Limit1, the fifth signal I51 keeps the upper limit value unchanged.

[0074] See also Figure 7 (b) in FIG. 1 shows a schematic diagram of the working curve of the logarithmic amplifier, taking the logarithmic amplifier 141 as an example. The dynamic range of the logarithmic amplifier usually has a lower limit. When the input is less than the lower limit, the logarithmic amplifier outputs the minimum value; when the input is greater than the lower limit and is within the linear working range, the logarithmic amplifier converts the input into a logarithmic form output; when the input is greater than the linear working range, the output may still increase with the input, but it is no longer a logarithmic relationship. Therefore, it is necessary to use a limiting amplifier to limit the upper power limit of the input to the logarithmic amplifier so that the logarithmic amplifier works within the linear range, thereby obtaining a better splicing result. Therefore, if the fifth signal I51<Limit2, the sixth signal I61 maintains the lower limit value unchanged; if Limit2<fifth signal I51<Limit3, then the (logarithm-converted) sixth signal I61 changes linearly with the fifth signal I51; if the fifth signal I51>Limit4, then the sixth signal I61 changes slightly with the fifth signal I51, but it is not a linear relationship. In particular, due to the limiting effect of the limiting amplifier 131 , the input range of the fifth signal I51 in this embodiment will not be higher than Limit4 .

[0075] See also Figure 7 (c) in the figure shows a schematic diagram of the working curve of the limiting amplifier 131 + logarithmic amplifier 141. By passing the output of the current mirror through the limiting amplifier and the logarithmic amplifier in sequence, it can be achieved that when (the fourth signal I41-the third signal I31) is between Limit4 and Limit1, the sixth signal I61 maintains a linear state, and when (the fourth signal I41-the third signal I31) < Limit4, or (the fourth signal I41-the third signal I31) > Limit1, the sixth signal I61 maintains a minimum value or a maximum value, thereby ensuring the output accuracy of the RMS detector. Here, Limit4 refers to: when the fifth signal I51 is Limit2, the value of the fourth signal I41-the third signal I31).

[0076] In this example, see Figure 8, which takes the number of current mirror units as 2 as an example to illustrate a specific structure of a root mean square detector 10. Figure 8 As shown, assuming that the input dynamic range of the RMS detector 10 is -60dBm to 0dBm, it has 2 current mirror units, 2 limiting amplifiers and 2 logarithmic amplifiers, that is, the output dynamic range is divided into 2 sections: the dynamic range of the fifth signal I51 covers the dynamic input range of -60dBm to -30dBm, and the dynamic range of the fifth signal I52 covers the dynamic input range of -30dBm to 0dBm, so that each logarithmic amplifier only needs to perform logarithmic amplification for the dynamic input range of 30dBm. In this way, for the RMS detector 10, the fifth signal of different power ranges is generated in a segmented manner, and each logarithmic amplifier only needs to perform logarithmic conversion processing on a small range of the fifth signal, thereby reducing the design difficulty of the logarithmic amplifier and improving the correctness of the logarithmic conversion process; in addition, the third signal and the fourth signal of different power ranges can be generated by multiple current mirror units (that is, power segmentation is achieved), without introducing a cascaded differential amplifier chain, and the mismatch of each differential amplifier in the differential amplifier chain will be superimposed, so the mismatch of this embodiment is also relatively small, further improving the accuracy of the output result.

[0077] like Figure 8 As shown, each current mirror unit includes a first current mirror, a second current mirror, a first voltage conversion unit 161 / 171 and a second voltage conversion unit 162 / 172 .

[0078] Each first current mirror includes a first transistor 21 and a second transistor 221 / 222, and different first current mirrors share the same first transistor 21; wherein the first transistor 21 is used to receive a first signal I1, and the second transistor 221 / 222 is used to output a third signal, for example, the gate terminal of the first transistor 21, the gate terminal of the second transistor, and the second terminal of the first transistor 21 all receive the first signal I1, and the second terminal of the second transistor outputs the third signal; the second terminal of the second transistor is connected to the ground terminal through a first voltage conversion unit. Each second current mirror includes a third transistor 23 and a fourth transistor 241 / 242, and different second current mirrors share the same third transistor 23, wherein the third transistor 23 is used to receive a second signal I2, and the fourth transistor 241 / 242 is used to output a fourth signal, for example, the gate terminal of the third transistor 23, the gate terminal of the fourth transistor, and the second terminal of the third transistor 23 all receive the second signal I2, and the second terminal of the fourth transistor outputs the fourth signal; the second terminal of the fourth transistor is connected to the ground terminal through a second voltage conversion unit.

[0079] That is to say, the first current mirror unit 121 includes a first current mirror composed of a first transistor 21 and a second transistor 221, a second current mirror composed of a third transistor 23 and a fourth transistor 241, and a first voltage conversion unit 161 and a second voltage conversion unit 171; the second current mirror unit 122 includes a first current mirror composed of a first transistor 21 and a second transistor 222, a second current mirror in the current mirror unit 122 composed of a third transistor 23 and a fourth transistor 242, and a first voltage conversion unit 162 and a second voltage conversion unit 172.

[0080] Among them, the sizes of the second transistors in different first current mirrors are different, and / or the resistance values ​​of different first voltage conversion units are different, so that different third signals belong to different power ranges; and the sizes of the fourth transistors in different second current mirrors are different, and / or the resistance values ​​of different second voltage conversion units are different, so that different fourth signals belong to different power ranges.

[0081] It should be noted that the transistor can be any type of semiconductor device such as a triode, a MOS transistor, a BJT, or a HBT. Taking the transistor as a MOS transistor as an example, its gate terminal refers to the gate, the first terminal refers to one of the source and the drain, and the second terminal refers to the other of the source and the drain. The size of the transistor refers to the width-to-length ratio of the transistor gate.

[0082] In some embodiments, the first voltage conversion unit and the second voltage conversion unit can be implemented by resistors, but this does not constitute a relevant limitation. The first voltage conversion unit 16 and the second voltage conversion unit 17 can also be diodes or bipolar junction transistors BJT connected to diodes, etc.

[0083] In a specific embodiment, for the purpose of large-scale manufacturing, the width-to-length ratio of the first transistor 21 is equal to the width-to-length ratio of the third transistor 23; in the same current mirror unit, the width-to-length ratio of the second transistor is equal to the width-to-length ratio of the fourth transistor, for example, the width-to-length ratio of the second transistor 221 is equal to the width-to-length ratio of the fourth transistor 241, and the width-to-length ratio of the second transistor 222 is equal to the width-to-length ratio of the fourth transistor 242.

[0084] In the same current mirror unit, the second voltage conversion unit and the first voltage conversion unit have the same resistance value, that is, the first voltage conversion unit 161 and the second voltage conversion unit 171 have the same resistance value, and the first voltage conversion unit 162 and the second voltage conversion unit 172 have the same resistance value.

[0085] In a specific embodiment, taking an input dynamic range of 60 dBm as an example, if the input dynamic range covered by the output signal is divided into two sections, each section covers a 30 dBm input range. The width-to-length ratio of the second transistor 221 (= the fourth transistor 241): the width-to-length ratio of the second transistor 222 (= the fourth transistor 242) is set to 1000:1, and the resistance values ​​of the first voltage conversion unit and the second voltage conversion unit are equal, so that the two output current ranges can be moved to the same dynamic range, and the original total output dynamic range is 0 to 120 dB; however, in this embodiment, (1) for an input dynamic range of -60 dBm to -30 dBm, the output dynamic range of the first segment is 0 to 60 dB, and the output dynamic range of the second segment maintains the lower limit, i.e., 0 dB, and the output dynamic range after superposition is 0 to 60 dB; (2) for an input dynamic range of -30 dBm to -0 dBm, the output of the first segment maintains the upper limit of 60 dB, and the output dynamic range of the second segment is 0 to 60 dB, and the output dynamic range after superposition is 60 to 120 dB. In this way, after the first section and the second end are spliced, an output dynamic range of 0 to 120 dB can be achieved for an input dynamic range of -60 dBm to -30 dBm. Thus, the total output dynamic range is compressed from 120 dB in the related technical solution to 60 dB (each section only needs to support an output dynamic range of 60 dB), reducing the difficulty of circuit design.

[0086] Specifically, the branches corresponding to the second transistor 221 and the fourth transistor 241 are responsible for the input range of 30dBm below, for example, -60dBm to -30dBm, and the branches corresponding to the second transistor 222 and the fourth transistor 242 are responsible for the input range of 30dBm above, for example, -30dBm to 0dBm. Subsequently, the curves are spliced ​​by connecting a limiting amplifier, a logarithmic amplifier, etc. to obtain a complete logarithmic curve, for example, the overall input dynamic range is -60dBm to 0dBm.

[0087] The following are the design parameters of each device in a specific scenario: Figure 8, the input dynamic range of the square module 11 is 60dBm (-60dBm~0dBm), the output current range is 10mA~10nA, the width-to-length ratio of the transistors in the current mirror is set as follows: the first transistor 21: the second transistor 221: the second transistor 222=the third transistor 23: the fourth transistor 241: the fourth transistor 242=1:100:0.1, the resistance of the first voltage conversion unit 161=the resistance of the second voltage conversion unit 171=the resistance of the first voltage conversion unit 162=the resistance of the second voltage conversion unit 172=1kΩ, then the output voltage of the third signal I31-the fourth signal I41 is within 1mV~1V when the input is -60dBm~-30dBm, and the output voltage of the third signal I32-the fourth signal I42 is within 1mV~1V when the input is -30dBm~0dBm.

[0088] At the same time, the linear amplification area of ​​the post-stage limiting amplifier + logarithmic amplifier is exactly between 1mV and 1V:

[0089] (1) When the dynamic range of the input signal of the current mirror unit (i.e., the second signal I2-the first signal I1) is between -60 dBm and -30 dBm, the logarithmic amplifier 141 enters the linear working range, and the input voltage is converted into a logarithmic current output sixth signal I61. At the same time, the input of the limiting amplifier 132 is lower than the linear amplification range, and the output lower limit is always maintained. The post-stage logarithmic amplifier outputs a constant lower limit current, that is, the sixth signal I62 maintains a constant lower limit current;

[0090] (2) When the dynamic range of the input signal of the current mirror unit (i.e., the second signal I2-the first signal I1) increases to between -30 dBm and 0 dBm, the limiting amplifier 131 maintains the output upper limit, and the post-stage logarithmic amplifier 141 outputs a constant upper limit current, i.e., the sixth signal I61 maintains a constant upper limit current, and the logarithmic amplifier 142 enters the linear working range, and the input voltage is converted into a logarithmic current output sixth signal I62. The sixth signal I61 and the sixth signal I62 are added together to realize curve splicing, i.e., the sixth signal I61 and the sixth signal I62 with different linear working ranges are spliced, and for each curve point, one of the sixth signals maintains the upper limit or the lower limit, and the other sixth signal is the linear amplification value.

[0091] It should also be noted that the linear gain of the limiting amplifier can be adjusted according to the requirements of the subsequent logarithmic amplification, and can be designed as amplification, unity gain or attenuation.

[0092] In another specific embodiment, also taking the input dynamic range of 60dBm as an example, the resistance ratio of different voltage conversion units can be changed, while keeping the width-to-length ratio of transistors in different current mirrors the same, to achieve the aforementioned segmentation effect. Specifically, the resistance of the first voltage conversion unit 161 (= the resistance of the second voltage conversion unit 171): the resistance of the first voltage conversion unit 162 (= the resistance of the second voltage conversion unit 172) = 1000:1, the width-to-length ratios of the second transistors 221, 222 and the fourth transistors 242, 242 are all equal, and the aforementioned current segmentation can also be achieved.

[0093] In another specific embodiment, also taking the input dynamic range of 60dBm as an example, the width-to-length ratio of transistors in different current mirrors and the resistance ratio of different voltage conversion units can be changed at the same time to achieve the aforementioned segmentation effect. Figure 8 , the second transistor 221: the second transistor 222 = the fourth transistor 241: the fourth transistor 242 = 100:1; the resistance of the first voltage conversion unit 161: the resistance of the first voltage conversion unit 162 = the resistance of the second voltage conversion unit 171: the resistance of the second voltage conversion unit 172) = 10:1, and the above-mentioned current segmentation can also be achieved.

[0094] In another specific embodiment, if the input dynamic range of 90dBm is taken as an example, and three groups of current mirror units are used; the resistance of the voltage conversion unit of the first group of current mirror units and the second group of current mirror units is the same, and the transistor width-to-length ratio is different; the transistor width-to-length ratio of the first group of current mirror units and the third group of current mirror units is the same, and the resistance of the voltage conversion unit is different, so as to achieve current segmentation. For example, the second transistor 221: the second transistor 222 (= the second transistor 223) = 1000:1, and the fourth transistor 241: the fourth transistor 242 (= the fourth transistor 243) = 1000:1; the resistance of the first voltage conversion unit 161 (= the resistance of the first voltage conversion unit 162): the resistance of the first voltage conversion unit 163 = 1000:1, and the resistance of the second voltage conversion unit 171 (= the resistance of the first voltage conversion unit 172): the resistance of the second voltage conversion unit 173 = 1000:1.

[0095] The following are the design parameters of each device in a specific scenario: Figure 8, the output current range of the square module 11 is 10mA~10nA, and the width-to-length ratio of the transistors in the current mirror is set as follows: the first transistor 21: the second transistor 221: the second transistor 222=the third transistor 23: the fourth transistor 241: the fourth transistor 242=1:0.1:0.1, the resistance of the first voltage conversion unit 161=the resistance of the second voltage conversion unit 171=1MΩ, the resistance of the first voltage conversion unit 162=the resistance of the second voltage conversion unit 172=1kΩ, then the voltage of the third signal I31-the fourth signal I41 is within 1mV~1V when the input is -60dBm~-30dBm, and the voltage of the third signal I32-the fourth signal I42 is within 1mV~1V when the input is -30dBm~0dBm, realizing the same segmentation function.

[0096] In the above scenario, since the first transistor 21: the second transistor 221: the second transistor 222 = the third transistor 23: the fourth transistor 241: the fourth transistor 242 = 1: 0.1: 0.1, the current output by the first current mirror / the second current mirror is much smaller than the input current, and the impedance of the corresponding voltage conversion unit can be designed to be larger, so that a small error in the manufacturing of the voltage conversion unit will not have a significant impact on the subsequent results. At the same time, the above ratio values ​​do not constitute a limitation and can be selected by oneself in actual applications.

[0097] In addition, different current mirror sizes and impedances of voltage conversion units can be selected according to different segmentation methods. However, for the convenience of subsequent splicing design, the input and output ranges of each segment are usually equal.

[0098] At this time, the width-to-length ratio of each current mirror segment can be reduced segment by segment in proportion to the segment length.

[0099] For example, the square module 11 corresponds to an input dynamic range of 60 dBm and an output voltage range of 120 dB. The output is divided into two sections, each section corresponds to an output range of 60 dB, and the impedance ratio of the two current mirror units in the section is 1000 times. (1) In one design, the width-to-length ratio of the second transistor (and the width-to-length ratio of the fourth transistor) in the two current mirror units of the segmented output is 1000:1, and the impedance of the voltage conversion unit is the same. (2) In another design, the width-to-length ratio of the transistors in the two current mirror units of the segmented output is the same, and the impedance ratio of the first voltage conversion unit (and the impedance ratio of the second voltage conversion unit) in the two current mirror units is 1000:1.

[0100] For example, the square module 11 corresponds to an input dynamic range of 60 dBm and an output voltage range of 120 dB. The output is divided into three sections, each section corresponds to an output voltage range of 40 dB, and the impedance ratio of two adjacent current mirror units in the section is 100 times. (1) In one design, the width-to-length ratio of the second transistor (and the width-to-length ratio of the fourth transistor) in the three current mirror units of the segmented output is 10000:100:1, and the impedance of the voltage conversion unit is the same. (2) In another design, the width-to-length ratio of the transistors in the three current mirror units of the segmented output is the same, and the impedance ratio of the first voltage conversion unit (and the impedance ratio of the second voltage conversion unit) in the three current mirror units is 10000:100:1.

[0101] For example, the square module 11 corresponds to an input dynamic range of 60 dBm and an output voltage range of 120 dB. The output is divided into six segments, each segment corresponds to an output voltage range of 20 dB, and the impedance ratio of two adjacent current mirror units in the segment is 10 times. (1) In one design, the width-to-length ratio of the second transistor (and the width-to-length ratio of the fourth transistor) in the six current mirror units of the segmented output is 100000: 10000: 1000: 100: 10: 1, and the impedance of the voltage conversion unit is the same. (2) In another design, the width-to-length ratio of the transistors in the six current mirror units of the segmented output is the same, and the impedance ratio of the first voltage conversion unit (and the impedance ratio of the second voltage conversion unit) in the six current mirror units is 100000: 10000: 1000: 100: 10: 1.

[0102] And so on.

[0103] In some embodiments, the limiting amplifier includes a differential amplifier, and the two differential input terminals of the differential amplifier receive the third signal and the fourth signal respectively. In this case, the limiting amplifier has both a subtraction function (subtraction of the third signal and the fourth signal) and a function of limiting the subtracted signal.

[0104] In some other embodiments, the limiting amplifier includes a subtractor and a differential amplifier, the subtractor receives the third signal and the fourth signal, and a differential input terminal of the differential amplifier receives the output signal of the subtractor, and another differential input terminal of the differential amplifier receives the reference signal. In this case, the subtractor is used to implement the subtraction function (the third signal is differentiated from the fourth signal), and then the differential amplifier mainly implements the function of limiting the subtracted signal.

[0105] It should be noted that the above logarithmic amplifier can be a full-wave rectifier.

[0106] In some embodiments, the logarithmic amplifier output current signal can be directly added on the final output line, for example, the output terminals of all logarithmic amplifiers are directly connected to form a target output terminal at the intersection point P, and the target output terminal generates a target output signal.

[0107] In other embodiments, if the logarithmic amplifier outputs a voltage signal, an adder is required to add the outputs of all logarithmic amplifiers. That is, the RMS detector 10 also includes an adder, the outputs of all logarithmic amplifiers are connected to the input of the adder, and the output of the adder generates a target output signal.

[0108] See also Figure 8 The RMS detector 40 further includes an averaging capacitor 204, which is connected in series between the input terminal and the ground terminal of the first transistor 21. It should be understood that the averaging capacitor 204 is used to implement an averaging operation, so that the averaging operation and the square operation are performed together, the overall current is more stable, and the subsequent processing is more accurate.

[0109] In some other embodiments, the average capacitor 204 may also be connected in series between the output terminal of each limiting amplifier and the ground terminal. Figure 3 To understand.

[0110] From the above, it can be seen that for the RMS detector 10, the output power is transferred to different power ranges in a segmented manner, and each logarithmic amplifier only needs to perform logarithmic conversion processing on a small range, thereby reducing the design difficulty of the logarithmic amplifier and improving the accuracy of the RMS detector 10.

[0111] In addition, in order to improve the problem of inaccurate detection results caused by the offset current between the square unit 111 and the mirror square unit 112, please refer to Fig. 9 The RMS detector 10 also includes at least one trimming unit 15, which is connected to the corresponding current mirror unit and is used to adjust the mirror copy ratio of the first current mirror or the mirror copy ratio of the second current mirror in the current mirror unit, so as to eliminate the current mismatch between the third signal and the fourth signal.

[0112] Specifically, since the DC portion between the first signal and the second signal is not completely the same, the DC portion between the third signal and the fourth signal is also not completely the same, resulting in a current mismatch between the third signal and the fourth signal; through the adjustment unit, the mirror copy ratio when the first signal is copied to generate the third signal can be adjusted (or the mirror copy ratio when the second signal is copied to generate the third signal is adjusted), so that even if the DC portion between the first signal and the second signal is not completely the same, due to the difference in the mirror copy ratio, the DC portion of the third signal and the fourth signal can be made completely the same, thereby eliminating the current mismatch between the third signal and the fourth signal.

[0113] In the first specific embodiment, see Fig. 9 , each current mirror unit is connected to a trimming unit 15 . Fig. 9 Taking two current mirror units as an example, the number of the trimming units 15 is also two, and one current mirror unit is connected to one trimming unit.

[0114] In the second specific embodiment, see Fig.10 , only a part of the current mirror units are connected to one of the trimming units 15 . Fig.10 Taking two current mirror units as an example, the number of the trimming unit 15 is one, and only the first current mirror unit is connected to the trimming unit, and the first current mirror unit is not provided with the trimming unit.

[0115] In simple terms, taking the input range of -60dBm to 0dBm as an example, for the corresponding current mirror unit with a smaller input range (i.e., -60dBm to -30dBm), the DC mismatch between the third signal and the fourth signal will cause a very large error to the subsequent circuit, so it is necessary to introduce the adjustment unit 15 for calibration; however, for the corresponding current mirror unit with a larger input range (i.e., -30dBm to -00dBm), the DC mismatch between the third signal and the fourth signal is negligible relative to its power value, so it will not cause obvious errors to the subsequent circuit, so there is no need to introduce the adjustment unit 15.

[0116] See also Fig.11 , which takes one trimming unit 15 as an example to illustrate the composition of the trimming unit 15 and the connection relationship between the trimming unit 15 and the current mirror unit, and Fig.11 The example in which the trimming unit 15 is connected to the second current mirror (and used to adjust the mirror copy ratio of the second current mirror) is used for illustration.

[0117] See also Fig.11 The trimming unit includes a plurality of fifth transistors, and the plurality of fifth transistors are connected to the fourth transistor 24; the trimming unit 15 is configured to receive a control signal to control each of the fifth transistors to be in a closed state or a working state; the control signal is used to adjust the mirror copy ratio of the second current mirror.

[0118] Thus, when the fifth transistor is in working state, it is used to increase the width-to-length ratio of the fourth transistor 24, thereby increasing the mirror copy ratio of the second current mirror. Fig.11As shown, when the fifth transistor is turned on, the fourth transistor 24 and the fifth transistor in working state are connected in parallel, which is equivalent to increasing the equivalent size of the fourth transistor 24 of the second current mirror (i.e., the width-to-length ratio of the transistor gate). In simple terms, the more the number of first transistors 21 in working state, the higher the mirror copy ratio of the output signal of the current mirror relative to the input signal. For example, if all the fifth transistors are in the off state, at this time the fourth signal I4 = the current I4o directly output by the fourth transistor 24; if the fifth transistor 151a is in working state, the fourth signal I4 = I4o + I4a; if the fifth transistor 151a and the fifth transistor 151b are both in working state, the fourth signal I4 = I4o + I4a + I4b...

[0119] In this way, the size of the fourth signal I4 can be adjusted by the adjustment unit 15, so that the difference between the DC parts of the third signal I3 and the fourth signal I4 is within a first range. The first range is a preset range, and when the difference is within the first range, the mismatch between the square unit 111 and the mirror square unit 112 can be ignored. The first range can be close to 0, and when the difference is 0, the mismatch between the square unit 111 and the mirror square unit 112 is completely calibrated.

[0120] At the same time, the current output by the third transistor 23 includes the temperature characteristics of the square unit, and the fourth transistor 24 and the trimming unit 15 are both copies of the current of the third transistor 23. If the fourth transistor 24 and the trimming unit 15 are of the same device type, the working curves of the two have the same change trend, so even if it is calibrated at a single temperature point, the calibration effect is still good after the working temperature changes. Alternatively, if the trimming unit 15 and the fourth transistor 24 have different device doping types, it is necessary to add an additional temperature control signal and perform multi-temperature point calibration. It is also possible to design a current with temperature characteristics, thereby also achieving single-point calibration.

[0121] like Fig.11 As shown, the trimming unit 15 further includes a plurality of first switches 152a-152d, and the first switch is used to control the fifth transistor. In order to achieve the best control efficiency, the number of the first switches is the same as the number of the fifth transistors. The following is a detailed description of this situation but does not constitute a specific limitation. Fig.11 As shown, the first switches 152a~152d can correspond one-to-one to the fifth transistors 151a~151d, and each first switch is used to control the gate connection state of a fifth transistor. The first switches 152a~152d are based on the control signal to turn on the control terminal of the corresponding fifth transistor and the power supply voltage VDD, or turn on the control terminal of the corresponding fifth transistor and the first node, and the first node is the connection node between the third transistor 23 and the fourth transistor.

[0122] Exemplarily, the first switches 152a to 152d are all first single-pole double-throw switches, which can conveniently control the gate connection state of the fifth transistor. The first single-pole double-throw switch has a control terminal ( Fig.11 ), a fixed terminal s, a first gating terminal c1, and a second gating terminal c2. Taking the fifth transistor as a P-type doping as an example, the fixed terminal s and the second gating terminal c2 are connected based on the control terminal signal to set the fifth transistor corresponding to the first single-pole double-throw switch to a working state, or the fixed terminal s and the first gating terminal c1 are connected based on the control terminal signal to set the fifth transistor corresponding to the first single-pole double-throw switch to a closed state. The control terminal of the first single-pole double-throw switch receives the control signal, the first gating terminal c1 of the first single-pole double-throw switch is connected to the power supply voltage VDD, and the second gating terminal c2 of each first single-pole double-throw switch is connected to the first node, which can be regarded as receiving the second signal, and the fixed terminal s of a first single-pole double-throw switch is connected to the gate of a fifth transistor. In the case where the fifth transistor is a PMOS transistor, the first end of the fifth transistor is connected to the power supply voltage VDD. The second end of the fifth transistor is connected to the output end of the fourth transistor 24.

[0123] Fig.11 Only the example that the trimming unit 15 includes four fifth transistors and four first switches is used for illustration, but the number of the fifth transistors and the number of the first switches can be flexibly selected. Here, the number of the control signal Trim Code is the same as the number of the first switches. It should be understood that if the number of the first switches is more or less, the number of bits of the control signal can also be more or less.

[0124] In this way, if a control signal is in the first state (for example, a low level), the fixed end s of the first single-pole double-throw switch corresponding to the control signal is connected to the power supply voltage VDD, and the corresponding fifth transistor is turned off; if a control signal is in the second state (for example, a high level), the fixed end s of the first single-pole double-throw switch corresponding to the control signal is connected to the first node (that is, receiving the second signal), that is, the second signal controls the current flowing through the fifth transistor, which is equivalent to the fifth transistor being connected in parallel with the P-type transistor in the fourth transistor 24, thereby increasing the width-to-length ratio of the P-type transistor in the fourth transistor 24.

[0125] exist Fig.11 In the embodiment shown, the square unit 111 outputs a first signal I1, and the mirror square unit 112 outputs a second signal I2. The first signal I1=I B +I SQ +I OS , for I B is the quiescent current, I SQ is the square current, I OS is the offset current I OS , the second signal I2 = IB Assuming that the mirror ratios of the first current mirror and the second current mirror are both one to one, the current I30 output by the second transistor = I1 = I B +I SQ +I OS , the current I4o output by the fourth transistor 24 = I2 = I B .

[0126] The currents I4a-I4d output by the fifth transistors 151a-151d are used to compensate for the offset current I OS , such as the offset current I OS A current I4a is required for compensation, that is, I4a = I OS , it is only necessary to control the signal to connect the fixed terminal s and the second gate terminal c2 of the first switch 152a, and to connect the fixed terminal s and the first gate terminal c1 of the first switches 152b-152d. Then the output current I4 of the second current mirror is I4o+I4a, therefore, I30-I4=(I B +I SQ +I OS )-(I B +I41)=I SQ It can be seen that the offset current I in the first signal I1 and the second signal I2 OS are offset. OS As the temperature changes, I4a as a mirror current also changes with the temperature, so I4a can dynamically compensate for the mismatch problem.

[0127] In the above description, the current mirror is used as follows Fig.12 In the first variant, any other type of current mirror structure may be used, such as Fig.12 (b) to (d) in the above, even if Fig.12 In the structures (b) to (d), the first current mirror includes at least two transistors, namely the first transistor and the second transistor; the second current mirror includes at least two transistors, namely the third transistor and the fourth transistor, and therefore the above description is also applicable.

[0128] like Fig.11 In the RMS detector 10 shown in FIG. 1 , a plurality of fifth transistors 151a to 151d are connected in parallel with the fourth transistor 24. In the second variant, for example Fig.13In this case, the plurality of fifth transistors 151a-151d can also be connected in series with the plurality of fourth transistors 24 respectively. Meanwhile, the switching states of the fifth transistors 151a-151d depend on the corresponding trimming signals Trim[0]-Trim[3], wherein Trim[0]-Trim[3] are respectively the trimming signals TrimCode on the gates of the fifth transistors 151a-151d, and the mirror ratio can also be adjusted.

[0129] like Fig.11 In the RMS detector 10 shown, the plurality of fifth transistors 151a-151d in the trimming unit 15 are respectively connected to the fourth transistor 24. In a third variation, the plurality of fifth transistors in the trimming unit 15 are respectively connected to the second transistor 22. The trimming unit 15 is configured to receive a control signal to control each of the fifth transistors to be in a closed state or a working state; the control signal is used to adjust the mirror copy ratio of the first current mirror.

[0130] like Fig.11 In the RMS detector 10 shown, the transistors in the current mirror unit and the transistors in the trimming unit 15 are both P-type transistors. In a fourth variation, the transistor types in the current mirror and the transistor types in the trimming unit 15 can be replaced with N-type transistors, but the corresponding technical details need to be adaptively modified.

[0131] like Fig.11 In the RMS detector 10 shown, the mirror image square unit 112 receives the bias voltage DC Bias. In the fifth variation, the mirror image square unit 112 may also receive the bias voltage DC Bias+feedback voltage Feedback, where the feedback voltage Feedback refers to the voltage generated by other circuit modules of the square circuit that also affects the signal, so that the mirror image square unit 112 can replicate the influencing factors caused by the feedback voltage, so that the accurate square result of the AC signal is obtained after the third signal and the fourth signal are subtracted.

[0132] like Fig.11 In the RMS detector 10 shown, the first transistor 21 receives the first signal I1, and the third transistor 23 receives the second signal I22. In the sixth variation, the first transistor 21 may receive the second signal I2, and the third transistor 23 may receive the first signal I1, and the purpose of accurate measurement may also be achieved.

[0133] The embodiment of the present application provides a root mean square detector 10, which significantly reduces the input dynamic range of the subsequent logarithmic amplifier by segmentation, thereby reducing the design difficulty of the subsequent logarithmic amplifier; at the same time, there is no cascaded limiting amplifier chain in the present solution, and each segmented limiting amplifier is independent of each other, and their respective mismatches do not affect each other, thereby reducing the mismatch requirements for the limiting amplifier.

[0134] In yet another embodiment of the present application, the embodiment of the present application further provides an electronic device, which includes the aforementioned root mean square detector 10.

[0135] The above are only preferred embodiments of the present application and are not intended to limit the scope of protection of the present application. It should be noted that in the present application, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that the process, method, article or device including a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "including one..." do not exclude the existence of other identical elements in the process, method, article or device including the element. The above serial numbers of the embodiments of the present application are only for description and do not represent the advantages and disadvantages of the embodiments. The methods disclosed in the several method embodiments provided in the present application can be arbitrarily combined without conflict to obtain new method embodiments. The features disclosed in the several product embodiments provided in the present application can be arbitrarily combined without conflict to obtain new product embodiments. The features disclosed in the several method or device embodiments provided in the present application can be arbitrarily combined without conflict to obtain new method embodiments or device embodiments. The above are only specific implementation methods of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be covered by the protection scope of the present application.

Claims

1. A root mean square detector, characterized in that: include: Square module; The device is configured to receive a bias voltage and an AC signal, square the bias voltage and the AC signal as a whole to output a first signal, and square the bias voltage to output a second signal; A plurality of current mirror units; each of the current mirror units is connected to the square module, and is configured to receive and copy the first signal and the second signal respectively, and output a third signal and a fourth signal; different third signals belong to different power ranges, and different fourth signals belong to different power ranges; A plurality of limiting amplifiers; each of the limiting amplifiers is connected to the corresponding current mirror unit, and is configured to receive and perform subtraction and limiting processing on the third signal and the fourth signal, and output a fifth signal; wherein different limiting amplifiers have different limiting thresholds; Multiple logarithmic amplifiers; each of the logarithmic amplifiers is connected to the corresponding limiting amplifier and is configured to receive and perform logarithmic conversion on the fifth signal to generate a sixth signal; wherein the output ends of all the logarithmic amplifiers are connected together, and all the sixth signals are superimposed to generate a target output signal.

2. The root mean square detector according to claim 1, characterized in that: Each of the current mirror units includes a first current mirror, a second current mirror, a first voltage conversion unit and a second voltage conversion unit; The first current mirrors each include a first transistor and a second transistor, and different first current mirrors share the same first transistor; a gate terminal of the first transistor, a gate terminal of the second transistor, and a second terminal of the first transistor all receive the first signal, and the second terminal of the second transistor outputs the third signal; the second terminal of the second transistor is connected to the ground terminal through the first voltage conversion unit; The second current mirrors each include a third transistor and a fourth transistor, and different second current mirrors share the same third transistor; a gate terminal of the third transistor, a gate terminal of the fourth transistor and a second terminal of the third transistor all receive the second signal, and the second terminal of the fourth transistor outputs the fourth signal; the second terminal of the fourth transistor is connected to the ground terminal through the second voltage conversion unit; Wherein, the sizes of the second transistors in different first current mirrors are different, and / or the resistance values ​​of different first voltage conversion units are different; The sizes of the fourth transistors in different of the two current mirrors are different, and / or the resistance values ​​of different of the second voltage conversion units are different.

3. The root mean square detector according to claim 2, characterized in that: It also includes at least one trimming unit, wherein the trimming unit is connected to the corresponding current mirror unit; The trimming unit includes a plurality of fifth transistors, and the plurality of fifth transistors are connected to the second transistor or the fourth transistor; The trimming unit is configured to receive a control signal to control each of the fifth transistors to be in a closed state or a working state; the control signal is used to adjust the mirror copy ratio of the first current mirror or the second current mirror.

4. The root mean square detector according to claim 2 or 3, characterized in that: The third signal and the fourth signal output by the same current mirror unit belong to the same power range; The width-to-length ratio in the first transistor=the width-to-length ratio in the third transistor; In the same current mirror unit, the width-to-length ratio of the second transistor is equal to the width-to-length ratio of the fourth transistor.

5. The root mean square detector according to claim 2 or 3, characterized in that: The third signal and the fourth signal output by the same current mirror unit belong to the same power range; In the same current mirror unit, the resistance value of the second voltage conversion unit is the same as that of the first voltage conversion unit.

6. The root mean square detector according to any one of claims 1 to 3, characterized in that: The limiting amplifier includes a differential amplifier, and two differential input terminals of the differential amplifier receive the third signal and the fourth signal respectively; or, The limiting amplifier includes a subtractor and a differential amplifier, the subtractor receives the third signal and the fourth signal, a differential input terminal of the differential amplifier receives an output signal of the subtractor, and another differential input terminal of the differential amplifier receives a reference signal.

7. The root mean square detector according to any one of claims 1 to 3, characterized in that: The logarithmic amplifier is a full-wave rectifier.

8. The root mean square detector according to any one of claims 1 to 3, characterized in that: The output ends of all the logarithmic amplifiers are directly connected to form a target output end, and the target output end generates the target output signal; or, the root mean square detector also includes an adder, the output ends of all the logarithmic amplifiers are connected to the input end of the adder, and the output end of the adder generates the target output signal.

9. The root mean square detector according to claim 2, characterized in that: The RMS detector further includes an average capacitor, which is connected in series between the input terminal and the ground terminal of the first transistor; or, the average capacitor is connected in series between the output terminal and the ground terminal of the limiting amplifier.

10. An electronic device, characterized in that: The electronic device comprises a root mean square detector as claimed in any one of claims 1 to 9.

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