A three-chip FPGA heterogeneous accelerator card
By designing a three-chip FPGA heterogeneous acceleration card, using PCIE gen4 interface and high-performance FPGA chip, the problem of insufficient performance of existing FPGA heterogeneous computing cards is solved, and high-performance data transmission and computing acceleration are achieved.
Patent Information
- Application Number
- CN202421539519.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-07-02
- Publication Date
- 2025-04-08
- Estimated Expiration
- 2034-07-02
AI Technical Summary
During the accelerated computing process, existing FPGA heterogeneous computing cards have problems such as insufficient heterogeneous resources, slow interaction speed between FPGAs, lack of cache, and low PCIE transmission speed, resulting in insufficient performance.
A three-chip FPGA heterogeneous acceleration card is designed, using PCIE gen4 interface, using a Xilinx UltraScale 16nm VU37P chip and two VU13P chips to achieve high-performance data transmission and computing acceleration.
It significantly improves the performance of heterogeneous accelerator cards, achieves high throughput and low latency network processing capabilities, and assists the CPU in network function offloading, saves CPU computing power, and reduces CPU usage and power consumption.
Smart Images
Figure CN222734480U_ABST
Abstract
Description
Technical Field
[0001] The utility model belongs to the technical field of FPGA data processing, and in particular relates to an FPGA heterogeneous acceleration card based on three chips. Background Art
[0002] Heterogeneous computing uses different types of processors to handle different computing tasks. The most common ones are GPU, ASIC, DSP, and FPGA. GPU has a wide parallel structure, and high-end GPU has very high double-precision floating-point computing capabilities. ASIC has the acceleration capability in the instruction field. Chip-based acceleration algorithms in special fields are implemented to achieve heterogeneous acceleration functions. DSP is used as an accelerator, and the floating-point computing capability of DSP is used to implement double floating-point operations of large matrices. FPGA heterogeneous acceleration has the characteristics of high flexibility, fast computing speed, and high real-time performance.
[0003] At present, in the PCIE gen3 type of heterogeneous computing cards of FPGA, the programming model of FPGA array type in the accelerated computing process has shortcomings, such as insufficient heterogeneous resources, insufficient interaction speed between FPGAs, lack of high-speed cache in FPGAs, and low transmission speed of PCIE. In order to obtain better performance from heterogeneous computing systems with FPGAs and traditional processors working together, a lot of effort is needed to convert traditional codes into appropriate FPGA architectures and carefully design hardware configurations to achieve overall functions. The above work requires rich FPGA design expertise and a lot of cost investment, as well as overall strategic experience in inputting and outputting data into and out of these FPGA accelerators to complete the memory and storage architecture of the task.
[0004] However, it is very difficult for technicians in this field to complete the above work. How to design a new FPGA heterogeneous acceleration card to solve the above technical problems has become a technical difficulty in this field. Utility Model Content
[0005] In response to the above technical problems, the utility model provides a three-chip FPGA heterogeneous acceleration card. The heterogeneous acceleration card utilizes a heterogeneous FPGA with a PCIE gen4 interface to achieve ultra-high-speed data transmission bandwidth with a PC processor. Based on three high-performance FPGAs, it can be applied to high-performance computing storage, network acceleration and other fields, and can significantly improve the performance of the heterogeneous acceleration card.
[0006] The utility model solves the above problems through the following technical means:
[0007] A three-chip FPGA heterogeneous accelerator card, characterized in that it includes a VU37P chip and two VU13P chips, the first VU13P chip and the second VU13P chip are respectively arranged on both sides of a VU37P chip, wherein: the BANK_127, BANK_128, BANK_129, BANK_130, BANK_131, BANK_132, BANK_133, BANK_134, and BANK_135 pin sets of the VU37P chip are respectively connected to the BANK_232, BANK_224, BANK_225, BANK_226, BANK_227, BANK_228, BANK_139, BANK_240, BANK_241, BANK_242, BANK_243, BANK_244, BANK_245, BANK_246, BANK_247, BANK_248, BANK_249, BANK_250, BANK_251, BANK_252, BANK_253, BANK_254, BANK_255, BANK_256, BANK_257, BANK_258, BANK_259, BANK_260, BANK_261, BANK_262, BANK_263, BANK_264, BANK_265, BANK_266, BANK_267, BANK_268, BANK_269, BANK_269, BANK_261, BANK_269, BANK_261, BANK_269, BANK_261, BANK_262, NK_229, BANK_230, BANK_231 pin sets; the BANK_227, BANK_228, BANK_229, BANK_330, BANK_331, BANK_332, BANK_333, BANK_342, BANK_335 pin sets of the VU37P chip are respectively connected to the BANK_232, BANK_231, BANK_230, BANK_229, BANK_228, BANK_227, BANK_226, BANK_225, BANK_224 pin sets of the second VU13P chip; the BANK_224 pin set of the VU37P chip is connected to the PCIE bus pins.
[0008] Preferably, it also includes a power supply circuit composed of an LTM4650 chip, an LTM4644 chip, and an LTM4622 chip, wherein: the 12V input power supply is converted into a 0.85V power supply by multiple LTM4650 chips and delivered to the INTVCC pin of the VU37P chip; the 12V input power supply is converted into 1.2V power supply, 1.0V power supply, 1.8V power supply, 1.2V power supply, 1.8V power supply and 2.5V power supply by the LTM4644 chip and delivered to the MGTAVTT pin, MGTAVCC pin, VCCAUX pin, VCC_HBM pin, VCC_1V8 pin, and VCCAUX_HBM pin of the VU37P chip respectively; the 12V input power supply is converted into a 0.85V power supply by multiple LTM4650 chips and delivered to the INTVCC pin of the first VU13P chip; the 12V input power supply is converted into a 0.85V power supply by multiple LTM4650 chips and delivered to the INTVCC pin of the first VU13P chip; the 12V input power supply is converted into a 1.2V power supply, a 1.0V power supply, a 1.8V power supply, a 1.2V power supply, and a 2.5V power supply by the LTM4644 chip and delivered to the MGTAVTT pin, the MGTAVCC pin, the VCCAUX pin, the VCC_HBM pin, the VCC_1V8 pin, and the VCCAUX_HBM pin of the VU37P chip respectively. The input power is converted into 0.9V power and 1.2V power respectively through multiple LTM4644 chips and delivered to the MGTAVCC pin and MGTAVTT pin of the first VU13P chip respectively; the 12V input power is converted into 1.8V power through the LTM4622 chip and delivered to the VCC1V8 pin of the first VU13P chip; the 12V input power is converted into 0.85V power through multiple LTM4650 chips and delivered to the INTVCC pin of the second VU13P chip; the 12V input power is converted into 0.9V power and 1.2V power respectively through multiple LTM4644 chips and delivered to the MGTAVCC pin and MGTAVTT pin of the second VU13P chip respectively; the 12V input power is converted into 1.8V power through the LTM4622 chip and delivered to the VCC1V8 pin of the second VU13P chip.
[0009] Preferably, it also includes a JTAG debugging circuit consisting of a switching switch and a JTAG debugging interface, the JTAG debugging interface is connected to the TDI pin, TMS pin, TCK pin and TDO pin of the VU13P chip through the switching switch, and the JTAG debugging interface is connected to the TDI pin, TMS pin, TCK pin and TDO pin of the VU37P chip through the switching switch.
[0010] Preferably, it also includes a heat sink, a cover plate, and a circuit board for mounting the chip, wherein: the heat sink is a rectangular structure, a plurality of heat dissipation teeth are evenly cut out on the four sides of the heat sink, a mounting cavity is arranged in the middle of the heat sink, X-shaped connecting arms are arranged at the four corners of the heat sink, connecting holes are arranged at the ends of the X-shaped connecting arms, and arc-shaped tooth roots are formed at the positions where the heat dissipation teeth contact the X-shaped connecting arms; the cover plate is composed of a cover body and a plurality of mounting ears, and the circuit board is installed in the cavity formed by the cover plate and the mounting cavity.
[0011] Preferably, a sealing ring is provided between the cover plate and the installation cavity. The bottom of the heat sink is provided with one or more circular bottom cavities, and a tooth platform is provided at the portion where the circular bottom cavity overlaps with the heat dissipation teeth to ensure that the bottom of the circular bottom cavity is flat, and a heat dissipation fan is installed in the circular bottom cavity. A side opening is provided on the side of the heat sink, and a plurality of interfaces are installed on the side opening.
[0012] The utility model provides a three-chip FPGA heterogeneous acceleration card with the following beneficial effects:
[0013] 1) The heterogeneous accelerator card has three high-performance FPGAs loaded on the same hardware board, and uses high-speed hardware circuit design technology to achieve high-speed interconnection of multiple chips on the board. At the same time, one interface can be used to complete the configuration of multiple FPGAs. The total on-chip integrated memory of the accelerator card can reach 500Mb, and the high-bandwidth memory can reach 16GB. It also supports PCIe 4th generation and transceivers with speeds up to 32.75Gb / s. In addition, the heterogeneous accelerator card uses heterogeneous FPGAs with PCIE gen4 interfaces to achieve ultra-high-speed data transmission bandwidth, which is much higher than the transmission speed of traditional PCIE.
[0014] 2) This heterogeneous acceleration card is an FPGA PCI-Express v3.0 x16 acceleration computing card developed based on Xilinx UltraScale's 16 nm VU37P chip and two VU13P chip solutions. This heterogeneous acceleration card has high throughput, low-latency network processing capabilities and the ability to assist the CPU in offloading network functions, thereby saving CPU computing power, reducing CPU occupancy and also reducing power consumption.
[0015] 3) The heat sink of the heterogeneous accelerator card is made of heat-conducting metal material, and heat-dissipating teeth are designed on the entire side. The heat-dissipating teeth around and the heat-dissipating fan at the bottom can effectively reduce the temperature of the accelerator card. In particular, the circular bottom cavity at the bottom and the heat-dissipating teeth adopt a coincident layout scheme, which can accelerate the gas flow between the heat-dissipating teeth as much as possible. The design scheme of the arc-shaped tooth root can greatly reduce the wall thickness and improve the thermal conductivity. BRIEF DESCRIPTION OF THE DRAWINGS
[0016] In order to more clearly illustrate the technical solution of the present invention, the drawings required for use in the implementation mode will be briefly introduced below. Obviously, the drawings described below are only some implementation modes of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.
[0017] Figure 1 It is the overall circuit diagram of the utility model;
[0018] Figure 2 It is a schematic diagram of a power supply circuit of the utility model;
[0019] Figure 3 It is a schematic diagram of the debugging interface circuit of the utility model;
[0020] Figure 4 It is a schematic diagram of the pins of the VU37 chip of the utility model;
[0021] Figure 5 This is a schematic diagram of the pinout of the VU13P chip of the utility model;
[0022] Figure 6 This is a schematic diagram of the overall structure of the heat sink of the utility model;
[0023] Figure 7 This is a schematic diagram of the bottom structure of the heat sink of the utility model;
[0024] Figure 8 It is a schematic diagram of the side structure of the heat sink of the utility model.
[0025] In the formula, 1-heat sink, 101-heat dissipation tooth, 102-mounting cavity, 103-X-type connecting arm, 104-connecting hole, 105-arc tooth root, 106-sealing ring, 107-circular bottom cavity, 108-tooth platform, 109-cooling fan, 110-side port, 111-interface, 2-cover plate, 201-cover body, 202-mounting ear, 3-circuit board. DETAILED DESCRIPTION
[0026] In the description of the present utility model, it should be understood that the terms "center", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside" and the like indicate positions or positional relationships based on the positions or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present utility model and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present utility model. The terms "first" and "second" are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present utility model, unless otherwise specified, "multiple" means two or more.
[0027] The present invention will be described in detail below with reference to the accompanying drawings.
[0028] like Figures 1 to 5As shown, the three-chip FPGA heterogeneous accelerator card includes a VU37P chip and two VU13P chips. The first VU13P chip and the second VU13P chip are respectively arranged on both sides of a VU37P chip. In the figure: the BANK_127, BANK_128, BANK_129, BANK_130, BANK_131, BANK_132, BANK_133, BANK_134, and BANK_135 pin sets of the VU37P chip are respectively connected to BANK_232, BANK_224, BANK_225, BANK_226, BANK_227, BANK_228, BANK_139, BANK_240, BANK_241, BANK_242, BANK_243, BANK_244, BANK_245, BANK_246, BANK_247, BANK_248, BANK_249, BANK_250, BANK_251, BANK_252, BANK_253, BANK_254, and BANK_255 of the first VU13P chip. _229, BANK_230, BANK_231 pin sets; the BANK_227, BANK_228, BANK_229, BANK_330, BANK_331, BANK_332, BANK_333, BANK_342, BANK_335 pin sets of the VU37P chip are respectively connected to the BANK_232, BANK_231, BANK_230, BANK_229, BANK_228, BANK_227, BANK_226, BANK_225, BANK_224 pin sets of the second VU13P chip; the BANK_224 pin set of the VU37P chip is connected to the PCIE bus pins.
[0029] Specifically, the model of the VU37P chip is XCVU37PfSVH2892, and the model of the VU13P chip is XCVU13P-L2FIGD2104E.
[0030] It should be noted that the correspondence between the BANK_ pin set and the physical pins of the chip is shown in the following table. The number after the suffix represents the pin set, and the English after the pin set represents the actual physical pin. For example, the BANK_227 pin set of VU37P includes eight physical pins from AN2 to AN10. At this time, the MGTYRXP0_227 (AN2) pin of the VU37P chip is connected to the MGTYTXP0_232_J9 pin of the VU13PB chip. Similarly, the MGTYRXN0_227 (AN1) pin, MGTYRXP1_227 (AN6) pin, and MGTYRXN1_227 (AN5) pin are connected to the MGTYTXN0_232_J8 pin, MGTYTXP1_232_H7 pin, and MGTYTXN1_232_H6 pin, respectively. Specifically, the pins with suffixes including 227 such as MGTYRXP0_227 (AN2), MGTYRXN0_227 (AN1), MGTYRXP1_227 (AN6) and MGTYRXN1_227 (AN5) are collectively referred to as the BANK_227 pin set of the VU37P chip, and the pins with suffixes including 232 such as MGTYTXP0_232_J9, MGTYTXN0_232_J8, MGTYTXP1_232_H7, MGTYTXN1_232_H6 are collectively referred to as the BANK_232 pin set of the VU13P chip.
[0031] Table 1 The correspondence between the BANK_ pin set and the physical pins of the chip
[0032] VU13PA VU37P VU13PB MGTYRXP0_227(AN2)MGTYRXN0_227(AN1)MGTYRXP1_227 (AN6)MGTYRXN1_227 (AN5) MGTYTXP0_232_J9MGTYTXN0_232_J8MGTYTXP1_232_H7MGTYTXN1_232_H6 MGTYTXP0_227(AP9)MGTYTXN0_227(AP8)MGTYTXP1_227(AN11)MGTYTXN1_227(AN10) MGTYRXP0_232_J4MGTYRXN0_232_J3MGTYRXP1_232_H2MGTYRXN1_232_H1 MGTYRXP0_228AL6MGTYRXN0_228AL5MGTYRXP1_228 AK4MGTYRXN1_228AK3MGTYRXP2_228 AJ2MGTYRXN2_228AJ1MGTYRXP3_228 AH4MGTYRXN3_228 AH3 MGTYTXP0_224_BF5MGTYTXN0_224_BF4MGTYTXP1_224_BD5MGTYTXN1_224_BD4MGTYTXP2_224_BB5MGTYTXN2_224_BB4MGTYTXP3_224_AV7MGTYTXN3_224_AV6 MGTYTXP0_228AK9MGTYTXN0_228AK8MGTYTXP1_228 AJ7MGTYTXN1_228AJ6MGTYTXP2_228 AJ11MGTYTXN2_228AJ10MGTYTXP3_228 AH9MGTYTXN3_228 AH8 MGTYRXP0_224_BC2MGTYRXN0_224_BC1MGTYRXP1_224_BA2MGTYRXN1_224_BA1MGTYRXP2_224_AW4MGTYRXN2_224_AW3MGTYRXP3_224_AV2MGTYRXN3_224_AV1 MGTYRXP0_229AG2MGTYRXN0_229AG1MGTYRXP1_229 AF4MGTYRXN1_229AF3MGTYRXP2_229 AE2MGTYRXN2_229AE1MGTYRXP3_229 AE6MGTYRXN3_229 AE5 MGTYTXP0_225_AU9MGTYTXN0_225_AU8MGTYTXP1_225_AT7MGTYTXN1_225_AT6MGTYTXP2_225_AR9MGTYTXN2_225_AR8MGTYTXP3_225_AP7MGTYTXN3_225_AP6 MGTYTXP0_229AG7MGTYTXN0_229AG6MGTYTXN1_229 AG10MGTYTXP1_229AG11MGTYTXN2_229 AF8MGTYTXP2_229AF9MGTYTXN3_229 AE10MGTYTXP3_229 AE11 MGTYRXP0_225_AU4MGTYRXN0_225_AU3MGTYRXP1_225_AT2MGTYRXN1_225_AT1MGTYRXP2_225_AR4MGTYRXN2_225_AR3MGTYRXP3_225_AP2MGTYRXN3_225_AP1 MGTYRXP0_230AD4MGTYRXN0_230AD3MGTYRXN1_230 AC1MGTYRXP1_230AC2MGTYRXN2_230 AC5MGTYRXP2_230AC6MGTYRXP3_230 AB4MGTYRXN3_230 AB3 MGTYTXP0_226_AN9MGTYTXN0_226_AN8MGTYTXP1_226_AM7MGTYTXN1_226_AM6MGTYTXN2_226_AL8MGTYTXP2_226_AL9MGTYTXN3_226_AK6MGTYTXP3_226_AK7 MGTYTXP0_230AD9MGTYTXN0_230AD8MGTYTXN1_230 AC10MGTYTXP1_230AC11MGTYTXN2_230 AB8MGTYTXP2_230AB9MGTYTXN3_230 AA7MGTYTXP3_230 AA6 MGTYRXP0_226_AN4MGTYRXN0_226_AN3MGTYRXP1_226_AM2MGTYRXN1_226_AM1MGTYRXP2_226_AL4MGTYRXN2_226_AL3MGTYRXP3_226_AK2MGTYRXN3_226_AK1 MGTYRXP0_231_N4MGTYRXN0_231_N3MGTYRXP1_231_M2MGTYRXN1_231_M1MGTYRXP2_231_L4MGTYRXN2_231_L3MGTYRXP3_231_K2MGTYRXN3_231_K1 MGTYTXP0_235G7MGTYTXN1_235 G6MGTYTXP1_235 E6MGTYTXN0_235 E7MGTYTXN2_235C6MGTYTXP2_235 C7MGTYTXN3_235A5MGTYTXP3_235A6 MGTYTXN0_225_AU8MGTYTXN1_225_AT6MGTYTXN2_225_AR8MGTYTXN3_225_AP6MGTYTXP0_225_AU9MGTYTXP1_225_AT7MGTYTXP2_225_AR9MGTYTXP3_225_AP7 MGTYRXP0_229MGTYRXN0_229MGTYRXN1_229MGTYRXP1_229MGTYRXN2_229MGTYRXP2_229MGTYRXN3_229MGTYRXP3_229 MGTYRXP0_225_AU4MGTYRXN0_225_AU3MGTYRXP1_225_AT2MGTYRXN1_225_AT1MGTYRXP2_225_AR4MGTYRXN2_225_AR3MGTYRXP3_225_AP2MGTYRXN3_225_AP1 MGTYTXP0_229MGTYTXN0_229MGTYTXN1_229MGTYTXP1_229MGTYTXN2_229MGTYTXP2_229MGTYTXP3_229MGTYTXN3_229 MGTYTXP0_226_AN9MGTYTXN0_226_AN8MGTYTXP1_226_AM7MGTYTXN1_226_AM6MGTYTXP2_226_AL9MGTYTXN2_226_AL8MGTYTXP3_226_AK7MGTYTXN3_226_AK6 MGTYRXP0_230MGTYRXN0_230MGTYRXN1_230MGTYRXP1_230MGTYRXN2_230MGTYRXP2_230MGTYRXN3_230MGTYRXP3_230 MGTYRXN0_226_AN3MGTYRXN1_226_AM1MGTYRXN2_226_AL3MGTYRXN3_226_AK1MGTYRXP0_226_AN4MGTYRXP1_226_AM2MGTYRXP2_226_AL4MGTYRXP3_226_AK2 MGTYTXP0_230MGTYTXN0_230MGTYTXN1_230MGTYTXP1_230MGTYTXN2_230MGTYTXP2_230MGTYTXN3_230MGTYTXP3_230 MGTYRXP0_227_AJ4MGTYRXN0_227_AJ3MGTYRXP1_227_AH2MGTYRXN1_227_AH1MGTYRXP2_227_AG4MGTYRXN2_227_AG3MGTYRXP3_227_AF2MGTYRXN3_227_AF1 MGTYTXP0_231AA11MGTYTXN0_231AA10MGTYTXN1_231 Y8MGTYTXP1_231Y9MGTYTXN2_231 W6MGTYTXP2_231W7MGTYTXP3_231 W11MGTYTXN3_231 W10 MGTYTXP0_227_AJ9MGTYTXN0_227_AJ8MGTYTXP1_227_AH7MGTYTXN1_227_AH6MGTYTXP2_227_AG9MGTYTXN2_227_AG8MGTYTXP3_227_AF7MGTYTXN3_227_AF6 MGTYRXP0_231AA2MGTYRXN0_231AA1MGTYRXN1_231 Y3MGTYRXP1_231Y4MGTYRXN2_231 W1MGTYRXP2_231W2MGTYRXN3_231 V3MGTYRXP3_231 V4 MGTYRXP0_228_AE4MGTYRXN0_228_AE3MGTYRXP1_228_AD2MGTYRXN1_228_AD1MGTYRXP2_228_AC4MGTYRXN2_228_AC3MGTYRXP3_228_AB2MGTYRXN3_228_AB1 MGTYTXP0_232V9MGTYTXN0_232 V8MGTYTXP1_232 U11MGTYTXN1_232 U10MGTYTXP2_232T9MGTYTXN2_232 T8MGTYTXP3_232R11MGTYTXN3_232 R10 MGTYTXP0_228_AE9MGTYTXN0_228_AE8MGTYTXP1_228_AD7MGTYTXN1_228_AD6MGTYTXP2_228_AC9MGTYTXN2_228_AC8MGTYTXP3_228_AB7MGTYTXN3_228_AB6 MGTYRXP0_232U2MGTYRXN0_232 U1MGTYRXP1_232 U6MGTYRXN1_232 U5MGTYRXP2_232T4MGTYRXN2_232 T3MGTYRXP3_232R2MGTYRXN3_232R1 MGTYRXP0_229_AA4MGTYRXN0_229_AA3MGTYRXP1_229_Y2MGTYRXN1_229_Y1MGTYRXP2_229_W4MGTYRXN2_229_W3MGTYRXP3_229_V2MGTYRXN3_229_V1 MGTYTXP0_233P9MGTYTXN0_233 P8MGTYTXP1_233 N7MGTYTXN1_233 N6MGTYTXP2_233N11MGTYTXN2_233 N10MGTYTXP3_233M9MGTYTXN3_233 M8 MGTYTXP0_229_AA9MGTYTXN0_229_AA8MGTYTXP1_229_Y7MGTYTXN1_229_Y6MGTYTXP2_229_W9MGTYTXN2_229_W8MGTYTXP3_229_V7MGTYTXN3_229_V6 MGTYRXP0_233R6MGTYRXN0_233 R5MGTYRXP1_233 P4MGTYRXN1_233 P3MGTYRXP2_233N2MGTYRXN2_233 N1MGTYRXP3_233M4MGTYRXN3_233 M3 MGTYRXP0_230_U4MGTYRXN0_230_U3MGTYRXP1_230_T2MGTYRXN1_230_T1MGTYRXP2_230_R4MGTYRXN2_230_R3MGTYRXP3_230_P2MGTYRXN2_230_R3 MGTYTXP0_234 L7MGTYTXN0_234 L6MGTYTXP1_234 L11MGTYTXN1_234 L10MGTYTXP2_234K8MGTYTXN2_234 K9MGTYTXP3_234J7MGTYTXN3_234 J6 MGTYTXP0_230_U9MGTYTXN0_230_U8MGTYTXP1_230_T7MGTYTXN1_230_T6MGTYTXP2_230_R9MGTYTXN2_230_R8MGTYTXP3_230_P7MGTYTXN3_230_P6 MGTYRXP0_234 L2MGTYRXN0_234 L1MGTYRXP1_234 K4MGTYRXN1_234 K3MGTYRXP2_234J2MGTYRXN2_234 J1MGTYRXP3_234H4MGTYRXN3_234 H3
[0033] Figure 2The invention also includes a power supply circuit composed of an LTM4650 chip, an LTM4644 chip, and an LTM4622 chip, wherein: a 12V input power supply is converted into a 0.85V power supply by multiple LTM4650 chips and transmitted to the INTVCC pin of the VU37P chip; the 12V input power supply is converted into 1.2V power supply, 1.0V power supply, 1.8V power supply, 1.2V power supply, 1.8V power supply, and 2.5V power supply by the LTM4644 chip and transmitted to the MGTAVTT pin, MGTAVCC pin, VCCAUX pin, VCC_HBM pin, VCC_1V8 pin, and VCCAUX_HBM pin of the VU37P chip respectively; the 12V input power supply is converted into a 0.85V power supply by multiple LTM4650 chips and transmitted to the INTVCC pin of the first VU13P chip; the 12V input The power supply is converted into 0.9V power supply and 1.2V power supply through multiple LTM4644 chips and respectively transmitted to the MGTAVCC pin and MGTAVTT pin of the first VU13P chip; the 12V input power supply is converted into 1.8V power supply through the LTM4622 chip and transmitted to the VCC1V8 pin of the first VU13P chip; the 12V input power supply is converted into 0.85V power supply through multiple LTM4650 chips and transmitted to the INTVCC pin of the second VU13P chip; the 12V input power supply is converted into 0.9V power supply and 1.2V power supply through multiple LTM4644 chips and respectively transmitted to the MGTAVCC pin and MGTAVTT pin of the second VU13P chip; the 12V input power supply is converted into 1.8V power supply through the LTM4622 chip and transmitted to the VCC1V8 pin of the second VU13P chip.
[0034] Figure 3 The JTAG debugging circuit is also included, which is composed of a switching switch and a JTAG debugging interface. The JTAG debugging interface is connected to the TDI pin, TMS pin, TCK pin and TDO pin of the VU13P chip through the switching switch. The JTAG debugging interface is connected to the TDI pin, TMS pin, TCK pin and TDO pin of the VU37P chip through the switching switch.
[0035] In actual operation, the heterogeneous acceleration card loads three high-performance FPGAs on the same hardware board, and uses high-speed hardware circuit design technology to achieve the function of high-speed interconnection of multiple on-board chips. At the same time, one interface can be used to complete the configuration of multiple FPGAs. The total on-chip integrated memory of the acceleration card can reach 500Mb, and the high-bandwidth memory can reach 16GB. It also supports PCIe 4th generation and transceivers with speeds up to 32.75Gb / s. In addition, the heterogeneous acceleration card is an FPGA PCI-Express v3.0 x16 acceleration computing card developed based on Xilinx UltraScale's 16 nm VU37P chip and two VU13P chip solutions. The heterogeneous acceleration card has high throughput, low-latency network processing capabilities and the ability to assist the CPU in unloading network functions, saving CPU computing power, reducing CPU occupancy and also reducing power consumption.
[0036] like Figures 6 to 8 As shown, it also includes a heat sink 1, a cover plate 2, and a circuit board 3 for mounting a chip, wherein: the heat sink 1 is a rectangular structure, a plurality of heat dissipation teeth 101 are evenly cut out on the four sides of the heat sink 1, a mounting cavity 102 is arranged in the middle of the heat sink 1, X-shaped connecting arms 103 are arranged at the four corners of the heat sink 1, and connecting holes 104 are arranged at the ends of the X-shaped connecting arms 103, and arc-shaped tooth roots 105 are formed at the positions where the heat dissipation teeth 101 contact the X-shaped connecting arms 103; the cover plate 2 is composed of a cover body 201 and a plurality of mounting ears 202, and the circuit board 3 is mounted in a cavity formed by the cover plate 2 and the mounting cavity 102.
[0037] Specifically, a sealing ring 106 is provided between the cover plate 2 and the installation cavity 102. One or more circular bottom cavities 107 are provided at the bottom of the heat sink 1. A tooth stand 108 is provided at the portion where the circular bottom cavity 107 overlaps with the heat sink tooth 101 to ensure that the bottom of the circular bottom cavity 107 is flat. A heat sink fan 109 is installed in the circular bottom cavity 107. A side opening 110 is provided on the side of the heat sink 1, and a plurality of interfaces 111 are installed on the side opening 110.
[0038] In actual application, the heat sink of the heterogeneous accelerator card is made of heat-conducting metal material, and heat-dissipating teeth are designed on the entire side. The heat-dissipating teeth around and the cooling fan at the bottom can effectively reduce the temperature of the accelerator card. In particular, the circular bottom cavity at the bottom and the heat-dissipating teeth adopt a coincident layout scheme, which can accelerate the gas flow between the heat-dissipating teeth as much as possible. The design scheme of the arc-shaped tooth root can greatly reduce the wall thickness and improve the thermal conductivity.
[0039] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the utility model, rather than to limit it. Although the utility model has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the various embodiments of the utility model.
Claims
1. A three-chip FPGA heterogeneous accelerator card, characterized in that: It includes a VU37P chip and two VU13P chips, wherein the first VU13P chip and the second VU13P chip are respectively arranged on both sides of the VU37P chip, wherein: The BANK_127, BANK_128, BANK_129, BANK_130, BANK_131, BANK_132, BANK_133, BANK_134, and BANK_135 pin sets of the VU37P chip are respectively connected to the BANK_232, BANK_224, BANK_225, BANK_226, BANK_227, BANK_228, BANK_229, BANK_230, and BANK_231 pin sets of the first VU13P chip; The BANK_227, BANK_228, BANK_229, BANK_330, BANK_331, BANK_332, BANK_333, BANK_342, and BANK_335 pin sets of the VU37P chip are respectively connected to the BANK_232, BANK_231, BANK_230, BANK_229, BANK_228, BANK_227, BANK_226, BANK_225, and BANK_224 pin sets of the second VU13P chip; The BANK_224 pin set of the VU37P chip is connected to the PCIE bus pins.
2. The three-chip FPGA heterogeneous acceleration card according to claim 1, characterized in that: It also includes a power supply circuit composed of an LTM4650 chip, an LTM4644 chip, and an LTM4622 chip, wherein: The 12V input power is converted into 0.85V power through multiple LTM4650 chips and sent to the INTVCC pin of the VU37P chip; the 12V input power is converted into 1.2V power, 1.0V power, 1.8V power, 1.2V power, 1.8V power and 2.5V power through the LTM4644 chip and sent to the MGTAVTT pin, MGTAVCC pin, VCCAUX pin, VCC_HBM pin, VCC_1V8 pin, VCCAUX_HBM pin of the VU37P chip respectively; The 12V input power is converted into 0.85V power through multiple LTM4650 chips and delivered to the INTVCC pin of the first VU13P chip; the 12V input power is converted into 0.9V power and 1.2V power through multiple LTM4644 chips and delivered to the MGTAVCC pin and MGTAVTT pin of the first VU13P chip respectively; the 12V input power is converted into 1.8V power through the LTM4622 chip and delivered to the VCC1V8 pin of the first VU13P chip; The 12V input power supply is converted into a 0.85V power supply through multiple LTM4650 chips and delivered to the INTVCC pin of the second VU13P chip; the 12V input power supply is converted into a 0.9V power supply and a 1.2V power supply through multiple LTM4644 chips and delivered to the MGTAVCC pin and the MGTAVTT pin of the second VU13P chip respectively; the 12V input power supply is converted into a 1.8V power supply through the LTM4622 chip and delivered to the VCC1V8 pin of the second VU13P chip.
3. The three-chip FPGA heterogeneous acceleration card according to claim 1, characterized in that: It also includes a JTAG debugging circuit consisting of a switching switch and a JTAG debugging interface, wherein the JTAG debugging interface is connected to the TDI pin, TMS pin, TCK pin and TDO pin of the VU13P chip through the switching switch, and the JTAG debugging interface is connected to the TDI pin, TMS pin, TCK pin and TDO pin of the VU37P chip through the switching switch.
4. The three-chip FPGA heterogeneous acceleration card according to claim 1, characterized in that: It also includes a heat sink (1), a cover plate (2), and a circuit board (3) for mounting the chip, wherein: The heat sink (1) is a rectangular parallelepiped structure, a plurality of heat dissipation teeth (101) are evenly cut out on four sides of the heat sink (1), a mounting cavity (102) is provided in the middle of the heat sink (1), X-shaped connecting arms (103) are provided at four corners of the heat sink (1), connecting holes (104) are provided at the ends of the X-shaped connecting arms (103), and arc-shaped tooth roots (105) are formed at the positions where the heat dissipation teeth (101) contact the X-shaped connecting arms (103); the cover plate (2) is composed of a cover body (201) and a plurality of mounting ears (202), and the circuit board (3) is mounted in a cavity formed by the cover plate (2) and the mounting cavity (102).
5. The three-chip FPGA heterogeneous acceleration card according to claim 4, characterized in that: A sealing ring (106) is provided between the cover plate (2) and the installation cavity (102).
6. The three-chip FPGA heterogeneous acceleration card according to claim 4, characterized in that: One or more circular bottom cavities (107) are provided at the bottom of the heat sink (1), and a tooth platform (108) is provided at the portion where the circular bottom cavity (107) overlaps with the heat dissipation teeth (101) to ensure that the bottom of the circular bottom cavity (107) is flat, and a heat dissipation fan (109) is installed in the circular bottom cavity (107).
7. The three-chip FPGA heterogeneous acceleration card according to claim 4, characterized in that: A side opening (110) is provided on the side of the heat dissipation seat (1), and a plurality of interfaces (111) are installed on the side opening (110).