A new structure for reading EDID display information of VGA interface

Abstract

The utility model discloses a novel EDID display information reading structure of a VGA interface. A controllable signal channel switch is arranged between the VGA interface of a display driver card and the DC load resistor on the RGB signal channel. When the controllable signal channel switch is turned on, it is controlled by the display driver card MCU, and the EDID information is stored in the display driver card MCU. The reading structure ensures the rationality, reliability and stability of the VGA display in access identification and EDID information reading.

Description

Technical Field

[0001] The utility model relates to the technical field of display, in particular to a novel EDID display information reading structure of a VGA interface. Background Art

[0002] EDID: Extended Display Identification Data is a VESA (Video Electronics Standards Association) standard data format that contains parameters about the display and its performance, including vendor information, maximum image size, color settings, factory presets, frequency range limits, and strings of the display name and serial number. The host device "knows" some of the display's properties by reading the EDID data in the display. In short, EDID is a nameplate for the display, and EDID data is usually transmitted by a direct digital control system channel.

[0003] VGA: Video Graphics Array, a special interface for computers to output data using the VGA standard. The VGA interface has 15 pins in 3 rows, with 5 holes in each row. It is the most widely used interface type on graphics cards, and most graphics cards have this interface. It transmits red, green, and blue analog signals as well as synchronization signals (horizontal and vertical signals).

[0004] The principle of computer identification of VGA monitor: There is a monitor driver board inside the VGA monitor. The driver board provides a 75Ω DC load on the VGA RGB signal connection circuit, and the computer host also has a 75Ω source-end DC load. When the VGA monitor is not connected, the DC load on the computer host is 75Ω. At this time, the computer host recognizes that the VGA monitor is not connected. When the VGA monitor is connected, the load on the VGA RGB signal connection circuit becomes a 75Ω load on the computer host and a 75Ω load on the VGA video signal driver board in parallel, that is, 37.5Ω. The VGA driver source on the computer host outputs a detection pulse current. Since the DC load is doubled when the VGA monitor is connected and not connected, the voltage generated by the same intensity of the detection pulse current passing through the DC load is also doubled. The VGA driver source detects this voltage to identify whether the monitor is connected. When the computer host recognizes that a VGA monitor is connected, the computer host will read the VGA interface EDID information of the VGA monitor display driver board through the I2C channel on the VGA interface, and then output the corresponding configured VGA display signal to the VGA monitor based on the EDID information, so that the VGA monitor can display the appropriate picture.

[0005] Correct reading of EDID information is crucial for the host computer to output the correct display signal. Currently, there are two main schemes for the EDID information reading design of mainstream VGA monitors: Scheme 1 is to store EDID information in an EEPROM chip, which is placed at the VGA interface of the monitor driver card and powered by the 5V of the VGA interface. When the host computer recognizes that a VGA monitor is connected, the host can read the EDID information in the EEPROM through the I2C data channel in the VGA line, thereby sending the correct display signal to the VGA monitor.

[0006] Compared with Solution 1, Solution 2 cancels the electrically erasable programmable read-only memory (EEPROM) chip at the VGA interface of the display driver card and adopts the display driver card MCU with better stability to save EDID information. The design process is similar to Solution 1, and the EDID information storage chip is replaced from the electrically erasable programmable read-only memory (EEPROM) to the MCU.

[0007] It can be seen that there are obvious problems in the existing technology: Solution 1 has three problems: First, the EEPROM that stores EDID information at the VGA interface is susceptible to voltage fluctuations, external ambient temperature, static electricity, electromagnetic fields and other factors, causing abnormal operation or damage, resulting in host EDID information reading errors. Second, the EEPROM chip at the VGA interface of the display is powered by the computer host's VGA 5V after it is inserted into the display through the VGA cable. Because the computer host starts to read the EDID information after recognizing that the VGA display is connected, it is easy for the host to recognize that the VGA display is connected and start reading EDID during the process of inserting the VGA cable into the display, and then the host's VGA 5V supplies power to the EEPROM. In this way, the host EDID information reading error will be caused because the EEPROM chip has not yet stabilized. Third, when the VGA of the computer host is connected to a monitor without power supply, because the computer host recognizes that the VGA monitor is connected, the graphics card will output the corresponding VGA signal. If the computer host is also connected to other monitors at this time, you will see that there will be two monitors in the display configuration (either in copy mode or extension mode), and sometimes the resolution will change. As long as the VGA of the computer host is connected to the VGA monitor, the VGA of the computer host will output the display signal regardless of whether the monitor is working properly. Obviously, this is unreasonable. Similarly, there will be no such problem for display signal interfaces such as HDMI, DP, and DVI.

[0008] Compared with Solution 1, Solution 2 uses a display driver card MCU with better stability to store EDID information, which greatly reduces the risk of EEPROM losing EDID information. However, because EDID is stored in the display driver card MCU, the display driver card MCU must be allowed to work normally before the computer host can read the correct VGA display EDID information. If the display VGA signal is plugged in first and then the display is powered on, the computer host will detect that the VGA display is connected and read the EDID information. There will be an EDID information reading error due to the display driver card MCU not working properly, so that the host outputs a signal that does not match the display. In addition, this solution still has the third problem in Solution 1, that is, when the VGA of the computer host is connected to a display without power supply, because the computer host recognizes that the VGA display is connected, the graphics card will output the corresponding VGA signal. As long as the VGA of the computer host is connected to the VGA display, regardless of whether the display is working properly, the VGA of the computer host will output the display signal, which is obviously unreasonable. Utility Model Content

[0009] The purpose of the utility model is to solve the above problems existing in the existing VGA display EDID reading technology, and to provide a novel VGA interface EDID display information reading structure, which ensures the rationality, reliability and stability of VGA display access identification and EDID information reading.

[0010] In order to achieve the above purpose, the utility model adopts the following technical solutions:

[0011] A novel EDID display information reading structure for a VGA interface is characterized in that a controllable signal channel switch is arranged between the VGA interface of a display driver card and the DC load resistor on an RGB signal channel. When the controllable signal channel switch is turned on, it is controlled by the display driver card MCU, and the EDID information is stored in the display driver card MCU.

[0012] The controllable signal channel switch is a TS5V522C chip, and the controllable signal channel switch is arranged between the VGA interface of the display driver card and the 75Ω DC load resistor.

[0013] The output pins AR, AG and AB of the controllable signal channel switch are connected to the signal channel 75Ω DC load resistor.

[0014] The RGB signals of the VGA interface of the display driver card are respectively connected to the input pins 1R, 1G and 1B of the controllable signal channel switch.

[0015] The conduction and disconnection of the pins 1R to AR, 1G to AG, and 1B to AB of the TS5V522C chip are controlled by the OE pin of the TS5V522C chip.

[0016] When the pin OE of the TS5V522C chip is at a high level, the signal channel of the TS5V522C is in a disconnected state, and when OE is at a low level, it is in a conductive state.

[0017] The power supply pin of the TS5V522C chip is connected to the display driver card. When the TS5V522C chip is not powered, the switch channel is in a high-impedance state and the signal is not conducted.

[0018] When the display driver card MCU works normally, the pin SEL of the TS5V522C chip is at a low level, 1R to AR, 1G to AG, and 1B to AB are turned on.

[0019] When the controllable signal channel switch is turned on, the VGA cable of the computer host is plugged into the VGA display, and the computer host reads the EDID information in the display driver card MCU through the I2C bus.

[0020] The controllable signal channel switch is reserved with a 0Ω connection resistor, and the VGA interface of the display driver card is reserved with an electrically erasable programmable read-only memory EEPROM for storing EDID information.

[0021] The advantages of adopting the utility model are:

[0022] 1. The EDID information of the VGA display is stored in the display driver card MCU with better stability, which greatly reduces the risk of losing EDID information in the EEPROM chip.

[0023] 2. When the VGA monitor is not working properly without power supply, the host computer will recognize the VGA monitor after connecting to the monitor VGA interface, read the EDID information, and output the VGA signal. At this time, if the host computer is connected to one and only one other normally working monitor, the system will not connect two monitors in copy or extension mode.

[0024] 3. When a VGA monitor loses power, it can release the VGA bus connected to the monitor by the host computer, turn off the VGA signal output, and wait until the monitor is powered on and works normally next time, re-identify the VGA access and read the EDID information. The entire EDID information reading logic is reasonable. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 A VGA interface circuit diagram for implementing the utility model design;

[0026] Figure 2A logic truth table diagram of a VGA controllable signal connection switch used to implement the design of the utility model;

[0027] Figure 3 A pin definition diagram of the VGA controllable signal connection switch used to implement the design of the utility model;

[0028] Figure 4 The present invention is a design diagram for reading the EDID display information of the VGA interface used to implement the design of the present invention.

[0029] The following are marked in the figure: 1. Controllable signal channel switch, 2. Display driver card VGA interface, 3. RGB signal channel, 4. Switch conduction direction selection control, 5. Power pin, 6. On / off control signal, 7. DC load resistor, 8. RGB signal connected to the display driver card MCU, 9. Electrically erasable programmable read-only memory EEPROM, 10. I2C bus. DETAILED DESCRIPTION

[0030] Example 1

[0031] This embodiment further illustrates the structure and principle of the utility model in conjunction with the accompanying drawings

[0032] A novel EDID display information reading structure of a VGA interface is provided. A controllable signal channel switch 1 is arranged between a VGA interface 2 of a display driver card and a DC load resistor 7 on an RGB signal channel 3. When the controllable signal channel switch 1 is turned on, it is controlled by an MCU of the display driver card, and the EDID information is stored in the MCU of the display driver card.

[0033] In this embodiment, the controllable signal channel switch 1 is a TS5V522C chip, and the controllable signal channel switch 1 is arranged between the display driver card VGA interface 2 and the 75Ω DC load resistor 7 .

[0034] In this embodiment, the output pins AR, AG and AB of the controllable signal channel switch 1 are connected to the signal channel 75Ω DC load resistor 7 .

[0035] In this embodiment, the RGB signals of the VGA interface 2 of the display driver card are respectively connected to the input pins 1R, 1G and 1B of the controllable signal channel switch 1.

[0036] In this embodiment, the conduction and disconnection of the pins 1R to AR, 1G to AG, and 1B to AB of the TS5V522C chip are controlled by the OE pin of the TS5V522C chip.

[0037] In this embodiment, when the pin OE of the TS5V522C chip is at a high level, the signal channel of the TS5V522C is in a disconnected state, and when OE is at a low level, it is in a conductive state.

[0038] In this embodiment, the power supply pin of the TS5V522C chip is connected to the display driver card. When the TS5V522C chip is not powered, the switch channel is in a high-impedance state and the signal is not conducted.

[0039] In this embodiment, when the RGB signal 8 of the display driver card MCU works normally, the pin SEL of the TS5V522C chip is at a low level, 1R to AR, 1G to AG, and 1B to AB are turned on.

[0040] In this embodiment, when the controllable signal channel switch 1 is turned on, the VGA cable of the computer host is plugged into the VGA display, and the computer host reads the EDID information in the RGB signal 8 of the display driver card MCU through the I2C bus 10.

[0041] In this embodiment, the controllable signal channel switch 1 is reserved with a 0Ω connection resistor, and the VGA interface of the display driver card is reserved with an electrically erasable programmable read-only memory EEPROM 9 for storing EDID information.

[0042] Example 2

[0043] like Figure 1-3 As shown, an RGB controllable signal channel switch 1 is added to the VGA interface of the display driver card, and the TS5V522C chip is selected. The chip is dedicated to the VGA video signal exchange switch, has a high bandwidth of 380MHz, which is sufficient to meet the VGA signal transmission bandwidth (about 162MHz), supports near-zero propagation delay, and can bring the VGA analog signal to the target location with less distortion. A 2:2 dual-graphics crossover solution can be provided for the VGA signal switch. The chip supports the switch of 2 VGA signal sources, and can direct the signal to one of the two destinations in a laptop. The utility model design does not use the 2:2 dual-graphics crossover function of the TS5V522C chip, but only uses the unidirectional RGB controllable signal switch conduction control function of this chip.

[0044] The implementation circuit design of the utility model is as follows Figure 1 As shown, Figure 1 1 is a controllable signal channel switch, which is a TS5V522C chip, 2 is a display driver card VGA interface, and 7 is a 75Ω DC load resistor on the display driver card RGB signal channel. The DC load resistor 7 is provided for the computer host to detect the load connected to the VGA display. The controllable signal channel switch is placed between the display driver card VGA interface and the 75Ω DC load resistor. The RGB signals of the VGA interface are connected to the 1R, 1G, and 1B input pins of the controllable switch respectively. Figure 1As shown in 3 (the 0Ω resistor on the RGB signal channel is a reserved design for compatibility with the traditional EDID information reading of VGA), then the AR, AG, and AB pins of the controllable signal channel switch are connected to the 75Ω DC load resistor of the signal channel as outputs. The conduction and disconnection of 1R to AR, 1G to AG, and 1B to AB of the TS5V522C chip are controlled by the OE pin of the chip. 6 is the conduction and shutdown control signal of the TS5V522C chip, which is generated by the display driver card MCU. When the OE pin is high, the signal channel of the TS5V522C chip is in a high-impedance state, that is, disconnected, and low level is in a conducting state. 4 is the switch conduction direction selection control of the TS5V522C chip, and the SEL pin realizes the signal cross output function. The design of the utility model does not use the signal cross function of the chip, but is only used for unidirectional conduction and disconnection of the signal. Therefore, after the display driver card MCU works normally, SEL is low, that is, 1R to AR, 1G to AG, and 1B to AB are conducting. 5 is the power pin of the TS5V522C chip. The power is provided by the display driver card. When the TS5V522C chip is not powered, the switch channel is in a high-impedance state and the signal is not conductive. 8 is the display signal connected to the MCU end of the display driver card, and after conversion, it is displayed on the display panel. 9 is the electrically erasable programmable read-only memory EEPROM that stores EDID information. This is a reserved design for the purpose of making the design of this utility model compatible with the traditional EDID information reading design. 10 is the I2C bus connected to the MCU end of the display driver card. The design of this utility model stores the EDID information in the display driver card MCU to improve the stability and reliability of EDID data storage.

[0045] The design of the utility model is that when the display is not powered on, that is, the display driver card MCU is not powered on and working, the TS5V522C chip is in a high-impedance state, that is, disconnected. At this time, after the VGA cable of the computer host is inserted into the VGA display, the computer host will not judge that the VGA is connected, and will not read the EDID information in the display driver card MCU. When the display is powered on, that is, the display driver card is powered on, but the display driver card MCU is not working properly, the display driver card MCU will not output the enable control OE pin signal, that is, the TS5V522C chip is in a high-impedance state, that is, disconnected. After the VGA cable of the computer host is inserted into the VGA display, the computer host will not judge that the VGA is connected, and will not read the EDID information in the display driver card MCU. When the display is powered on and works normally, that is, the display driver card MCU is powered on and works normally, the display driver card MCU outputs the enable control signal OE to turn on the signal channel switch. At this time, after the VGA cable of the computer host is inserted into the VGA display, the computer host judges that the VGA is connected, and then reads the EDID information in the display driver card MCU through the I2C bus. When the monitor is powered off, the TS5V522C chip is in a high-impedance state, i.e. disconnected. The host computer will recognize that the VGA is not connected and turn off the VGA signal output.

[0046] Example 3

[0047] like Figure 4 As shown, since the computer host's access identification to the VGA monitor is achieved by using the monitor driver board to provide a 75Ω DC load resistor on the VGA RGB signal channel, a controllable signal channel switch is added between the VGA interface of the monitor driver card and the 75Ω DC load resistor on the RGB signal channel. The conduction status of the switch is controlled by the display driver card MCU, and the EDID information is stored in the display driver card MCU.

[0048] When the monitor is not powered on, that is, the MCU of the monitor driver card is not working, the RGB controllable signal channel switch at the VGA interface is in the off state. At this time, connect the VGA of the computer host to the VGA interface of the monitor. Since the RGB signal channel of the monitor driver card is in the off state, it cannot provide a 75Ω DC load resistor to the computer host graphics card for VGA monitor access identification. The computer host will think that there is no VGA monitor connected, so it will not read the monitor EDID information through the I2C bus channel, and will not output signals to the VGA monitor.

[0049] When the VGA display is powered on and the display driver card MCU works normally, it sends a control signal through the display driver card MCU to turn on the RGB controllable signal channel switch at the display driver card VGA interface. At this time, connect the VGA of the computer host to the display VGA interface. Since the RGB controllable signal channel of the display driver card is connected, it provides a 75Ω DC load to the computer host graphics card for VGA display access identification. The computer host will think that there is a VGA display connected, and thus read the EDID information in the display driver card MCU through the I2C bus channel, and output the corresponding signal to the VGA display according to the EDID information configuration.

[0050] When the VGA monitor loses power, the monitor driver card MCU does not work. At this time, the RGB controllable signal channel switch at the VGA interface of the display driver card will become disconnected again. The computer host detects that the VGA monitor is disconnected and turns off the VGA signal.

[0051] Through the design of the utility model, the access detection and reading of EDID information of the VGA interface of the display driver card become more reasonable like HDMI, DP and DVI interfaces.

Claims

1. A novel EDID display information reading structure for a VGA interface, characterized in that: A controllable signal channel switch (1) is provided between a VGA interface (2) of a display driver card and a DC load resistor (7) on an RGB signal channel (3); when the controllable signal channel switch (1) is turned on, it is controlled by an MCU of the display driver card, and EDID information is stored in the MCU of the display driver card.

2. According to the novel EDID display information reading structure of VGA interface described in claim 1, it is characterized by: The controllable signal channel switch (1) is a TS5V522C chip, and the controllable signal channel switch (1) is arranged between a display driver card VGA interface (2) and a 75Ω DC load resistor (7).

3. According to the novel EDID display information reading structure of VGA interface of claim 1, it is characterized by: The output pins AR, AG and AB of the controllable signal channel switch (1) are connected to the signal channel 75Ω DC load resistor (7).

4. According to the novel EDID display information reading structure of VGA interface of claim 3, it is characterized by: The RGB signals of the VGA interface (2) of the display driver card are respectively connected to the input pins 1R, 1G and 1B of the controllable signal channel switch (1).

5. According to the novel VGA interface EDID display information reading structure of claim 3, it is characterized by: The conduction and disconnection of the pins 1R to AR, 1G to AG, and 1B to AB of the TS5V522C chip are controlled by the OE pin of the TS5V522C chip.

6. The novel EDID display information reading structure of the VGA interface according to claim 5, characterized in that: When the pin OE of the TS5V522C chip is at a high level, the signal channel of the TS5V522C is in a disconnected state, and when OE is at a low level, it is in a conductive state.

7. The novel EDID display information reading structure of the VGA interface according to claim 6, characterized in that: The power supply pin of the TS5V522C chip is connected to the display driver card. When the TS5V522C chip is not powered, the switch channel is in a high-impedance state and the signal is not conducted.

8. The novel EDID display information reading structure of VGA interface according to claim 7, characterized in that: When the display driver card MCU works normally, the pin SEL of the TS5V522C chip is at a low level, 1R to AR, 1G to AG, and 1B to AB are turned on.

9. The novel EDID display information reading structure of VGA interface according to claim 8, characterized in that: When the controllable signal channel switch (1) is turned on, the VGA cable of the computer host is plugged into the VGA display, and the computer host reads the EDID information in the display driver card MCU through the I2C bus (10).

10. The novel EDID display information reading structure of VGA interface according to claim 9, characterized in that: The controllable signal channel switch (1) is reserved with a 0Ω connection resistor, and the VGA interface of the display driver card is reserved with an electrically erasable programmable read-only memory (EEPROM) (9) for storing EDID information.

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