Oscillator circuit with start-up circuit and comparison voltage

Abstract

The utility model belongs to the technical field of oscillator circuits, and specifically discloses an oscillator circuit with a start-up circuit and a comparison voltage, including a start-up circuit, a reference voltage generating circuit and an oscillator core circuit, wherein the start-up circuit can not only generate a signal to get the RS latch out of the metastable state, but also provide a reference current to provide a basis for the normal operation of the remaining parts; the reference voltage generating circuit adopts a method of generating voltage by current flowing through a resistor to obtain a higher reference voltage VH and a lower reference voltage VL; the oscillator core circuit mainly includes two comparators, an RS latch and a current capacitor charging and discharging circuit. The utility model can simplify circuit design, improve circuit integration, reduce chip area, and improve the reliability of the start-up circuit, thereby having obvious advantages. The utility model is suitable for the design of oscillator circuits.

Description

Technical Field

[0001] The utility model belongs to the technical field of oscillator circuits and relates to an oscillator circuit with a starting circuit and a comparison voltage. Background Art

[0002] As the requirements for high performance, miniaturization and low power consumption of various electronic equipment used in military and civilian fields become increasingly higher, people's performance requirements for integrated circuits are also constantly increasing.

[0003] In the field of electronic circuits, an oscillator is a circuit that generates a periodic signal and is commonly used in various electronic devices such as wireless communications, computers, and audio equipment. Oscillators using RS latch structures usually need to get rid of the metastable point, otherwise the circuit will not oscillate normally. In order to achieve the above purpose, an external power supply or other signal source is usually used to stimulate the oscillator to start. At the same time, because it needs to be compared with a reference voltage, a reference voltage circuit is introduced to generate a reference voltage.

[0004] The above circuit design method requires additional external components and circuit connections, which not only increases the complexity and area of ​​the circuit, but also is not conducive to the miniaturization of the overall integration and increases the design cost. Summary of the invention

[0005] The purpose of the utility model is to provide an oscillator circuit with a start-up circuit and a comparison voltage, so as to simplify the overall design of the circuit, improve the integration of the circuit and reduce the chip area.

[0006] In order to achieve the above-mentioned purpose, the technical scheme adopted by the utility model is as follows:

[0007] An oscillator circuit with a start-up circuit and a comparison voltage comprises a start-up circuit, a reference voltage generating circuit and an oscillator core circuit;

[0008] Wherein, the starting circuit includes a reference current generating branch and an excitation signal generating branch, the reference current generating branch includes a first enable input terminal and a second enable input terminal, the first enable input terminal inputs a high level, and the second enable input terminal inputs a low level, the output terminal of the reference current generating branch serves as a reference current output terminal of the starting circuit on the one hand, and is connected to the input terminal of the excitation signal generating branch on the other hand; the output terminal of the excitation signal generating branch serves as an excitation signal output terminal of the starting circuit;

[0009] The reference voltage generating circuit comprises a high level reference branch and a low level reference branch, the input end of the high level reference branch and the input end of the low level reference branch are both connected to the reference current output end of the start-up circuit; the output end of the high level reference branch serves as the first reference voltage output end of the reference voltage generating circuit, and the output end of the low level reference branch serves as the second reference voltage output end of the reference voltage generating circuit;

[0010] The oscillator core circuit includes a current capacitor charging and discharging branch, a comparator branch and a latch branch;

[0011] The current capacitor charge and discharge branch includes an input end, an output end, a first control signal input end, a second control signal input end, and an enable signal input end. The input end of the current capacitor charge and discharge branch is connected to the reference current output end of the startup circuit; the comparator branch includes a first positive input end, a first negative input end, a first output end, a second positive input end, a second negative input end, and a second output end. The first positive input end of the comparator branch and the second negative input end of the comparator branch are both connected to the output end of the current capacitor charge and discharge branch. The first negative input end of the comparator branch is connected to the first reference voltage output end of the reference voltage generating circuit, and the second positive input end of the comparator branch is connected to the second reference voltage output end of the reference voltage generating circuit; the enable signal input end of the current capacitor charge and discharge branch is connected to the second enable input end of the startup circuit;

[0012] The latch branch includes an excitation signal input terminal, a reset signal input terminal, a set signal input terminal, a first output terminal, and a second output terminal. The excitation signal input terminal of the latch branch is connected to the excitation signal output terminal of the start-up circuit, the reset signal input terminal of the latch branch is connected to the first output terminal of the comparator branch, the set signal input terminal of the latch branch is connected to the second output terminal of the comparator branch, and the first output terminal and the second output terminal of the latch branch serve as output terminals of an oscillator circuit with a start-up circuit and a comparison voltage.

[0013] The first output end of the latch branch is connected to the first control signal input end of the current capacitor charging and discharging branch, and the second output end of the latch branch is connected to the second control signal input end of the current capacitor charging and discharging branch.

[0014] As a limitation, the reference current generating branch includes a zeroth MOS tube, a first MOS tube, a second MOS tube, a fourth MOS tube, a fifth MOS tube, a sixth MOS tube, an eighth MOS tube, a ninth MOS tube, a tenth MOS tube and a first resistor; the excitation signal generating branch includes a third MOS tube, a seventh MOS tube and a second resistor;

[0015] The gate of the zeroth MOS transistor serves as the first enable input terminal of the reference current generating branch, and the gate of the eighth MOS transistor serves as the second enable input terminal of the reference current generating branch;

[0016] The source of the eighth MOS tube is grounded, and the drain of the eighth MOS tube is respectively connected to the drain of the ninth MOS tube, the gate and drain of the ninth MOS tube, the drain of the sixth MOS tube, the drain of the seventh MOS tube, and the gate of the first MOS tube; the source of the ninth MOS tube is respectively connected to the drain and gate of the tenth MOS tube, and the source of the tenth MOS tube is grounded; the source of the first MOS tube is grounded through the first resistor, and the drain of the first MOS tube is respectively connected to the gate and drain of the second MOS tube, the gate of the third MOS tube, the gate of the seventh MOS tube, and the drain of the fourth MOS tube; the source of the second MOS tube, the source of the third MOS tube, the source of the fourth MOS tube, the source of the fifth MOS tube, the source of the sixth MOS tube, and the source of the seventh MOS tube are all connected to the voltage VDD; the gate of the fourth MOS tube is connected to the gate of the fifth MOS tube; the drain of the fifth MOS tube is connected to the gate of the sixth MOS tube and the drain of the third MOS tube on the one hand, and is connected to the drain of the zeroth MOS tube through the second resistor on the other hand; the source of the zeroth MOS tube is grounded;

[0017] The common end of the gate and drain of the second MOS tube serves as the reference current output end of the startup circuit, and the common end of the drain of the third MOS tube and the second resistor serves as the excitation signal output end of the startup circuit.

[0018] As a further limitation, the high-level reference branch includes an eleventh MOS transistor and a third resistor, and the low-level reference branch includes a twelfth MOS transistor and a fourth resistor;

[0019] The source of the eleventh MOS tube and the source of the twelfth MOS tube are both connected to the voltage VDD, the gate of the eleventh MOS tube is connected to the gate of the twelfth MOS tube, the drain of the eleventh MOS tube is grounded through the third resistor, and the drain of the twelfth MOS tube is grounded through the fourth resistor;

[0020] The gate of the eleventh MOS tube serves as the input end of the high-level reference branch, and the gate of the twelfth MOS tube serves as the input end of the low-level reference branch; the drain of the eleventh MOS tube and the common end of the third resistor serve as the first reference voltage output end of the reference voltage generating circuit; the drain of the twelfth MOS tube and the common end of the fourth resistor serve as the second reference voltage output end of the reference voltage generating circuit.

[0021] As a further limitation, the current-capacitance charge-discharge branch includes a thirteenth MOS transistor to a twenty-first MOS transistor and a first capacitor;

[0022] The source of the thirteenth MOS tube, the source of the fourteenth MOS tube, and the drain of the nineteenth MOS tube are all connected to the voltage VDD; the gate of the thirteenth MOS tube and the gate of the fourteenth MOS tube are connected together as the input end of the current capacitor charging and discharging branch;

[0023] The drain of the thirteenth MOS tube is connected to the drain of the sixteenth MOS tube and the gate of the sixteenth MOS tube respectively, and the source of the sixteenth MOS tube is grounded; the gate of the sixteenth MOS tube is connected to the gate of the seventeenth MOS tube and the drain of the fifteenth MOS tube respectively, and the source of the fifteenth MOS tube is grounded, and the gate of the fifteenth MOS tube serves as the enable signal input terminal of the current capacitor charge and discharge branch; the source of the seventeenth MOS tube is grounded, and the drain of the seventeenth MOS tube is connected to the source of the nineteenth MOS tube and the source of the twenty-first MOS tube respectively; the gate of the nineteenth MOS tube is connected to the gate of the seventeenth MOS tube and the drain of the fifteenth MOS tube respectively; The gate of the 20th MOS tube is connected to the gate of the 21st MOS tube, serving as the first control signal input end of the current capacitor charging and discharging branch; the drain of the 18th MOS tube is grounded, the source of the 18th MOS tube is connected to the drain of the 14th MOS tube and the source of the 20th MOS tube respectively, and the gate of the 20th MOS tube is connected to the gate of the 21st MOS tube, serving as the second control signal input end of the current capacitor charging and discharging branch; the drain of the 20th MOS tube is connected to the drain of the 21st MOS tube and is grounded through the first capacitor, and the common end of the three serves as the output end of the current capacitor charging and discharging branch.

[0024] As yet further defined, the comparator branch includes a first comparator and a second comparator;

[0025] The non-inverting input terminal of the first comparator serves as the first non-inverting input terminal of the comparator branch, the inverting input terminal of the first comparator serves as the first inverting input terminal of the comparator branch, and the output terminal of the first comparator serves as the first output terminal of the comparator branch;

[0026] The non-inverting input terminal of the second comparator serves as the second non-inverting input terminal of the comparator branch, the inverting input terminal of the second comparator serves as the second inverting input terminal of the comparator branch, and the output terminal of the second comparator serves as the second output terminal of the comparator branch.

[0027] As a further limitation, the latch branch includes a twenty-second MOS transistor and an RS latch;

[0028] The source of the twenty-second MOS tube is connected to the voltage VDD, and the gate of the twenty-second MOS tube serves as the excitation signal input terminal of the latch branch; the drain of the twenty-second MOS tube is connected to the reset terminal of the RS latch, serving as the reset signal input terminal of the latch branch, the set terminal of the RS latch serves as the set signal input terminal of the latch branch, the positive phase output terminal of the RS latch serves as the first output terminal of the latch branch, and the negative phase output terminal of the RS latch serves as the second output terminal of the latch branch.

[0029] As the utility model adopts the above technical solution, compared with the prior art, the technical progress achieved is:

[0030] (1) The utility model reduces the chip area while ensuring the oscillation accuracy, improves the circuit integration and reliability, has a simple circuit structure, a small chip area, and is conducive to the control of design costs;

[0031] (2) The utility model can be used in other chip circuits or as an oscillator alone;

[0032] (3) In the present invention, the startup circuit is directly integrated into the oscillator and is not affected by the interference or instability of the external circuit, thereby improving the reliability of the startup circuit; the startup circuit can make the RS latch structure get rid of the metastable point and avoid the need for external excitation. By integrating the startup circuit into the oscillator, an external circuit is no longer required to provide a startup signal, thereby simplifying the circuit design and reducing the required external components and circuit connections; at the same time, the startup circuit can reduce the power consumption of the overall circuit by increasing the resistance value;

[0033] (5) The utility model includes a comparison voltage generating circuit, which is beneficial to improving the integration of the chip;

[0034] (6) The circuit of the utility model adds an enable control, which can realize the opening and closing of the oscillator;

[0035] (7) When the other external circuits of the utility model need current bias, they can obtain it by mirroring the current of the M2 tube without external supply;

[0036] (8) In the present invention, since the startup circuit is integrated with the oscillator, the chip area can be reduced and the circuit integration can be improved. In this way, more functions can be integrated on the same chip, reducing the complexity and cost of the system; further, since no additional external circuits and components are required, the present invention can reduce the chip area and improve the compactness and efficiency of the circuit.

[0037] In summary, the utility model belongs to the technical field of oscillator circuits, can simplify circuit design, improve circuit integration, reduce chip area, and improve the reliability of the start-up circuit, thus having obvious advantages. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] The accompanying drawings are used to provide a further understanding of the present invention and constitute a part of the specification. They are used together with the embodiments of the present invention to explain the present invention and do not constitute a limitation to the present invention.

[0039] In the attached picture:

[0040] Figure 1 This is a circuit diagram of an embodiment of the utility model;

[0041] Figure 2A circuit schematic diagram of a startup circuit according to an embodiment of the present utility model;

[0042] Figure 3 A circuit schematic diagram of a reference voltage generating circuit according to an embodiment of the present utility model;

[0043] Figure 4 A circuit schematic diagram of an oscillator core circuit according to an embodiment of the present utility model;

[0044] Figure 5 The circuit diagram of the embodiment of the utility model;

[0045] Figure 6 Schematic diagram of the comparison process of the voltage VCAP and two reference voltages VH and VL in the embodiment of the utility model;

[0046] Figure 7 A simulation relationship diagram of the voltage VCAP and two reference voltages VH and VL in an embodiment of the utility model;

[0047] Figure 8 This is a diagram showing the output result of the final oscillation signal CLK of the entire oscillator circuit with a startup circuit and a comparison voltage in an embodiment of the present utility model. DETAILED DESCRIPTION

[0048] The preferred embodiments of the present invention are described below in conjunction with the accompanying drawings. It should be understood that the preferred embodiments described herein are only used to illustrate and explain the present invention, and are not used to limit the present invention.

[0049] Embodiment Oscillator circuit with start-up circuit and comparison voltage

[0050] like Figures 1 to 5 As shown, this embodiment includes a startup circuit, a reference voltage generation circuit and an oscillator core circuit.

[0051] Among them, the starting circuit includes a reference current generating branch and an excitation signal generating branch. The reference current generating branch includes a first enable input terminal and a second enable input terminal. The first enable input terminal inputs a high level ENP, and the second enable input terminal inputs a low level ENN. The output terminal of the reference current generating branch serves as a reference current output terminal of the starting circuit on the one hand, and is connected to the input terminal of the excitation signal generating branch on the other hand; the output terminal of the excitation signal generating branch serves as an excitation signal output terminal of the starting circuit, and outputs a voltage VS.

[0052] The reference voltage generating circuit includes a high-level reference branch and a low-level reference branch, and the input end of the high-level reference branch and the input end of the low-level reference branch are both connected to the reference current output end of the startup circuit. The output end of the high-level reference branch serves as the first reference voltage output end of the reference voltage generating circuit, outputting the first reference voltage VH; the output end of the low-level reference branch serves as the second reference voltage output end of the reference voltage generating circuit, outputting the second reference voltage VL.

[0053] The oscillator core circuit includes a current capacitor charging and discharging branch, a comparator branch and a latch branch.

[0054] The current capacitor charge and discharge branch includes an input terminal, an output terminal, a first control signal input terminal, a second control signal input terminal, and an enable signal input terminal. The input terminal of the current capacitor charge and discharge branch is connected to the reference current output terminal of the startup circuit. The comparator branch includes a first positive input terminal, a first negative input terminal, a first output terminal, a second positive input terminal, a second negative input terminal, and a second output terminal. The first positive input terminal of the comparator branch and the second negative input terminal of the comparator branch are both connected to the output terminal of the current capacitor charge and discharge branch, the first negative input terminal of the comparator branch is connected to the first reference voltage output terminal of the reference voltage generating circuit, and the second positive input terminal of the comparator branch is connected to the second reference voltage output terminal of the reference voltage generating circuit. The enable signal input terminal of the current capacitor charge and discharge branch is connected to the second enable input terminal of the startup circuit.

[0055] The latch branch includes an excitation signal input terminal, a reset signal input terminal, a set signal input terminal, a first output terminal, and a second output terminal. The excitation signal input terminal of the latch branch is connected to the excitation signal output terminal of the startup circuit, the reset signal input terminal of the latch branch is connected to the first output terminal of the comparator branch, the set signal input terminal of the latch branch is connected to the second output terminal of the comparator branch, and the first output terminal and the second output terminal of the latch branch serve as output terminals of an oscillator circuit with a startup circuit and a comparison voltage.

[0056] The first output end of the latch branch is connected to the first control signal input end of the current capacitor charging and discharging branch, and the second output end of the latch branch is connected to the second control signal input end of the current capacitor charging and discharging branch.

[0057] like Figure 2 and Figure 5 As shown, the reference current generating branch includes the zeroth MOS tube M0, the first MOS tube M1, the second MOS tube M2, the fourth MOS tube M4, the fifth MOS tube M5, the sixth MOS tube M6, the eighth MOS tube M8, the ninth MOS tube M9, the tenth MOS tube M10 and the first resistor R1. The excitation signal generating branch includes the third MOS tube M3, the seventh MOS tube M7 and the second resistor R2.

[0058] The gate of the zeroth MOS transistor M0 is used as the first enable input terminal of the reference current generating branch, inputting the high level ENP; the gate of the eighth MOS transistor M8 is used as the second enable input terminal of the reference current generating branch, inputting the low level ENN.

[0059] The source of the eighth MOS tube M8 is grounded, and the drain of the eighth MOS tube M8 is respectively connected to the drain of the ninth MOS tube M9, the gate and drain of the ninth MOS tube M9, the drain of the sixth MOS tube M6, the drain of the seventh MOS tube M7, and the gate of the first MOS tube M1; the source of the ninth MOS tube M9 is respectively connected to the drain and gate of the tenth MOS tube M10, and the source of the tenth MOS tube M10 is grounded; the source of the first MOS tube M1 is grounded through the first resistor R1, and the drain of the first MOS tube M1 is connected to the gate and drain of the second MOS tube M2, the gate of the third MOS tube M3, and the seventh MOS tube M7. The gate of the fourth MOS tube M4 is connected to the drain of the fourth MOS tube M4 respectively; the source of the second MOS tube M2, the source of the third MOS tube M3, the source of the fourth MOS tube M4, the source of the fifth MOS tube M5, the source of the sixth MOS tube M6 and the source of the seventh MOS tube M7 are all connected to the voltage VDD; the gate of the fourth MOS tube M4 is connected to the gate of the fifth MOS tube M5; the drain of the fifth MOS tube M5 is connected to the gate of the sixth MOS tube M6 and the drain of the third MOS tube M3 on the one hand, and is connected to the drain of the zeroth MOS tube M0 through the second resistor R2 on the other hand; the source of the zeroth MOS tube M0 is grounded.

[0060] The common end of the gate and drain of the second MOS tube M2 is used as the reference current output end of the startup circuit, and the common end of the drain of the third MOS tube M3 and the second resistor R2 is used as the excitation signal output end of the startup circuit, outputting the voltage VS.

[0061] like Figure 3 and Figure 5 As shown, the high-level reference branch includes an eleventh MOS transistor M11 and a third resistor R3, and the low-level reference branch includes a twelfth MOS transistor M12 and a fourth resistor R4.

[0062] The source of the eleventh MOS tube M11 and the source of the twelfth MOS tube M12 are both connected to the voltage VDD, the gate of the eleventh MOS tube M11 is connected to the gate of the twelfth MOS tube M12, the drain of the eleventh MOS tube M11 is grounded through the third resistor R3, and the drain of the twelfth MOS tube M12 is grounded through the fourth resistor R4.

[0063] The gate of the eleventh MOS tube M11 is used as the input end of the high-level reference branch, and the gate of the twelfth MOS tube M12 is used as the input end of the low-level reference branch, and both are connected to the gate of the second MOS tube M2, mirroring the current of the second MOS tube M2. The drain of the eleventh MOS tube M11 and the common end of the third resistor R3 are used as the first reference voltage output end of the reference voltage generating circuit, outputting the first reference voltage VH; the drain of the twelfth MOS tube M12 and the common end of the fourth resistor R4 are used as the second reference voltage output end of the reference voltage generating circuit, outputting the second reference voltage VL.

[0064] like Figure 4 and Figure 5 As shown, the current-capacitance charge-discharge branch includes a thirteenth MOS tube M13 to a twenty-first MOS tube M21 and a first capacitor.

[0065] The source of the thirteenth MOS tube M13, the source of the fourteenth MOS tube M14 and the drain of the nineteenth MOS tube M19 are all connected to the voltage VDD; the gate of the thirteenth MOS tube M13 and the gate of the fourteenth MOS tube M14 are connected together as the input end of the current capacitor charging and discharging branch.

[0066] The drain of the thirteenth MOS tube M13 is connected to the drain of the sixteenth MOS tube M16 and the gate of the sixteenth MOS tube M16, respectively, and the source of the sixteenth MOS tube M16 is grounded; the gate of the sixteenth MOS tube M16 is connected to the gate of the seventeenth MOS tube M17 and the drain of the fifteenth MOS tube M15, respectively, and the source of the fifteenth MOS tube M15 is grounded, and the gate of the fifteenth MOS tube M15 serves as the enable signal input terminal of the current capacitor charge and discharge branch, and inputs the enable signal ENN. The source of the seventeenth MOS tube M17 is grounded, and the drain of the seventeenth MOS tube M17 is connected to the source of the nineteenth MOS tube M19 and the source of the twenty-first MOS tube M21, respectively; the gate of the nineteenth MOS tube M19 is connected to the gate of the eighteenth MOS tube M18, serving as the first control signal input terminal of the current capacitor charge and discharge branch. The drain of the eighteenth MOS tube M18 is grounded, the source of the eighteenth MOS tube M18 is connected to the drain of the fourteenth MOS tube M14 and the source of the twentieth MOS tube M20 respectively, the gate of the twentieth MOS tube M20 is connected to the gate of the twenty-first MOS tube M21, and serves as the second control signal input end of the current capacitor charge-discharge branch. The drain of the twentieth MOS tube M20 is connected to the drain of the twenty-first MOS tube M21 and is grounded through the first capacitor, and the common end of the three serves as the output end of the current capacitor charge-discharge branch, and outputs the voltage VCAP.

[0067] The comparator branch includes a first comparator COMP1 and a second comparator COMP2. The positive phase input terminal of the first comparator COMP1 serves as the first positive phase input terminal of the comparator branch, the negative phase input terminal of the first comparator COMP1 serves as the first negative phase input terminal of the comparator branch, and the output terminal of the first comparator COMP1 serves as the first output terminal of the comparator branch. The positive phase input terminal of the second comparator COMP2 serves as the second positive phase input terminal of the comparator branch, the negative phase input terminal of the second comparator COMP2 serves as the second negative phase input terminal of the comparator branch, and the output terminal of the second comparator COMP2 serves as the second output terminal of the comparator branch.

[0068] The latch branch includes a twenty-second MOS transistor M22 and an RS latch. The source of the twenty-second MOS transistor M22 is connected to the voltage VDD, and the gate of the twenty-second MOS transistor M22 is used as the excitation signal input terminal of the latch branch, and the input voltage VS. The drain of the twenty-second MOS transistor M22 is connected to the reset terminal of the RS latch, which is used as the reset signal input terminal of the latch branch, the set terminal of the RS latch is used as the set signal input terminal of the latch branch, the positive phase output terminal of the RS latch is used as the first output terminal of the latch branch, and the negative phase output terminal of the RS latch is used as the second output terminal of the latch branch.

[0069] Figure 2 In the example, the working process of the startup circuit is as follows: after the power-on operation is enabled, the gate of the eighth MOS tube M8, that is, the second enable input terminal ENN is at a low level, and the gate of the zeroth MOS tube M0, that is, the first enable input terminal ENP is at a high level, so the zeroth MOS tube M0 is turned on, and the fourth MOS tube M4, the fifth MOS tube M5, and the eighth MOS tube M8 are turned off; then the drain of the third MOS tube and the common terminal voltage of R2, that is, the excitation signal output terminal voltage VS is pulled low; the sixth MOS tube M6 works first, that is, there is a current between the voltage VDD, the sixth MOS tube M6, the ninth MOS tube M9, and the tenth MOS tube M10. The voltage generated on the ninth MOS tube M9 then turns on the first MOS tube M1, so that the branch formed by the second MOS tube M2, the first MOS tube M1, and the first resistor R1 works normally and generates a reference current; then, the third MOS tube M3 and the seventh MOS tube M7 mirror the reference current of the second MOS tube M2; the current mirrored by the third MOS tube M3 passes through the second resistor R2 to generate a voltage VS; when the resistance value of the second resistor R2 is very large, the voltage VS is approximately equal to the voltage VDD, so the sixth MOS tube M6 is turned off, so the voltage VS is first low and then high, and this characteristic can just allow the RS latch to get rid of the metastable state. The above process is the working process of powering on the voltage VDD and enabling the start-up. After the entire startup circuit completes normal operation, it will turn off the startup tube, that is, the sixth MOS tube M6, so that the circuit works normally.

[0070] like Figure 3 As shown, the principle of the reference voltage generating circuit is: current flows through the third resistor R3 and the fourth resistor R4, and voltage is generated on the third resistor R3 and the fourth resistor R4. Specifically, the reference current generated in the mirror start circuit of the eleventh MOS tube M11 and the twelfth MOS tube M12, that is, the gates of the eleventh MOS tube M11 and the twelfth MOS tube M12 are connected to the gate of the second MOS tube M2, the current mirrored by the eleventh MOS tube M11 flows through the third resistor R3 to generate a first reference voltage VH, and the current mirrored by the twelfth MOS tube M12 flows through the fourth resistor R4 to generate a second reference voltage VL. By changing the resistance values ​​of the third resistor R3 and the fourth resistor R4, the values ​​of the first reference voltage VH and the second reference voltage VL can be changed. The first reference voltage VH and the second reference voltage VL are also called comparison voltages. When the chip layout is laid out, the third resistor R3 and the fourth resistor R4 are matched to obtain a more accurate ratio of the first reference voltage VH and the second reference voltage VL to ensure the oscillation frequency of the oscillator. Among them, VH = I11*R3, VL = I12*R4, where I11 is the current passing through the eleventh MOS tube M11, and I12 is the current passing through the twelfth MOS tube M12.

[0071] The specific implementation circuit of the oscillator core circuit is as follows Figure 4 As shown, the thirteenth MOS tube M13 and the fourteenth MOS tube M14 mirror the reference current generated in the startup circuit, that is, the gates of the thirteenth MOS tube M13 and the fourteenth MOS tube M14 are connected to the gate of the second MOS tube M2, and the gate of the twenty-second MOS tube M22 is connected to the voltage VS in the startup circuit part. Because the voltage VS is low first and then high, the RS latch gets rid of the metastable state.

[0072] Figure 5 The schematic diagram of the entire oscillator circuit with startup circuit and comparison voltage is given. This structure can also realize the opening and closing of the oscillator by enabling ENP and ENN. Figures 2 to 5 It can be seen that in the present embodiment, the second MOS tube M2, the third MOS tube M3, the fourth MOS tube M4, the fifth MOS tube M5, the sixth MOS tube M6, the seventh MOS tube M7, the eleventh MOS tube M11, the twelfth MOS tube M12, the thirteenth MOS tube M13, the fourteenth MOS tube M14, the eighteenth MOS tube M18, the twentieth MOS tube M20, and the twenty-second MOS tube M22 are all NMOS tubes; the zeroth MOS tube M0, the first MOS tube M1, the eighth MOS tube M8, the ninth MOS tube M9, the tenth MOS tube M10, the fifteenth MOS tube M15, the sixteenth MOS tube M16, the seventeenth MOS tube M17, the nineteenth MOS tube M19, and the twenty-first MOS tube M21 are all PMOS tubes.

[0073] like Figure 6 As shown in FIG. 1 , the comparison process between the voltage VCAP on the first capacitor C1 and the first reference voltage VH and the second reference voltage VL is shown. The output of the entire oscillator core circuit can select PHI1 or PHI0 as needed. Figure 6 In the stages ① to ⑦ shown, the working principle of the oscillator core circuit is as follows:

[0074] Phase ①: The current capacitor charging and discharging branch starts to start, the first capacitor C1 is not charged, and the output voltage is very low, that is, VCAP<VL and VCAP<VH, so the output of the first comparator COMP1 is low, and the output of the second comparator COMP2 is high, that is, the two input terminals of the RS latch reset signal input terminal R="0", and the set signal input terminal S="1", so the first output terminal outputs PHI1="1", and the second output terminal outputs PHI0="0". At this time, the eighteenth MOS tube M18 and the twenty-first MOS tube M21 are turned off, the nineteenth MOS tube M19 and the twentieth MOS tube M20 are turned on, and the current passes through the fourteenth MOS tube M14 and the twentieth MOS tube M20 to charge the first capacitor C1, and the voltage VCAP rises.

[0075] Phase ②: As the first capacitor C1 is charged, the voltage VCAP reaches a certain voltage value, VL<VCAP<VH, and the outputs of the first comparator COMP1 and the second comparator COMP2 are both low level, that is, the two input terminals R=S=“0” of the RS latch, so the output maintains the original state, the first output terminal PHI1=“1”, and the second output terminal output PHI0=“0”. At this time, the eighteenth MOS tube M18 and the twenty-first MOS tube M21 are turned off, the nineteenth MOS tube M19 and the twentieth MOS tube M20 are turned on, and the current still passes through the fourteenth MOS tube M14 and the twentieth MOS tube M20 to charge the first capacitor C1, and the voltage VCAP continues to rise.

[0076] Stage 3: When VL<VCAP and VH<VCAP, the VCAP voltage will rise a little bit because of the circuit delay.

[0077] Phase ④: When VL<VCAP and VH<VCAP, the output of the first comparator COMP1 is high and the output of the second comparator COMP2 is low, that is, the two input terminals of the RS latch reset signal input terminal R="1" and the set signal input terminal S="0", so the first output terminal outputs PHI1="0" and the second output terminal outputs PHI0="1". At this time, the eighteenth MOS tube M18 and the twenty-first MOS tube M21 are turned on, the nineteenth MOS tube M19 and the twentieth MOS tube M20 are turned off, and the charge on the first capacitor C1 is discharged to the ground through the twenty-first MOS tube M21 and the seventeenth MOS tube M17, and the voltage VCAP drops.

[0078] Phase ⑤: As the first capacitor C1 discharges, the voltage VCAP drops to a certain voltage value, VL<VCAP<VH, the outputs of the first comparator COMP1 and the second comparator COMP2 are both low level, that is, the two input terminals R=S=“0” of the RS latch, so the output maintains the original state, the first output terminal outputs PHI1=“0”, and the second output terminal outputs PHI0=“1”. At this time, the eighteenth MOS tube M18 and the twenty-first MOS tube M21 are turned on, the nineteenth MOS tube M19 and the twentieth MOS tube M20 are turned off, and the charge on the first capacitor C1 still passes through the twenty-first MOS tube M21 and the seventeenth MOS tube M17 to the ground, and continues to discharge, and the voltage VCAP continues to drop.

[0079] Stage ⑥: When VCAP<VL and VCAP<VH, the VCAP voltage will drop a little bit because of the circuit delay.

[0080] Phase 7: When VCAP<VL and VCAP<VH, the output of the first comparator COMP1 is low, and the output of the second comparator COMP2 is high, that is, the two input terminals of the RS latch reset signal input terminal R = "0", and the set signal input terminal S = "1", so the first output terminal outputs PHI1 = "1", and the second output terminal outputs PHI0 = "0". At this time, the eighteenth MOS tube M18 and the twenty-first MOS tube M21 are turned off, the nineteenth MOS tube M19 and the twentieth MOS tube M20 are turned on, and the current passes through the fourteenth MOS tube M14 and the twentieth MOS tube M20 to charge the first capacitor C1, and the voltage VCAP rises again.

[0081] Subsequently, as the capacitor C1 charges and discharges, the circuit repeats the above process over and over again to achieve oscillation.

[0082] Figure 7 The simulation relationship diagram of VCAP and two reference voltages VH and VL is given. The output of the entire oscillator circuit with startup circuit and comparison voltage can select PHI1 or PHI0 as needed. Figure 8 This is a diagram showing the output result of the final oscillation signal CLK of the entire oscillator circuit with a startup circuit and a comparison voltage.

[0083] It can be seen that in this embodiment, the startup circuit can not only generate a signal to get rid of the metastable state of the RS latch, but also provide a reference current to provide a basis for the normal operation of the rest of the parts. The startup part will shut down automatically after generating the reference current to ensure the normal operation of the oscillator and reduce the power consumption of the circuit. The reference voltage generation circuit uses the method of generating voltage by flowing current through the resistor to obtain a higher reference voltage VH and a lower reference voltage VL. The current is the reference current generated by the startup circuit, and the resistor can obtain a reference voltage with a higher temperature coefficient by selecting different types of resistors in the process library. The oscillator core circuit mainly includes two comparators, an RS latch and a current capacitor charging and discharging circuit. The two comparators use the same five-tube OTA structure, which is simple and guarantees speed; the RS latch is mainly composed of two NOR gates. In order to get rid of the metastable point, a PMOS control is added at the R end; the current capacitor charging and discharging circuit can realize the charge and discharge on the capacitor to obtain different voltage values, and then compare with the reference voltage. The above three parts need to work together to ensure the normal operation of the entire circuit.

Claims

1. An oscillator circuit with a start-up circuit and a comparison voltage, characterized in that: Including a startup circuit, a reference voltage generation circuit and an oscillator core circuit; Wherein, the starting circuit includes a reference current generating branch and an excitation signal generating branch, the reference current generating branch includes a first enable input terminal and a second enable input terminal, the first enable input terminal inputs a high level, and the second enable input terminal inputs a low level, the output terminal of the reference current generating branch serves as a reference current output terminal of the starting circuit on the one hand, and is connected to the input terminal of the excitation signal generating branch on the other hand; the output terminal of the excitation signal generating branch serves as an excitation signal output terminal of the starting circuit; The reference voltage generating circuit comprises a high level reference branch and a low level reference branch, the input end of the high level reference branch and the input end of the low level reference branch are both connected to the reference current output end of the start-up circuit; the output end of the high level reference branch serves as the first reference voltage output end of the reference voltage generating circuit, and the output end of the low level reference branch serves as the second reference voltage output end of the reference voltage generating circuit; The oscillator core circuit includes a current capacitor charging and discharging branch, a comparator branch and a latch branch; The current capacitor charge and discharge branch includes an input end, an output end, a first control signal input end, a second control signal input end, and an enable signal input end. The input end of the current capacitor charge and discharge branch is connected to the reference current output end of the startup circuit; the comparator branch includes a first positive input end, a first negative input end, a first output end, a second positive input end, a second negative input end, and a second output end. The first positive input end of the comparator branch and the second negative input end of the comparator branch are both connected to the output end of the current capacitor charge and discharge branch. The first negative input end of the comparator branch is connected to the first reference voltage output end of the reference voltage generating circuit, and the second positive input end of the comparator branch is connected to the second reference voltage output end of the reference voltage generating circuit; the enable signal input end of the current capacitor charge and discharge branch is connected to the second enable input end of the startup circuit; The latch branch includes an excitation signal input terminal, a reset signal input terminal, a set signal input terminal, a first output terminal, and a second output terminal. The excitation signal input terminal of the latch branch is connected to the excitation signal output terminal of the start-up circuit, the reset signal input terminal of the latch branch is connected to the first output terminal of the comparator branch, the set signal input terminal of the latch branch is connected to the second output terminal of the comparator branch, and the first output terminal and the second output terminal of the latch branch serve as output terminals of an oscillator circuit with a start-up circuit and a comparison voltage. The first output end of the latch branch is connected to the first control signal input end of the current capacitor charging and discharging branch, and the second output end of the latch branch is connected to the second control signal input end of the current capacitor charging and discharging branch.

2. An oscillator circuit with a start-up circuit and a comparison voltage according to claim 1, characterized in that: The reference current generating branch includes a zeroth MOS tube, a first MOS tube, a second MOS tube, a fourth MOS tube, a fifth MOS tube, a sixth MOS tube, an eighth MOS tube, a ninth MOS tube, a tenth MOS tube and a first resistor; the excitation signal generating branch includes a third MOS tube, a seventh MOS tube and a second resistor; The gate of the zeroth MOS transistor serves as the first enable input terminal of the reference current generating branch, and the gate of the eighth MOS transistor serves as the second enable input terminal of the reference current generating branch; The source of the eighth MOS tube is grounded, and the drain of the eighth MOS tube is respectively connected to the drain of the ninth MOS tube, the gate and drain of the ninth MOS tube, the drain of the sixth MOS tube, the drain of the seventh MOS tube, and the gate of the first MOS tube; the source of the ninth MOS tube is respectively connected to the drain and gate of the tenth MOS tube, and the source of the tenth MOS tube is grounded; the source of the first MOS tube is grounded through the first resistor, and the drain of the first MOS tube is respectively connected to the gate and drain of the second MOS tube, the gate of the third MOS tube, the gate of the seventh MOS tube, and the drain of the fourth MOS tube; the source of the second MOS tube, the source of the third MOS tube, the source of the fourth MOS tube, the source of the fifth MOS tube, the source of the sixth MOS tube, and the source of the seventh MOS tube are all connected to the voltage VDD; the gate of the fourth MOS tube is connected to the gate of the fifth MOS tube; the drain of the fifth MOS tube is connected to the gate of the sixth MOS tube and the drain of the third MOS tube on the one hand, and is connected to the drain of the zeroth MOS tube through the second resistor on the other hand; the source of the zeroth MOS tube is grounded; The common end of the gate and drain of the second MOS tube serves as the reference current output end of the startup circuit, and the common end of the drain of the third MOS tube and the second resistor serves as the excitation signal output end of the startup circuit.

3. An oscillator circuit with a start-up circuit and a comparison voltage according to claim 2, characterized in that: The high level reference branch includes an eleventh MOS tube and a third resistor, and the low level reference branch includes a twelfth MOS tube and a fourth resistor; The source of the eleventh MOS tube and the source of the twelfth MOS tube are both connected to the voltage VDD, the gate of the eleventh MOS tube is connected to the gate of the twelfth MOS tube, the drain of the eleventh MOS tube is grounded through the third resistor, and the drain of the twelfth MOS tube is grounded through the fourth resistor; The gate of the eleventh MOS tube serves as the input end of the high-level reference branch, and the gate of the twelfth MOS tube serves as the input end of the low-level reference branch; the drain of the eleventh MOS tube and the common end of the third resistor serve as the first reference voltage output end of the reference voltage generating circuit; the drain of the twelfth MOS tube and the common end of the fourth resistor serve as the second reference voltage output end of the reference voltage generating circuit.

4. An oscillator circuit with a start-up circuit and a comparison voltage according to claim 3, characterized in that: The current capacitor charging and discharging branch includes a thirteenth MOS tube to a twenty-first MOS tube and a first capacitor; The source of the thirteenth MOS tube, the source of the fourteenth MOS tube, and the drain of the nineteenth MOS tube are all connected to the voltage VDD; the gate of the thirteenth MOS tube and the gate of the fourteenth MOS tube are connected together as the input end of the current capacitor charging and discharging branch; The drain of the thirteenth MOS tube is connected to the drain of the sixteenth MOS tube and the gate of the sixteenth MOS tube respectively, and the source of the sixteenth MOS tube is grounded; the gate of the sixteenth MOS tube is connected to the gate of the seventeenth MOS tube and the drain of the fifteenth MOS tube respectively, and the source of the fifteenth MOS tube is grounded, and the gate of the fifteenth MOS tube serves as the enable signal input terminal of the current capacitor charge and discharge branch; the source of the seventeenth MOS tube is grounded, and the drain of the seventeenth MOS tube is connected to the source of the nineteenth MOS tube and the source of the twenty-first MOS tube respectively; the gate of the nineteenth MOS tube is connected to the gate of the seventeenth MOS tube and the drain of the fifteenth MOS tube respectively; The gate of the 20th MOS tube is connected to the gate of the 21st MOS tube, serving as the first control signal input end of the current capacitor charging and discharging branch; the drain of the 18th MOS tube is grounded, the source of the 18th MOS tube is connected to the drain of the 14th MOS tube and the source of the 20th MOS tube respectively, and the gate of the 20th MOS tube is connected to the gate of the 21st MOS tube, serving as the second control signal input end of the current capacitor charging and discharging branch; the drain of the 20th MOS tube is connected to the drain of the 21st MOS tube and is grounded through the first capacitor, and the common end of the three serves as the output end of the current capacitor charging and discharging branch.

5. An oscillator circuit with a start-up circuit and a comparison voltage according to claim 4, characterized in that: The comparator branch includes a first comparator and a second comparator; The non-inverting input terminal of the first comparator serves as the first non-inverting input terminal of the comparator branch, the inverting input terminal of the first comparator serves as the first inverting input terminal of the comparator branch, and the output terminal of the first comparator serves as the first output terminal of the comparator branch; The non-inverting input terminal of the second comparator serves as the second non-inverting input terminal of the comparator branch, the inverting input terminal of the second comparator serves as the second inverting input terminal of the comparator branch, and the output terminal of the second comparator serves as the second output terminal of the comparator branch.

6. An oscillator circuit with a start-up circuit and a comparison voltage according to claim 5, characterized in that: The latch branch includes a twenty-second MOS tube and an RS latch; The source of the twenty-second MOS tube is connected to the voltage VDD, and the gate of the twenty-second MOS tube serves as the excitation signal input terminal of the latch branch; the drain of the twenty-second MOS tube is connected to the reset terminal of the RS latch, serving as the reset signal input terminal of the latch branch, the set terminal of the RS latch serves as the set signal input terminal of the latch branch, the positive phase output terminal of the RS latch serves as the first output terminal of the latch branch, and the negative phase output terminal of the RS latch serves as the second output terminal of the latch branch.

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