A power-on timing protection circuit for power amplifiers

Abstract

The utility model discloses a power-on timing protection circuit for a power amplifier, including a voltage stabilizing diode and a NOT gate, an AND gate, a driver, and a P-channel MOS field effect transistor; the input end of the voltage stabilizing diode and the NOT gate is connected to a DC voltage stabilizing power supply, the output end of the voltage stabilizing diode and the NOT gate is connected to an input end of the AND gate, and the other input end of the AND gate is connected to an external TTL; the output end of the AND gate is connected to the input end of the driver; the output end of the driver is connected to the gate of the P-channel MOS field effect transistor. The voltage stabilizing diode and the NOT gate of the utility model convert 0, ‑5V to 0, +5V, the AND gate is used for logic relationship conversion, the driver is used to increase the TTL high-level voltage to control the gate of the P-channel MOS field effect transistor, and the P-channel MOS field effect transistor is used to control the shutdown of the positive voltage of the power amplifier, thereby solving the problem that the power amplifier is burned due to the power-on timing of the gate and drain of the power amplifier.

Description

Technical Field

[0001] The utility model belongs to the technical field of protection circuits, and in particular relates to a power-on timing protection circuit applied to a power amplifier. Background Art

[0002] As an important component of the transmitter, the stability and reliability of the power amplifier's working state have a great impact on the performance of the entire device.

[0003] The power-on sequence of the power amplifier is crucial to protect the power amplifier tube and ensure its normal operation. The wrong power-on sequence may cause the power amplifier tube to burn out. This is because the power amplifier tube, especially the field effect tube, is a voltage-controlled current type device, and the size of its drain current depends on the size of the gate voltage. When powering on, if the drain voltage is applied to the power amplifier tube before the gate voltage, the gate voltage may not be adjusted to a suitable static operating point, resulting in excessive drain current, thereby burning out the field effect tube.

[0004] With the continuous development of electronic technology, power amplifiers have been widely used in fields such as communications and consumer electronics. For different types of power amplifiers, the design of their power-on timing also needs to be optimized and adjusted according to specific application scenarios and device characteristics. Utility Model Content

[0005] The utility model aims to address the above-mentioned deficiencies in the prior art and to provide a power amplifier power-on timing protection circuit to solve the problem that the power amplifier is burned out due to the power-on timing of the gate and drain of the power amplifier.

[0006] In order to achieve the above purpose, the technical solution adopted by the utility model is:

[0007] A power-on timing protection circuit for a power amplifier, comprising a voltage-stabilizing diode, a NOT gate, an AND gate, a driver, and a P-channel MOS field effect transistor;

[0008] The input end of the voltage stabilizing diode and the NOT gate is connected to a DC regulated power supply, the output end of the voltage stabilizing diode and the NOT gate is connected to one input end of the AND gate, and the other input end of the AND gate is connected to an external TTL;

[0009] The output end of the AND gate is connected to the input end of the driver; the output end of the driver is connected to the gate of the P-channel MOS field effect transistor.

[0010] Furthermore, the DC voltage-stabilized power supply provides two -5V voltages, one of which is connected to the input end of the voltage-stabilizing diode, the output end of the voltage-stabilizing diode is connected to the input end of the NOT gate, and the other is connected to the voltage-dividing resistor.

[0011] Furthermore, the voltage divider resistor divides the -5V voltage into -0.8V and inputs the voltage to the gate of the power amplifier.

[0012] Furthermore, the voltage stabilizing diode and the NOT gate convert -5V into a high level +5V, and output the high level +5V to the input end of the AND gate through the output end of the NOT gate.

[0013] Furthermore, the external TTL provides a high level +5V, and inputs the high level +5V to the input terminal of the AND gate.

[0014] Furthermore, the AND gate outputs a high level +5V to the driver input terminal, and the driver converts the high level +5V into a low level 0V and outputs it to the gate of the P-channel MOS field effect transistor.

[0015] Furthermore, the drain of the P-channel MOS field effect transistor is connected to the drain of the power amplifier.

[0016] The utility model provides a power-on timing protection circuit for a power amplifier, which has the following beneficial effects:

[0017] The utility model uses a voltage stabilizing diode and a NOT gate to convert 0 and -5V into 0 and +5V, an AND gate is used for logic relationship conversion, a driver is used to increase the TTL high-level voltage to control the gate of a P-channel MOS field effect transistor, and the P-channel MOS field effect transistor is used to control the shutdown of the positive voltage of a power amplifier. Based on the cooperation of the voltage stabilizing diode, the NOT gate, the AND gate, the driver, and the P-channel MOS field effect transistor, the problem of burning out the power amplifier due to the power-on timing of the gate and drain of the power amplifier is solved. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 The utility model is a principle block diagram of a power amplifier power-on timing protection circuit.

[0019] Figure 2 The schematic diagram is a principle diagram of an implementation method of a power-on timing protection circuit for a power amplifier.

[0020] Figure 3 The utility model is a circuit diagram of a power amplifier power-on timing protection circuit. DETAILED DESCRIPTION

[0021] The specific implementation methods of the utility model are described below to facilitate technical personnel in this technical field to understand the utility model, but it should be clear that the utility model is not limited to the scope of the specific implementation methods. For ordinary technical personnel in this technical field, as long as various changes are within the spirit and scope of the utility model defined and determined by the attached claims, these changes are obvious, and all utility model creations using the concept of the utility model are protected.

[0022] Reference to an embodiment herein means that a particular feature, structure, or characteristic described in conjunction with the embodiment may be included in at least one embodiment of the present application. The appearance of the phrase in various locations in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0023] It is understandable that the power-on timing protection circuit in the present application works with the power amplifier, and the testing and analysis equipment includes a DC power supply, a signal source, a spectrum analyzer, a multimeter, etc. In order to enable those skilled in the art to better understand the present application, the technical solution in the embodiment of the present application will be clearly and completely described below in conjunction with the accompanying drawings.

[0024] Example 1

[0025] This embodiment provides a power-on timing protection circuit for a power amplifier, which is used to solve the problem that the power amplifier is burned due to the power-on timing of the gate and drain of the power amplifier. Figure 1 and Figure 2 , which specifically include:

[0026] Zener diodes and NOT gates, AND gates, drivers, P-channel MOS field effect transistors;

[0027] Since the voltage zener diode and the NOT gate are combined to convert 0, -5V to 0, +5V, the voltage zener diode and the NOT gate are considered as a whole in this embodiment;

[0028] That is, the input end of the voltage stabilizing diode and the NOT gate is connected to the DC regulated power supply, and the output end of the voltage stabilizing diode and the NOT gate is connected to an input end of the AND gate;

[0029] Its essence is that the input end of the Zener diode is connected to the DC regulated power supply, the output end of the Zener diode is connected to the input end of the NOT gate, and the output end of the NOT gate is connected to one input end of the AND gate.

[0030] The other input end of the AND gate is connected to the external TTL, the output end of the AND gate is connected to the driver input end; the driver output end is connected to the gate of the P-channel MOS field effect transistor.

[0031] The AND gate in this embodiment is used for logic relationship conversion;

[0032] The driver is used to increase the TTL high-level voltage to control the gate of the P-channel MOS field effect transistor;

[0033] The P-channel MOS field effect transistor is used to control the shutdown of the positive voltage of the power amplifier.

[0034] Specifically, a DC regulated power supply provides two -5V voltages, one of which is connected to the input end of a voltage stabilizing diode and a NOT gate, and the other is connected to a voltage dividing resistor; the voltage dividing resistor divides the -5V voltage into -0.8V to supply a gate voltage of a power amplifier; the voltage stabilizing diode and the NOT gate convert -5V into a high level +5V, and outputs the high level +5V to the input end of the AND gate; an external TTL provides a high level +5V, and inputs the high level +5V to the input end of the AND gate; the AND gate outputs a high level +5V to the input end of the driver, and the driver converts the high level +5V into a low level 0V and outputs it to the gate of a P-channel MOS field effect transistor; the drain of the P-channel MOS field effect transistor is connected to the power amplifier.

[0035] In this embodiment, the source of the P-channel MOS field effect transistor is connected to the positive voltage required by the drain of the power amplifier, and the drain of the P-channel MOS field effect transistor is connected to the drain of the power amplifier. When the voltage zener diode input is -5V and the AND gate input is +5V, the source and drain of the P-channel MOS field effect transistor are turned on, thereby providing a positive voltage to the gate of the power amplifier. When either the voltage zener diode input or the AND gate input is 0V, the source and drain of the P-channel MOS field effect transistor are turned off.

[0036] This embodiment 2

[0037] refer to Figure 2 and Figure 3 This embodiment is described by taking a power amplifier with a working gate voltage of 0.8V and a drain voltage of 8V as an example.

[0038] When the power amplifier is powered on, the timing protection circuit works as follows:

[0039] The DC regulated power supply provides -5V for the Zener diode, +5V for the VCC of the NOT gate and AND gate, and +8V for the source of the P-channel MOS field effect transistor;

[0040] The -5V provided by the DC regulated power supply is divided into -0.8V by a voltage divider resistor and directly supplied to the gate voltage of the power amplifier. The other way is supplied to the zener diode. The zener diode and the NOT gate convert -5V to a high level of +5V, and output +5V to the AND gate A through the NOT gate. At this time, the external TTL is set to a high level of +5V and given to the AND gate B. The AND gate Y outputs a high level of +5V to the driver. The driver converts the input high level +5V into a low level 0V and outputs it to the gate of the P-channel MOS field effect tube. The source and drain of the P-channel MOS field effect tube are turned on, the drain voltage of the power amplifier is powered, and the power amplifier amplifies the input RF signal.

[0041] When the power amplifier is powered off and does not work, the timing protection circuit works as follows:

[0042] Set the external TTL to a low level of 0V and give it to gate B. AND gate Y outputs a low level of 0V to the driver. The driver converts the input low level 0V into a high level +8V and outputs it to the gate of the P-channel MOS field effect transistor. The source and drain of the P-channel MOS field effect transistor are cut off. At this time, the power amplifier leakage voltage is not powered and does not work.

[0043] When the DC regulated power supply does not provide -5V to the Zener diode, but provides +5V to the VCC of the NOT gate and the AND gate, and +8V to the source of the P-channel MOS field effect transistor, the power amplifier gate voltage has no -0.8V supply, and the NOT gate outputs a low level 0V to the AND gate A. At this time, no matter the external TTL is set to a low level 0V or a high level +5V to the AND gate B, the AND gate Y outputs a low level 0V to the driver. The driver converts the input low level 0V into a high level +8V and outputs it to the gate of the P-channel MOS field effect transistor. The source and drain of the P-channel MOS field effect transistor are cut off, and the power amplifier drain voltage does not work without power supply.

[0044] Although the specific implementation of the utility model is described in detail in conjunction with the drawings, it should not be understood as limiting the scope of protection of this patent. Within the scope described in the claims, various modifications and variations that can be made by those skilled in the art without creative work still fall within the scope of protection of this patent.

Claims

1. A power-on timing protection circuit for a power amplifier, characterized in that: Including voltage stabilizing diodes and NOT gates, AND gates, drivers, and P-channel MOS field effect transistors; The input ends of the voltage stabilizing diode and the NOT gate are connected to a DC regulated power supply, the output end of the voltage stabilizing diode and the NOT gate is connected to an input end of the AND gate, and the other input end of the AND gate is connected to an external TTL; The output end of the AND gate is connected to the input end of the driver; the output end of the driver is connected to the gate of the P-channel MOS field effect transistor.

2. The power-on timing protection circuit for a power amplifier according to claim 1, characterized in that: The DC voltage-stabilized power supply provides two -5V voltages, one of which is connected to the input end of the voltage-stabilizing diode, the output end of the voltage-stabilizing diode is connected to the input end of the NOT gate, and the other is connected to the voltage-dividing resistor.

3. The power-on timing protection circuit for a power amplifier according to claim 2, characterized in that: The voltage-dividing resistor divides the -5V voltage into -0.8V and inputs the voltage to the gate of the power amplifier.

4. The power-on timing protection circuit for a power amplifier according to claim 2, characterized in that: The voltage stabilizing diode and the NOT gate convert -5V into a high level +5V, and output the high level +5V to the input end of the AND gate through the output end of the NOT gate.

5. The power-on timing protection circuit for a power amplifier according to claim 4, characterized in that: The external TTL provides a high level +5V, and inputs the high level +5V to the input terminal of the AND gate.

6. The power-on timing protection circuit for a power amplifier according to claim 5, characterized in that: The AND gate outputs a high level +5V to the driver input terminal, and the driver converts the high level +5V into a low level 0V and outputs it to the gate of the P-channel MOS field effect tube.

7. The power-on timing protection circuit for a power amplifier according to claim 6, characterized in that: The drain of the P-channel MOS field effect transistor is connected to the drain of the power amplifier.

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