A power reset circuit based on watchdog chip driver

Abstract

The utility model discloses a power reset circuit based on watchdog chip drive, which relates to the technical field of watchdog chips, including: PMOS tube Q1, NMOS tube Q2, diode D1 and power conversion chip N1, watchdog reset signal is electrically connected to resistor R2, the resistor R2 is electrically connected to the NMOS tube Q2, the resistor R2 is electrically connected to resistor R3 and resistor R1, and the resistor R3 is electrically connected to the PMOS tube Q1. Beneficial effect: By using discrete devices such as PMOS tube Q1, NMOS tube Q2 and power conversion chip N1 to build a circuit, the cost is low, and the watchdog reset signal is used as input to achieve hardware reset, the circuit is simple and reliable, and the processor power is disconnected for reset, which effectively avoids the occurrence of hardware interface abnormalities when the processor software is restarted. In addition, it can be adjusted according to the actual circuit working needs, and has a wide range of applications.

Description

Technical Field

[0001] The utility model relates to the technical field of watchdog chips, in particular to a power reset circuit driven by a watchdog chip. Background Art

[0002] In a microcomputer system composed of a single-chip microcomputer, the operation of the single-chip microcomputer is often interfered by external electromagnetic fields, causing confusion in the data of various registers and memories, resulting in program pointer errors, being out of the program area, taking out wrong program instructions, etc., which may lead to an infinite loop and interrupt the normal operation of the program. The system controlled by the single-chip microcomputer cannot continue to work normally, causing the entire system to stagnate and unpredictable consequences.

[0003] At present, in order to automatically restore the system when a system failure or abnormal situation occurs, software watchdog and hardware watchdog are generally used. Among them, the hardware watchdog uses a timer circuit, whose timing output is connected to the reset end of the circuit. The program clears the timer within a certain time range. Therefore, when the program works normally, the timer cannot overflow and cannot generate a reset signal. If the program fails and does not reset the watchdog within the timing period, the watchdog timer overflows to generate a reset signal and restart the system. The working principle diagram of the watchdog is shown in the figure below. Figure 2 The principle of software watchdog is the same, except that the timer on the hardware circuit is replaced by the internal timer of the processor. This can simplify the hardware circuit design, but it is not as reliable as the hardware timer. For example, if the internal timer of the system fails, it cannot be detected.

[0004] However, the existing technical solution is to use the reset signal output of the watchdog as the input of the processor reset pin, so as to reset and restart the processor program when an abnormality occurs in the processor program. This solution has the following disadvantages: when the processor software runs abnormally due to external interference, both the software watchdog and the hardware watchdog can restart the processor program, but if the processor hardware interface is already in an abnormal state (such as abnormal potential), the program restart itself cannot solve the abnormal state, and the entire system will continue to remain in an abnormal state, and the various functions of the system cannot be completed normally.

[0005] Currently, no effective solution has been proposed for the problems in the related technologies. Utility Model Content

[0006] In view of the problems in the related art, the purpose of the utility model is to propose a power reset circuit based on a watchdog chip driver to overcome the above technical problems existing in the existing related art.

[0007] The technical solution of the utility model is achieved in this way:

[0008] A power reset circuit based on a watchdog chip driver comprises: a PMOS tube Q1, an NMOS tube Q2, a diode D1 and a power conversion chip N1, wherein;

[0009] The watchdog reset signal is electrically connected to the resistor R2, the resistor R2 is electrically connected to the NMOS tube Q2, the resistor R2 is electrically connected to the resistor R3 and the resistor R1, the resistor R3 is electrically connected to the PMOS tube Q1, and the resistor R1 is electrically connected to the external power input VIN terminal and the PMOS tube Q1 respectively, the PMOS tube Q1 is electrically connected to the diode D1, the diode D1 is electrically connected to the power conversion chip N1, and the power conversion chip N1 is electrically connected to the output power VCC terminal.

[0010] Furthermore, the diode D1 is electrically connected to the capacitor C1, the capacitor C1 is electrically connected to the power conversion chip N1, the capacitor C2 and the capacitor C3 respectively, and the capacitor C2 and the capacitor C3 are electrically connected to the power conversion chip N1 respectively.

[0011] Furthermore, the capacitor C2 and the capacitor C3 are electrically connected to the output power supply VCC terminal respectively.

[0012] Beneficial effects of the utility model:

[0013] The utility model uses discrete devices such as a PMOS tube Q1 and an NMOS tube Q2 and a power conversion chip N1 to build a circuit, which has low cost. At the same time, a watchdog reset signal is used as an input to achieve hardware reset. The circuit is simple and reliable. In addition, the processor power is disconnected for reset, which effectively avoids the occurrence of hardware interface abnormalities due to processor software restart. In addition, it can be adjusted according to actual circuit working needs and has a wide range of applications.

[0014] Other features and advantages of the utility model will be described in the following description, and partly become apparent from the description, or understood by practicing the utility model. The purpose and other advantages of the utility model are realized and obtained by the structures particularly pointed out in the description and the drawings.

[0015] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, preferred embodiments are given below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the embodiments of the utility model or the technical solutions in the prior art, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the utility model. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0017] Figure 1 It is a circuit diagram of a power reset circuit based on a watchdog chip driver according to an embodiment of the utility model;

[0018] Figure 2 The present invention is a working principle diagram of a watchdog based on a power reset circuit driven by a watchdog chip according to an embodiment of the present invention. DETAILED DESCRIPTION

[0019] The following will be combined with the drawings in the embodiments of the utility model to clearly and completely describe the technical solutions in the embodiments of the utility model. Obviously, the described embodiments are only part of the embodiments of the utility model, not all of the embodiments. Based on the embodiments in the utility model, all other embodiments obtained by ordinary technicians in this field belong to the scope of protection of the utility model.

[0020] According to an embodiment of the utility model, a power reset circuit based on a watchdog chip driver is provided.

[0021] like Figure 1 As shown, a power reset circuit based on watchdog chip driving includes: a PMOS tube Q1, an NMOS tube Q2, a diode D1 and a power conversion chip N1, wherein;

[0022] The watchdog reset signal is electrically connected to the resistor R2, the resistor R2 is electrically connected to the NMOS tube Q2, the resistor R2 is electrically connected to the resistor R3 and the resistor R1, the resistor R3 is electrically connected to the PMOS tube Q1, and the resistor R1 is electrically connected to the external power input VIN terminal and the PMOS tube Q1 respectively, the PMOS tube Q1 is electrically connected to the diode D1, the diode D1 is electrically connected to the power conversion chip N1, and the power conversion chip N1 is electrically connected to the output power VCC terminal.

[0023] The diode D1 is electrically connected to the capacitor C1, the capacitor C1 is electrically connected to the power conversion chip N1, the capacitor C2 and the capacitor C3 respectively, and the capacitor C2 and the capacitor C3 are electrically connected to the power conversion chip N1 respectively. The capacitor C2 and the capacitor C3 are electrically connected to the output power VCC terminal respectively.

[0024] With the help of the above solution, when the system is working normally, the watchdog reset signal outputs a high level, the PMOS tube Q1 and the NMOS tube Q2 are both turned on, the external power input VIN terminal supplies power to the power conversion chip N1 through the diode D1, and outputs the power required for the normal operation of the processor to the output power VCC terminal.

[0025] In addition, when external interference causes software to run abnormally, the watchdog reset signal outputs a low-level reset signal, and both the PMOS tube Q1 and the NMOS tube Q2 are not turned on. The external power input VIN end cannot supply power to the power conversion chip N1 through the diode D1, and thus cannot output the power required for the normal operation of the processor to the output power VCC end. The processor will enter a power-off state, and all interfaces will be in a reset state; when the watchdog reset pin has passed a fixed reset time, the reset pin will flip the level and output a high-level signal. At this time, the PMOS tube Q1 and the NMOS tube Q2 are turned on again, and the external power input VIN end supplies power to the power conversion chip N1 through the diode D1, and outputs the power required for the normal operation of the processor to the output power VCC end, and the system restarts.

[0026] With the help of the above solution, when external interference causes the processor software to run abnormally, the watchdog chip controls the output of the processor's power supply module, thereby initializing all hardware interfaces and restarting software programs when an abnormality occurs in the system to ensure the normal operation of the system functions.

[0027] In summary, with the aid of the above technical solution of the utility model, the following effects can be achieved: by using discrete devices such as the PMOS tube Q1 and the NMOS tube Q2 and the power conversion chip N1 to build a circuit, the cost is low, and the watchdog reset signal is used as input to achieve hardware reset. The circuit is simple and reliable. In addition, the processor power is disconnected for reset, which effectively avoids the occurrence of hardware interface abnormalities due to processor software restart. In addition, it can be adjusted according to the actual circuit working needs and has a wide range of applications.

[0028] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A power reset circuit based on a watchdog chip driver, characterized in that: include: PMOS tube Q1, NMOS tube Q2, diode D1 and power conversion chip N1, among which; The watchdog reset signal is electrically connected to the resistor R2, the resistor R2 is electrically connected to the NMOS tube Q2, the resistor R2 is electrically connected to the resistor R3 and the resistor R1, the resistor R3 is electrically connected to the PMOS tube Q1, and the resistor R1 is electrically connected to the external power input VIN terminal and the PMOS tube Q1 respectively, the PMOS tube Q1 is electrically connected to the diode D1, the diode D1 is electrically connected to the power conversion chip N1, and the power conversion chip N1 is electrically connected to the output power VCC terminal.

2. A power reset circuit based on watchdog chip drive according to claim 1, characterized in that: The diode D1 is electrically connected to the capacitor C1, the capacitor C1 is electrically connected to the power conversion chip N1, the capacitor C2 and the capacitor C3 respectively, and the capacitor C2 and the capacitor C3 are electrically connected to the power conversion chip N1 respectively.

3. A power reset circuit based on watchdog chip drive according to claim 2, characterized in that: The capacitor C2 and the capacitor C3 are electrically connected to the output power supply VCC terminal respectively.

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