A timeout detection circuit for CAN transceiver chip

Abstract

The utility model relates to the field of timeout detection, and in particular to a timeout detection circuit applied to a CAN transceiver chip, comprising a start-up module, a charging module and an output module; the start-up module, the charging module and the output module are all electrically connected to an external power supply VCC, a first control end, a second control end, a third control end and a fourth control end of the start-up module are electrically connected to the charging module, a fifth control end of the start-up module is electrically connected to the output module, an output end of the charging module is electrically connected to the output module, a current mirror structure is used and time delay control is realized according to the time characteristics of charging and discharging of a capacitor C0, so that a timeout event can be quickly responded to and a corresponding action can be quickly stopped.

Description

Technical Field

[0001] The utility model relates to the field of timeout detection, in particular to a timeout detection circuit applied to a CAN transceiver chip. Background Art

[0002] CAN transceiver chips are an indispensable part of automotive electronics and industrial communications. They are responsible for converting the signals generated by the CAN controller into differential signals suitable for CAN bus transmission, and also converting the differential signals on the bus back to level signals that the controller can recognize. These chips ensure the reliability of CAN communication and maintain stable communication quality even in harsh electromagnetic environments. CAN transceiver chips not only support high-speed data transmission, but also support multi-master node structure, allowing different devices to send and receive data at the same time, greatly improving the real-time performance and flexibility of the system.

[0003] Timeout detection of CAN transceiver chips is an important part of ensuring the stability of CAN communication. In practical applications, when a CAN node does not respond or does not send expected data within a period of time, timeout detection is required to determine whether there is a fault. Conventional timeout detection circuits usually use RC circuits or are based on simple timers, but they are greatly affected by component parameters. At the same time, environmental conditions or signal interference can cause timing errors or instability, resulting in low timeout detection accuracy and reliability. Utility Model Content

[0004] The purpose of the utility model is to provide a timeout detection circuit applied to a CAN transceiver chip, aiming to improve the conventional timeout detection circuit which usually uses an RC circuit or is based on a simple timer, but is greatly affected by component parameters, and the influence of environmental conditions or signal interference can cause timing errors or instability, low timeout detection accuracy, and low reliability.

[0005] In order to achieve the above purpose, the utility model adopts the following technical solutions:

[0006] A timeout detection circuit applied to a CAN transceiver chip, comprising a start-up module, a charging module and an output module;

[0007] The charging module includes MOS transistor P2, MOS transistor P3, MOS transistor P5, MOS transistor P6, MOS transistor P7, MOS transistor P8, MOS transistor P9, MOS transistor P10, MOS transistor N1, MOS transistor N2, MOS transistor N4, MOS transistor N5, MOS transistor N6, MOS transistor N7 and capacitor C0;

[0008] The source of the MOS transistor P2, the source of the MOS transistor P3, the source of the MOS transistor P5, the source of the MOS transistor P6, and one end of the capacitor C0 are all electrically connected to the startup module, the output module and the external power supply VCC;

[0009] The first control end of the startup module is electrically connected to the gate and drain of MOS tube P2, the gate of MOS tube P3, the drain of MOS tube N1 and the output module; the second control end of the startup module is electrically connected to the gate and drain of MOS tube P5, the gate of MOS tube P6, the gate of MOS tube P7, the gate of MOS tube P8, the gate of MOS tube P9, the gate of MOS tube P10 and the drain of MOS tube N6; the gate of MOS tube N1 is electrically connected to the external bias voltage V ref Electrical connection;

[0010] The drain of the MOS transistor P6 is electrically connected to the source of the MOS transistor P7; the drain of the MOS transistor P7 is electrically connected to the source of the MOS transistor P8; the drain of the MOS transistor P8 is electrically connected to the source of the MOS transistor P9; the drain of the MOS transistor P9 is electrically connected to the source of the MOS transistor P10; the drain of the MOS transistor P10 is electrically connected to the drain of the MOS transistor N7 and the other end of the capacitor C0, and serves as an output end to output V A To the output module; the gate of the MOS tube N7 is connected to the external transmission data input V Datain Electrical connection;

[0011] The third control terminal of the startup module is electrically connected to the drain of the MOS transistor P3, the drain and gate of the MOS transistor N2, the gate of the MOS transistor N4, the gate of the MOS transistor N5 and the gate of the MOS transistor N6; the fourth control terminal of the startup module is electrically connected to the other end of the capacitor C0; the fifth control terminal of the startup module is electrically connected to the output module; the drain of the MOS transistor N4 is electrically connected to the source of the MOS transistor N5, and the drain of the MOS transistor N5 is electrically connected to the source of the MOS transistor N6;

[0012] The source of the MOS transistor N1 , the source of the MOS transistor N2 , the source of the MOS transistor N3 , the source of the MOS transistor N4 and the source of the MOS transistor N7 are all grounded.

[0013] Furthermore, the following conditions are met:

[0014] (W / L) P5 =m*(W / L) P6 =m*(W / L) P7 =m*(W / L) P8 =m*(W / L) P9 =m*(W / L) P10

[0015] (W / L) N2 =n*(W / L) N4 =n*(W / L) N5 =n*(W / L) N6

[0016] Among them, (W / L) P5 is the width-to-length ratio of MOS tube P5; (W / L) P6 is the width-to-length ratio of MOS tube P6; (W / L) P7 is the width-to-length ratio of MOS tube P7; (W / L) P8 is the width-to-length ratio of MOS tube P8; (W / L) P9 is the width-to-length ratio of MOS tube P9; (W / L) P10 is the width-to-length ratio of the MOS tube P19;

[0017] (W / L) N2 is the width-to-length ratio of MOS tube N2; (W / L) N4 is the width-to-length ratio of MOS tube N4; (W / L) N5 is the width-to-length ratio of MOS tube N5; (W / L) N6 is the width-to-length ratio of the MOS tube N6, and m and n are proportional coefficients.

[0018] Further, the startup module includes an operational amplifier U100, a NOR gate U101, a MOS transistor P0, a MOS transistor P1, a MOS transistor P4, a MOS transistor N0, a MOS transistor N3, a MOS transistor N8 and a MOS transistor N10;

[0019] The non-inverting input terminal of the operational amplifier U100 is connected to the external bias voltage V ref The reverse input terminal of the operational amplifier U100 is electrically connected to the external input enable signal; the output terminal of the operational amplifier U100 is electrically connected to the first input terminal of the NOR gate U101, and the second input terminal of the NOR gate U101 is electrically connected to the external low-level input.

[0020] The output end of the NOR gate U101 is electrically connected to the gate of the MOS transistor P0, the gate of the MOS transistor N0, the gate of the MOS transistor N3, the gate of the MOS transistor N8 and the gate of the MOS transistor N10; the drain of the MOS transistor N3 is electrically connected to the drain of the MOS transistor P3, the drain and the gate of the MOS transistor N2, the gate of the MOS transistor N4, the gate of the MOS transistor N5 and the gate of the MOS transistor N6 as the third control end; the drain of the MOS transistor N8 is electrically connected to the drain of the MOS transistor P10 and the drain of the MOS transistor N7 and the other end of the capacitor C0 as the fourth output end; the drain of the MOS transistor N10 is electrically connected to the output module as the fifth output end;

[0021] The source of the MOS transistor P0, the source of the MOS transistor P1 and the source of the MOS transistor P4 are all electrically connected to the external power supply VCC;

[0022] The drain of the MOS transistor P0 is electrically connected to the gate of the MOS transistor P1, the gate of the MOS transistor P4 and the drain of the MOS transistor N0; the drain of the MOS transistor P4 is electrically connected to the gate and drain of the MOS transistor P2, the gate of the MOS transistor P3, the drain of the MOS transistor N1 and the output module as a first control terminal; the drain of the MOS transistor P1 is electrically connected to the gate and drain of the MOS transistor P5, the gate of the MOS transistor P6, the gate of the MOS transistor P7, the gate of the MOS transistor P8, the gate of the MOS transistor P9, the gate of the MOS transistor P10 and the drain of the MOS transistor N6 as a second control terminal;

[0023] The source of the MOS transistor N0, the source of the MOS transistor N3, the source of the MOS transistor N8 and the source of the MOS transistor N10 are all grounded.

[0024] Furthermore, the following conditions are met:

[0025] (W / L) N0 =(W / L) N3 =(W / L) N7 =(W / L) N8 =(W / L) N10

[0026] Among them, (W / L) N0 is the width-to-length ratio of MOS tube N0; (W / L) N3 is the width-to-length ratio of MOS tube N3; (W / L) N7 is the width-to-length ratio of MOS tube N7; (W / L) N8 is the width-to-length ratio of MOS tube N8; (W / L) N10 is the width-to-length ratio of the MOS tube N10.

[0027] Further, the output module includes a NAND gate U102, a MOS transistor P11, a MOS transistor P12, a MOS transistor N9 and a MOS transistor N11;

[0028] The source of the MOS transistor P11 and the source of the MOS transistor P12 are both electrically connected to the external power supply VCC;

[0029] The gate of the MOS tube P11 is electrically connected to the other end of the capacitor C0 and connected to V A voltage; the drain of the MOS tube P11 is electrically connected to the drain of the MOS tube N9 and the first input terminal of the NAND gate U102; the second input terminal of the NAND gate U102 is electrically connected to the external low-level input;

[0030] The gate of the MOS transistor P12 is electrically connected to the gate and drain of the MOS transistor P2 and the gate of the MOS transistor N1, and the drain of the MOS transistor P12 is electrically connected to the drain and gate of the MOS transistor N10, the gate of the MOS transistor N9 and the fifth control terminal of the startup module;

[0031] The source of the MOS transistor N9 and the source of the MOS transistor N11 are both grounded.

[0032] Furthermore, the following conditions are met:

[0033] (W / L) P2 =(W / L) P3 =(W / L) P12

[0034] (W / L) N9 =(W / L) N11

[0035] Among them, (W / L) P2 is the width-to-length ratio of MOS tube P2; (W / L) P3 is the width-to-length ratio of MOS tube P3; (W / L) P12 is the width-to-length ratio of the MOS tube P12;

[0036] (W / L) N9 is the width-to-length ratio of MOS tube N9; (W / L) N11 is the width-to-length ratio of the MOS tube N11.

[0037] After adopting the above technical solution, the utility model has the following advantages compared with the background technology:

[0038] By using the current mirror structure of MOS tube P2, MOS tube P3, MOS tube N2, MOS tube N4, MOS tube N5, MOS tube N6, MOS tube P5, MOS tube P6, MOS tube P7, MOS tube P8, MOS tube P9 and MOS tube P10, and realizing time delay control according to the time characteristics of charging and discharging of capacitor C0, it can quickly respond to timeout events and quickly stop corresponding actions, and has high stability under steady-state and transient operation, reduces the influence of external environmental conditions and signal interference, and timeout detection has high detection accuracy and reliability. At the same time, it has a reset function, realizes continuous detection of timeout events, and flexibly adjusts the detection time according to the current mirror replication ratio, and has better practicality. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] Figure 1 It is a structural schematic diagram of the timeout detection circuit applied to the CAN transceiver chip described in the utility model;

[0040] Figure 2V is the timeout detection circuit applied to the CAN transceiver chip of the utility model. A Voltage variation curve diagram;

[0041] Figure 3 The gate-source voltage V of the MOS tube P11 used in the timeout detection circuit of the CAN transceiver chip described in the utility model is gsp Change curve chart;

[0042] Figure 4 The output voltage variation curve diagram of the timeout detection circuit applied to the CAN transceiver chip described in the utility model.

[0043] Description of reference numerals:

[0044] 1. Start-up module; 2. Charging module; 3. Output module. DETAILED DESCRIPTION

[0045] In order to make the purpose, technical solution and advantages of the utility model more clear, the utility model is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described here are only used to explain the utility model and are not used to limit the utility model.

[0046] In addition, it should be noted that the terms "up", "down", "left", "right", "vertical", "horizontal", "inside", "outside", etc. are based on the orientation or position relationship shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element of the present invention must have a specific orientation, and therefore cannot be understood as a limitation on the present invention.

[0047] When an element is referred to as being “fixed to” or “disposed on” or “provided on” another element, it may be directly on the other element or indirectly on the other element. When an element is referred to as being “connected to” another element, it may be directly connected to the other element or indirectly connected to the other element.

[0048] Unless otherwise clearly specified and limited, the terms "installed", "connected" and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in the utility model can be understood according to specific circumstances.

[0049] Example

[0050] Please refer to Figure 1As shown, this embodiment provides a timeout detection circuit applied to a CAN transceiver chip, including a starting module 1, a charging module 2 and an output module 3; the starting module 1, the charging module 2 and the output module 3 are all electrically connected to an external power supply VCC, the first control end, the second control end, the third control end and the fourth control end of the starting module 1 are electrically connected to the charging module 2, the fifth control end of the starting module 1 is electrically connected to the output module 3, and the output end of the charging module 2 is electrically connected to the output module 3.

[0051] Specifically, the charging module 2 includes MOS transistor P2, MOS transistor P3, MOS transistor P5, MOS transistor P6, MOS transistor P7, MOS transistor P8, MOS transistor P9, MOS transistor P10, MOS transistor N1, MOS transistor N2, MOS transistor N4, MOS transistor N5, MOS transistor N6, MOS transistor N7 and capacitor C0;

[0052] The source of the MOS transistor P2, the source of the MOS transistor P3, the source of the MOS transistor P5, the source of the MOS transistor P6, and one end of the capacitor C0 are all electrically connected to the start-up module 1, the output module 3 and the external power supply VCC;

[0053] The first control end of the start-up module 1 is electrically connected to the gate and drain of the MOS transistor P2, the gate of the MOS transistor P3, the drain of the MOS transistor N1 and the output module 3; the second control end of the start-up module 1 is electrically connected to the gate and drain of the MOS transistor P5, the gate of the MOS transistor P6, the gate of the MOS transistor P7, the gate of the MOS transistor P8, the gate of the MOS transistor P9, the gate of the MOS transistor P10 and the drain of the MOS transistor N6; the gate of the MOS transistor N1 is electrically connected to the external bias voltage V ref Electrical connection;

[0054] The drain of MOS tube P6 is electrically connected to the source of MOS tube P7; the drain of MOS tube P7 is electrically connected to the source of MOS tube P8; the drain of MOS tube P8 is electrically connected to the source of MOS tube P9; the drain of MOS tube P9 is electrically connected to the source of MOS tube P10; the drain of MOS tube P10 is electrically connected to the drain of MOS tube N7 and the other end of capacitor C0, and serves as an output end to output V A To output module 3; the gate of MOS tube N7 is connected to the external transmission data input V Datain Electrical connection;

[0055] The third control terminal of the start-up module 1 is electrically connected to the drain of the MOS transistor P3, the drain and gate of the MOS transistor N2, the gate of the MOS transistor N4, the gate of the MOS transistor N5 and the gate of the MOS transistor N6; the fourth control terminal of the start-up module 1 is electrically connected to the other end of the capacitor C0; the fifth control terminal of the start-up module 1 is electrically connected to the output module 3; the drain of the MOS transistor N4 is electrically connected to the source of the MOS transistor N5, and the drain of the MOS transistor N5 is electrically connected to the source of the MOS transistor N6;

[0056] The source of the MOS transistor N1 , the source of the MOS transistor N2 , the source of the MOS transistor N3 , the source of the MOS transistor N4 , and the source of the MOS transistor N7 are all grounded.

[0057] Specifically, the startup module 1 includes an operational amplifier U100, a NOR gate U101, a MOS transistor P0, a MOS transistor P1, a MOS transistor P4, a MOS transistor N0, a MOS transistor N3, a MOS transistor N8 and a MOS transistor N10.

[0058] The non-inverting input terminal of the operational amplifier U100 is connected to the external bias voltage V ref The reverse input terminal of the operational amplifier U100 is electrically connected to the external input enable signal EN; the output terminal of the operational amplifier U100 is electrically connected to the first input terminal of the NOR gate U101, and the second input terminal of the NOR gate U101 is electrically connected to the external low level input VL.

[0059] The output end of the NOR gate U101 is electrically connected to the gate of the MOS transistor P0, the gate of the MOS transistor N0, the gate of the MOS transistor N3, the gate of the MOS transistor N8, and the gate of the MOS transistor N10. The drain of the MOS transistor N3 is electrically connected to the drain of the MOS transistor P3, the drain and the gate of the MOS transistor N2, the gate of the MOS transistor N4, the gate of the MOS transistor N5, and the gate of the MOS transistor N6 as the third control end. The drain of the MOS transistor N8 is electrically connected to the drain of the MOS transistor P10, the drain of the MOS transistor N7, and the other end of the capacitor C0 as the fourth output end. The drain of the MOS transistor N10 is electrically connected to the output module 3 as the fifth output end.

[0060] The source of the MOS transistor P0 , the source of the MOS transistor P1 , and the source of the MOS transistor P4 are all electrically connected to the external power source VCC.

[0061] The drain of MOS transistor P0 is electrically connected to the gate of MOS transistor P1, the gate of MOS transistor P4 and the drain of MOS transistor N0. The drain of MOS transistor P4 is electrically connected to the gate and drain of MOS transistor P2, the gate of MOS transistor P3, the drain of MOS transistor N1 and the output module 3 as a first control terminal. The drain of MOS transistor P1 is electrically connected to the gate and drain of MOS transistor P5, the gate of MOS transistor P6, the gate of MOS transistor P7, the gate of MOS transistor P8, the gate of MOS transistor P9, the gate of MOS transistor P10 and the drain of MOS transistor N6 as a second control terminal. The source of MOS transistor N0, the source of MOS transistor N3, the source of MOS transistor N8 and the source of MOS transistor N10 are all grounded.

[0062] The start-up module 1 controls the start-up and shutdown of the charging module 2 and the output module 3 according to the external input enable signal EN. When the external input enable signal EN is at a low level, the start-up module 1 outputs a high level, the MOS tubes P1, P4, N3, N8 and N10 are turned off, and the charging module 2 and the output module 3 are started. When the external input enable signal EN is at a high level, the start-up module 1 outputs a low level, the MOS tubes P1, P4, N3, N8 and N10 are turned on, and the charging module 2 and the output module 3 are turned off.

[0063] Specifically, the output module 3 includes a NAND gate U102 , a MOS transistor P11 , a MOS transistor P12 , a MOS transistor N9 , and a MOS transistor N11 .

[0064] The source of the MOS transistor P11 and the source of the MOS transistor P12 are both electrically connected to the external power source VCC.

[0065] The gate of MOS tube P11 is electrically connected to the other end of capacitor C0 and connected to V A The drain of the MOS tube P11 is electrically connected to the drain of the MOS tube N9 and the first input terminal of the NAND gate U102; the second input terminal of the NAND gate U102 is electrically connected to the external low level input.

[0066] The gate of MOS transistor P12 is electrically connected to the gate and drain of MOS transistor P2 and the gate of MOS transistor N1, and the drain of MOS transistor P12 is electrically connected to the drain and gate of MOS transistor N10, the gate of MOS transistor N9 and the fifth control terminal of the start-up module 1, that is, the drain of MOS transistor P12 is electrically connected to the drain and gate of MOS transistor N10, the gate of MOS transistor N9 and the drain of MOS transistor N10. The source of MOS transistor N9 and the source of MOS transistor N11 are both grounded.

[0067] External bias voltage V ref Input MOS tube N1 gate, the current flowing through MOS tube N1 is Iref , is the reference current, after being copied by MOS tube P2, MOS tube P3, MOS tube N2, MOS tube N4, MOS tube N5, MOS tube N6, MOS tube P5, MOS tube P6, MOS tube P7, MOS tube P8, MOS tube P9 and MOS tube P10, the capacitor C0 is charged through point A, and the charging current is I OUT By changing the voltage difference between point A and the power supply, the switch state of the MOS tube P11 is controlled, thereby changing the output signal of the NOR gate U102.

[0068] In this embodiment, the MOS transistor P0, MOS transistor P1, MOS transistor P2, MOS transistor P3, MOS transistor P4, MOS transistor P5, MOS transistor P6, MOS transistor P7, MOS transistor P8, MOS transistor P9, MOS transistor P10, MOS transistor P11 and MOS transistor P12 are all PMOS transistors. In this embodiment, the body potential of the MOS transistor P0, MOS transistor P1, MOS transistor P2, MOS transistor P3, MOS transistor P4, MOS transistor P5, MOS transistor P6, MOS transistor P7, MOS transistor P8, MOS transistor P9, MOS transistor P10, MOS transistor P11 and MOS transistor P12 is equal to the source potential.

[0069] MOS transistor N0, MOS transistor N1, MOS transistor N2, MOS transistor N3, MOS transistor N4, MOS transistor N5, MOS transistor N6, MOS transistor N7, MOS transistor N8, MOS transistor N9, MOS transistor N10 and MOS transistor N11 are all NMOS transistors. In this embodiment, the substrate potential and the source potential of MOS transistor N0, MOS transistor N1, MOS transistor N2, MOS transistor N3, MOS transistor N4, MOS transistor N5, MOS transistor N6, MOS transistor N7, MOS transistor N8, MOS transistor N9, MOS transistor N10 and MOS transistor N11 are equal.

[0070] And the following conditions are met,

[0071] (W / L) P5 =m*(W / L) P6 =m*(W / L) P7 =m*(W / L) P8 =m*(W / L) P9 =m*(W / L) P10

[0072] (W / L) N2 =n*(W / L) N4 =n*(W / L) N5 =n*(W / L) N6

[0073] (W / L) N0 =(W / L)N3 =(W / L) N7 =(W / L) N8 =(W / L) N10

[0074] (W / L) P2 =(W / L) P3 =(W / L) P12

[0075] (W / L) N9 =(W / L) N11

[0076] Among them, (W / L) P2 is the width-to-length ratio of MOS tube P2; (W / L) P3 is the width-to-length ratio of MOS tube P3; (W / L) P5 is the width-to-length ratio of MOS tube P5; (W / L) P6 is the width-to-length ratio of MOS tube P6; (W / L) P7 is the width-to-length ratio of MOS tube P7; (W / L) P8 is the width-to-length ratio of MOS tube P8; (W / L) P9 is the width-to-length ratio of MOS tube P9; (W / L) P10 is the width-to-length ratio of MOS tube P19; (W / L) P12 is the width-to-length ratio of the MOS tube P12.

[0077] (W / L) N0 is the width-to-length ratio of MOS tube N0; (W / L) N2 is the width-to-length ratio of MOS tube N2; (W / L) N3 is the width-to-length ratio of MOS tube N3; (W / L) N4 is the width-to-length ratio of MOS tube N4; (W / L) N5 is the width-to-length ratio of MOS tube N5; (W / L) N6 is the width-to-length ratio of MOS tube N6, (W / L) N7 is the width-to-length ratio of MOS tube N7; (W / L) N8 is the width-to-length ratio of MOS tube N8; (W / L) N9 is the width-to-length ratio of MOS tube N9; (W / L) N10 is the width-to-length ratio of MOS tube N10; (W / L) N11 is the width-to-length ratio of the MOS tube N11.

[0078] m and n are proportionality coefficients.

[0079] From the above, we can get

[0080] I ref =I P2 =IP3 =I N2 =3n*I N4

[0081] I out =I P6 =I P7 =I P8 =I P9 =I P10 =(1 / 5m)*I P5

[0082] I N4 =I P5

[0083] but

[0084] I ref :I out =15mn:1

[0085] In the initial state, the potential at point A is V A =0, NOR gate U102 outputs V tdom =L (low level), external transmission data input V Datain =L, the capacitance of capacitor C0 is C. As time t increases, V A The electric potential gradually rises.

[0086]

[0087] When the gate-source voltage V gsp Less than or equal to the threshold voltage V of MOS tube P11 thp That is V A -VCC≤V thp When the MOS tube P11 is turned off, the drain voltage changes from H (high level) to L, and the NOR gate U102 outputs V tdom =H, the circuit outputs a timeout signal and the bus enters a recessive state through the internal control module of the CAN transceiver chip, that is, the circuit sets the timeout time t dom The formula is as follows:

[0088] t dom =15mn*(V thp +VCC)*C / I ref

[0089] When the timeout event ends, the external transmission data input V Datain =H, MOS tube N7 is turned on, capacitor C0 is discharged, V A The potential returns to zero, the MOS tube P11 resumes the on state, the drain potential of the MOS tube P11 changes from L to H, and the NOR gate U102 outputs V tdom=L, the circuit outputs a timeout event end signal flag, and the timeout detection circuit waits for the next corresponding timeout event to occur.

[0090] Please refer to Figure 2-4 As shown, Figure 2 V A Voltage variation curve, from the attached Figure 2 It can be seen that the potential at point A gradually increases with the increase of charging time t, and reaches the circuit setting timeout time t dom When the voltage rises to the critical voltage (VCC+V thp ), if t=t dom If the timeout response is not completed, capacitor C0 continues to charge until point A reaches the maximum potential VCC.

[0091] Among them, Figure 3 is the gate-source voltage of MOS tube P11 V gsp The change curve is shown in the attached Figure 3 It can be seen that the gate-source voltage of MOS tube P11 is V gsp With the potential V A The increase gradually decreases and at t = t dom When it is equal to the threshold voltage V of MOS tube P11 thp , MOS tube P11 is turned off. If t=t dom After the timeout response is not completed, the capacitor C0 continues to charge until the maximum potential VCC is reached at point A. At this time, V gsp =0.

[0092] Among them, Figure 4 The output voltage variation curve is shown in the attached figure. Figure 4 It can be seen that when no timeout event occurs, V tdom Output low level VL, when a timeout event occurs V tdom The output goes high, VH, and resets back to low, VL, at the end of the timeout event.

[0093] By using the current mirror structure of MOS tube P2, MOS tube P3, MOS tube N2, MOS tube N4, MOS tube N5, MOS tube N6, MOS tube P5, MOS tube P6, MOS tube P7, MOS tube P8, MOS tube P9 and MOS tube P10, and realizing time delay control according to the time characteristics of charging and discharging of capacitor C0, it can quickly respond to timeout events and quickly stop corresponding actions, and has high stability under steady-state and transient operation, reduces the influence of external environmental conditions and signal interference, and timeout detection has high detection accuracy and reliability. At the same time, it has a reset function, realizes continuous detection of timeout events, and flexibly adjusts the detection time according to the current mirror replication ratio, and has better practicality.

[0094] The above is only a preferred specific implementation of the utility model, but the protection scope of the utility model is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed by the utility model should be included in the protection scope of the utility model. Therefore, the protection scope of the utility model should be based on the protection scope of the claims.

Claims

1. A timeout detection circuit applied to a CAN transceiver chip, characterized in that: Including starting module, charging module and output module; The charging module includes MOS transistor P2, MOS transistor P3, MOS transistor P5, MOS transistor P6, MOS transistor P7, MOS transistor P8, MOS transistor P9, MOS transistor P10, MOS transistor N1, MOS transistor N2, MOS transistor N4, MOS transistor N5, MOS transistor N6, MOS transistor N7 and capacitor C0; The source of the MOS transistor P2, the source of the MOS transistor P3, the source of the MOS transistor P5, the source of the MOS transistor P6, and one end of the capacitor C0 are all electrically connected to the startup module, the output module and the external power supply VCC; The first control end of the startup module is electrically connected to the gate and drain of MOS tube P2, the gate of MOS tube P3, the drain of MOS tube N1 and the output module; the second control end of the startup module is electrically connected to the gate and drain of MOS tube P5, the gate of MOS tube P6, the gate of MOS tube P7, the gate of MOS tube P8, the gate of MOS tube P9, the gate of MOS tube P10 and the drain of MOS tube N6; the gate of MOS tube N1 is electrically connected to the external bias voltage V ref Electrical connection; The drain of the MOS transistor P6 is electrically connected to the source of the MOS transistor P7; the drain of the MOS transistor P7 is electrically connected to the source of the MOS transistor P8; the drain of the MOS transistor P8 is electrically connected to the source of the MOS transistor P9; the drain of the MOS transistor P9 is electrically connected to the source of the MOS transistor P10; the drain of the MOS transistor P10 is electrically connected to the drain of the MOS transistor N7 and the other end of the capacitor C0, and serves as an output end to output V A To the output module; the gate of the MOS tube N7 is connected to the external transmission data input V Datain Electrical connection; The third control terminal of the startup module is electrically connected to the drain of the MOS transistor P3, the drain and gate of the MOS transistor N2, the gate of the MOS transistor N4, the gate of the MOS transistor N5 and the gate of the MOS transistor N6; the fourth control terminal of the startup module is electrically connected to the other end of the capacitor C0; the fifth control terminal of the startup module is electrically connected to the output module; the drain of the MOS transistor N4 is electrically connected to the source of the MOS transistor N5, and the drain of the MOS transistor N5 is electrically connected to the source of the MOS transistor N6; The source of the MOS transistor N1 , the source of the MOS transistor N2 , the source of the MOS transistor N3 , the source of the MOS transistor N4 and the source of the MOS transistor N7 are all grounded.

2. The timeout detection circuit applied to a CAN transceiver chip according to claim 1, characterized in that: Satisfy the following conditions: (W / L) P5 =m*(W / L) P6 =m*(W / L) P7 =m*(W / L) P8 =m*(W / L) P9 =m*(W / L) P10 (W / L) N2 =n*(W / L) N4 =n*(W / L) N5 =n*(W / L) N6 Among them, (W / L) P5 is the width-to-length ratio of MOS tube P5; (W / L) P6 is the width-to-length ratio of MOS tube P6; (W / L) P7 is the width-to-length ratio of MOS tube P7; (W / L) P8 is the width-to-length ratio of MOS tube P8; (W / L) P9 is the width-to-length ratio of MOS tube P9; (W / L) P10 is the width-to-length ratio of the MOS tube P19; (W / L) N2 is the width-to-length ratio of MOS tube N2; (W / L) N4 is the width-to-length ratio of MOS tube N4; (W / L) N5 is the width-to-length ratio of MOS tube N5; (W / L) N6 is the width-to-length ratio of the MOS tube N6, and m and n are proportional coefficients.

3. The timeout detection circuit applied to a CAN transceiver chip according to claim 1, characterized in that: The startup module includes an operational amplifier U100, a NOR gate U101, a MOS transistor P0, a MOS transistor P1, a MOS transistor P4, a MOS transistor N0, a MOS transistor N3, a MOS transistor N8 and a MOS transistor N10; The non-inverting input terminal of the operational amplifier U100 is connected to the external bias voltage V ref The reverse input terminal of the operational amplifier U100 is electrically connected to the external input enable signal; the output terminal of the operational amplifier U100 is electrically connected to the first input terminal of the NOR gate U101, and the second input terminal of the NOR gate U101 is electrically connected to the external low-level input. The output end of the NOR gate U101 is electrically connected to the gate of the MOS transistor P0, the gate of the MOS transistor N0, the gate of the MOS transistor N3, the gate of the MOS transistor N8 and the gate of the MOS transistor N10; the drain of the MOS transistor N3 is electrically connected to the drain of the MOS transistor P3, the drain and the gate of the MOS transistor N2, the gate of the MOS transistor N4, the gate of the MOS transistor N5 and the gate of the MOS transistor N6 as the third control end; the drain of the MOS transistor N8 is electrically connected to the drain of the MOS transistor P10 and the drain of the MOS transistor N7 and the other end of the capacitor C0 as the fourth output end; the drain of the MOS transistor N10 is electrically connected to the output module as the fifth output end; The source of the MOS transistor P0, the source of the MOS transistor P1 and the source of the MOS transistor P4 are all electrically connected to the external power supply VCC; The drain of the MOS transistor P0 is electrically connected to the gate of the MOS transistor P1, the gate of the MOS transistor P4 and the drain of the MOS transistor N0; the drain of the MOS transistor P4 is electrically connected to the gate and drain of the MOS transistor P2, the gate of the MOS transistor P3, the drain of the MOS transistor N1 and the output module as a first control terminal; the drain of the MOS transistor P1 is electrically connected to the gate and drain of the MOS transistor P5, the gate of the MOS transistor P6, the gate of the MOS transistor P7, the gate of the MOS transistor P8, the gate of the MOS transistor P9, the gate of the MOS transistor P10 and the drain of the MOS transistor N6 as a second control terminal; The source of the MOS transistor N0, the source of the MOS transistor N3, the source of the MOS transistor N8 and the source of the MOS transistor N10 are all grounded.

4. The timeout detection circuit applied to a CAN transceiver chip according to claim 3, characterized in that: Satisfy the following conditions: (W / L) N0 =(W / L) N3 =(W / L) N7 =(W / L) N8 =(W / L) N10 Among them, (W / L) N0 is the width-to-length ratio of MOS tube N0; (W / L) N3 is the width-to-length ratio of MOS tube N3; (W / L) N7 is the width-to-length ratio of MOS tube N7; (W / L) N8 is the width-to-length ratio of MOS tube N8; (W / L) N10 is the width-to-length ratio of the MOS tube N10.

5. The timeout detection circuit applied to a CAN transceiver chip according to claim 1, characterized in that: The output module includes a NAND gate U102, a MOS transistor P11, a MOS transistor P12, a MOS transistor N9 and a MOS transistor N11; The source of the MOS transistor P11 and the source of the MOS transistor P12 are both electrically connected to the external power supply VCC; The gate of the MOS tube P11 is electrically connected to the other end of the capacitor C0 and connected to V A voltage; the drain of the MOS tube P11 is electrically connected to the drain of the MOS tube N9 and the first input terminal of the NAND gate U102; the second input terminal of the NAND gate U102 is electrically connected to the external low-level input; The gate of the MOS transistor P12 is electrically connected to the gate and drain of the MOS transistor P2 and the gate of the MOS transistor N1, and the drain of the MOS transistor P12 is electrically connected to the drain and gate of the MOS transistor N10, the gate of the MOS transistor N9 and the fifth control terminal of the startup module; The source of the MOS transistor N9 and the source of the MOS transistor N11 are both grounded.

6. The timeout detection circuit applied to a CAN transceiver chip according to claim 5, characterized in that: Satisfy the following conditions: (W / L) P2 =(W / L) P3 =(W / L) P12 (W / L) N9 =(W / L) N11 Among them, (W / L) P2 is the width-to-length ratio of MOS tube P2; (W / L) P3 is the width-to-length ratio of MOS tube P3; (W / L) P12 is the width-to-length ratio of the MOS tube P12; (W / L) N9 is the width-to-length ratio of MOS tube N9; (W / L) N11 is the width-to-length ratio of the MOS tube N11.

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