A TTE analyzer working circuit

Abstract

The utility model proposes a TTE analyzer working circuit, which is used for monitoring, diagnosing and troubleshooting TTE network equipment, and completing the verification of TTE network system protocols. It has bypass mode to capture real-time traffic, nanosecond timestamps, single-port storage capacity of up to 1024M bytes, and supports functions such as custom field search, filtering and traffic analysis. Through reasonable connection and configuration of each component, efficient data transmission and processing capabilities are achieved. The circuit receives and processes network data from a multi-channel data acquisition circuit board through the PEX8648 switching module, the power management module ensures stable power supply for each module, and the clock management module provides a high-precision clock signal to ensure the synchronization and stable operation of the system. The utility model has a compact structure and powerful functions, and is suitable for various application scenarios that require high real-time and high-reliability data transmission, especially for aerospace and industrial automation fields.

Description

Technical Field

[0001] The utility model relates to the technical field of network data transmission, in particular to a TTE analyzer working circuit. Background Art

[0002] With the development of modern network environment, higher requirements are put forward for the real-time and stability of signal transmission. Especially in the field of aerospace, the demand for high bandwidth, low latency and high reliability is increasing. At present, Ethernet technology, as the most common network communication standard protocol, is widely used in various local area networks. However, the data transmission in the Ethernet standard is competitive and cannot control data transmission in real time and reliably. Therefore, it is not suitable for direct application in fields such as aerospace and industrial control that require high real-time and high reliability.

[0003] Time-triggered Ethernet (TTE) technology is a data transmission solution for aerospace and industrial automation. TTE can provide a high-bandwidth and low-latency network environment while ensuring the real-time and deterministic nature of data transmission. Therefore, it is of great practical significance to develop a TTE analyzer working circuit that can monitor, diagnose and troubleshoot TTE network devices and support protocol verification and real-time traffic capture. Utility Model Content

[0004] The utility model aims to at least solve the technical problems existing in the prior art, and particularly innovatively proposes a TTE analyzer working circuit for monitoring, diagnosing and troubleshooting TTE network equipment, and completes the verification of the TTE network system protocol, supports bypass mode to capture real-time traffic, and has nanosecond timestamps, a single-port storage capacity of up to 1024M bytes, and supports functions such as custom field search, filtering and traffic analysis.

[0005] In order to achieve the above-mentioned purpose of the utility model, the utility model provides a TTE analyzer working circuit, such as Figures 1 to 16As shown, a TTE analyzer working circuit includes a data processing circuit board, a data acquisition circuit board, a backplane, a power board, a PEX8648 switching module, a T1042 data processing module VPX connector, an RJ45 network port, a DB9 serial port, an FPGA module, an LVDS switch, and an SFP network transmission interface. The data processing circuit board, the data acquisition circuit board, and the power board are all connected to the backplane through the VPX connector. The network port end of the data processing circuit board is connected to the host computer through the RJ45 network port, the VPX connector end of the data processing circuit board is connected to the backplane, and data is exchanged with the data acquisition circuit board on the backplane. The data acquisition circuit board is connected to the TTE network through the SFP network transmission interface, the data acquisition circuit board is connected to the backplane through the VPX interface, and data is exchanged with the data processing circuit board on the backplane. The power board is connected to the backplane to supply power to the data acquisition circuit board and the data processing circuit board.

[0006] In the above scheme: the data processing circuit board is as follows: Figure 3 As shown, it includes T1042 data processing module, PEX8648 switching module, DB9 serial port, RJ54 Ethernet port, VPX connector and power management module. PEX8648 switching module is connected to VPX connector through 4 PCIE X4 ports to receive network data transmitted from 4 data acquisition circuit boards. PEX8648 switching module is connected to VPX connector through 1 PCIE The X4 interface is connected to the T1042 data processing module, and forwards the data transmitted by the bus to the PEX8648 switching module to the T1042 data processing module. The T1042 data processing module is connected to the Ethernet interface RJ45 and sends the Ethernet signal to the host computer through the RJ45 Ethernet interface. The T1042 data processing module is connected to the DB9 serial port and can accept serial port signals for control and debugging. The PEX8648 is connected to the lamp holder and serves as an indicator for the normal operation of the module. The power management module is connected to the power board through the VPX connector, obtains the 12V power supply voltage from the power board and converts the 12V voltage into 3.3V voltage to power the entire data processing circuit board. The power management module is connected to the lamp holder and serves as an indicator for normal power supply.

[0007] In the above scheme, the data acquisition circuit board is as follows Figure 4The system shown includes an FPGA module, an LVDS switch, an SFP network transmission interface, a VPX connector, two 2GB DDR3 memories, two FLASHs (256Mb) and a power management module. The FPGA module interacts with the data processing circuit board through PCIE and is interconnected with three other data acquisition circuit boards through LVDS. One of the two FLASHs is used as the FPGA program storage and the other stores network parameters. The FPGA module is connected to the SFP network transmission interface through the LVDS switch and interacts with the TTE network environment. The FPGA module is connected to the indicator light through the GPIO interface to indicate the working status. The power management module converts the 12V voltage of the power board into a 3.3V voltage for powering the data acquisition circuit board.

[0008] In the above scheme, the data acquisition circuit board and the data processing circuit board include a power management module, such as Fig.15 As shown, the voltage output pin VOUT3_0 of the buck regulator chip D12, the voltage output pin VOUT3_1 of the buck regulator chip D12, the voltage output pin VOUT3_2 of the buck regulator chip D12, the voltage output pin VOUT4_0 of the buck regulator chip D12, the voltage output pin VOUT4_1 of the buck regulator chip D12 and the voltage output pin VOUT4_2 of the buck regulator chip D12 output the power supply voltage VCC1V_VINT and are connected to the first end of the capacitor C281 and the first end of the capacitor C284, the second end of the capacitor C281 and the second end of the capacitor C284 are grounded, and the feedback pin FB3 of the buck regulator chip D12 and the feedback pin FB4 of the buck regulator chip D12 are connected to the first end of the resistor R143 and the resistor R144. 46, the second end of the resistor R143 and the second end of the resistor R146 are grounded, the voltage tracking and soft-start pin TRACK|SS3 of the buck regulator chip D12 and the voltage tracking and soft-start pin TRACK|SS4 of the buck regulator chip D12 are connected to the first end of the capacitor C278, the second end of the capacitor C278 is grounded, the power good indication terminal PGOOD3 of the buck regulator chip D12 is connected to the first end of the resistor R141, the second end of the resistor R141 is connected to the internal power pin INTVCC3 of the buck regulator chip D12, the power good indication terminal PGOOD4 of the buck regulator chip D12 is connected to the first end of the resistor R142, and the second end of the resistor R142 is connected to the internal power pin INTVCC4 of the buck regulator chip D12;

[0009] The voltage input pin VIN3_0 of the buck regulator chip D12, the voltage input pin VIN3_1 of the buck regulator chip D12, the voltage input pin SVIN3 of the buck regulator chip D12, and the enable pin RUN3 of the buck regulator chip D12 are connected to the power supply voltage VCC5V and the first end of the capacitor C274, the second end of the capacitor C274 is grounded, the voltage input pin VIN4_0 of the buck regulator chip D12, the voltage input pin VIN4_1 of the buck regulator chip D12, and the enable pin RUN3 of the buck regulator chip D12 are connected to the power supply voltage VCC5V and the first end of the capacitor C274, the second end of the capacitor C274 is grounded, and ...1 of the buck regulator chip D12 The voltage input pin SVIN4 of the buck regulator chip D12 and the enable pin RUN4 of the buck regulator chip D12 are connected to the power supply voltage VCC5V and the first end of the capacitor C275, the second end of the capacitor C275 is grounded, the internal power pin INTVCC3 of the buck regulator chip D12 is connected to the working mode configuration pin MODE3 of the buck regulator chip D12, and the internal power pin INTVCC4 of the buck regulator chip D12 is connected to the working mode configuration pin MODE4 of the buck regulator chip D12;

[0010] The ground pin SGND of the buck regulator chip D12, the ground pin GND_0 of the buck regulator chip D12, the ground pin GND_1 of the buck regulator chip D12, the ground pin GND_2 of the buck regulator chip D12, the ground pin GND_3 of the buck regulator chip D12, the ground pin GND_4 of the buck regulator chip D12, the ground pin GND_5 of the buck regulator chip D12, the ground pin GND_6 of the buck regulator chip D12, the ground pin GND_7 of the buck regulator chip D12, the ground pin GND_8 of the buck regulator chip D12, the ground pin GND_9 of the buck regulator chip D The ground pin GND_10 of the buck regulator chip D12, the ground pin GND_11 of the buck regulator chip D12, the ground pin GND_12 of the buck regulator chip D12, the ground pin GND_13 of the buck regulator chip D12, the ground pin GND_14 of the buck regulator chip D12, the ground pin GND_15 of the buck regulator chip D12, the ground pin GND_16 of the buck regulator chip D12, the ground pin GND_17 of the buck regulator chip D12, the ground pin GND_18 of the buck regulator chip D12, the ground pin GND_19 of the buck regulator chip D12, and the ground pin GND_20 of the buck regulator chip D12 are all grounded. The input power supply voltage VCC5V is converted into a stable power supply voltage VCC1V_ for output through the buck regulator chip D12.

[0011] The voltage output pin VOUT1_0 of the buck regulator chip D12, the voltage output pin VOUT1_1 of the buck regulator chip D12 and the voltage output pin VOUT1_2 of the buck regulator chip D12 output the power supply voltage VCC1.8V and are connected to the first end of the capacitor C279 and the first end of the capacitor C282, the second end of the capacitor C279 and the second end of the capacitor C282 are grounded, the feedback pin FB1 of the buck regulator chip D12 is connected to the first end of the resistor R144, the second end of the resistor R144 is grounded, the voltage tracking and soft start pin TRACK|SS1 of the buck regulator chip D12 is connected to the first end of the capacitor C276, the second end of the capacitor C276 is grounded, the power good indication pin PGOOD1 of the buck regulator chip D12 is connected to the first end of the resistor R139, and the second end of the resistor R139 is connected to the internal power pin INTVCC1 of the buck regulator chip D12;

[0012] The voltage output pin VOUT2_0 of the buck regulator chip D12, the voltage output pin VOUT2_1 of the buck regulator chip D12 and the voltage output pin VOUT2_2 of the buck regulator chip D12 output the power supply voltage VCC1.5V and are connected to the first end of the capacitor C280 and the first end of the capacitor C283, the second end of the capacitor C280 and the second end of the capacitor C283 are grounded, the feedback pin FB2 of the buck regulator chip D12 is connected to the first end of the resistor R145, the second end of the resistor R145 is grounded, the voltage tracking and soft start pin TRACK|SS2 of the buck regulator chip D12 is connected to the first end of the capacitor C277, the second end of the capacitor C277 is grounded, the power good indication terminal PGOOD2 of the buck regulator chip D12 is connected to the first end of the resistor R140, and the second end of the resistor R140 is connected to the internal power pin INTVCC2 of the buck regulator chip D12;

[0013] The power good indication terminal PGOOD1 of the buck voltage regulator chip D12 is connected to the enable terminal RUN2 of the buck voltage regulator chip D12;

[0014] The voltage input pin VIN1_0 of the buck voltage regulator chip D12, the voltage input pin VIN1_1 of the buck voltage regulator chip D12, and the voltage input pin SVIN1 of the buck voltage regulator chip D12 are connected to the power supply voltage VCC5V and the first end of the capacitor C272, the second end of the capacitor C272 is grounded, and the power good indication terminal PGOOD3 of the buck voltage regulator chip D12 and the power good indication terminal PGOOD4 of the buck voltage regulator chip D12 are connected to the enable terminal RUN1 of the buck voltage regulator chip D12;

[0015] The voltage input pin VIN2_0 of the buck regulator chip D12, the voltage input pin VIN2_1 of the buck regulator chip D12, and the voltage input pin SVIN2 of the buck regulator chip D12 are connected to the power supply voltage VCC5V and the first end of the capacitor C273, and the second end of the capacitor C273 is grounded;

[0016] The internal power pin INTVCC1 of the buck regulator chip D12 is connected to the working mode configuration pin MODE1 of the buck regulator chip D12, and the internal power pin INTVCC2 of the buck regulator chip D12 is connected to the working mode configuration pin MODE2 of the buck regulator chip D12. The input power supply voltage VCC5V is converted into a stable power supply voltage VCC1.8V and VCC1.5V for output through the buck regulator chip D12.

[0017] In a preferred implementation manner of the present utility model, the model of the buck regulator chip D12 is LTM4644EY#PBF.

[0018] The clock management module includes a clock generator U1, a filter inductor, a filter capacitor, a voltage divider resistor, and a resistor-capacitor coupling network for impedance matching, and distributes the clock to the FPGA module through the clock generator U1;

[0019] The clock management module includes: an enable pin OE of the clock generator U1 is connected to the first end of the resistor R114, the second end of the resistor R114 is connected to the input voltage VCC3.3V, a voltage input pin VDD of the clock generator U1 is connected to the first end of the capacitor C244 and the second end of the inductor L5, the second end of the capacitor C244 is grounded, the first end of the inductor L5 is connected to the input voltage VCC3.3V, a clock output pin CLK of the clock generator U1 is connected to the FPGA module and the first end of the capacitor C255, the second end of the capacitor C255 is connected to the first end of the resistor R126, the first end of the resistor R127, the first end of the inductor L5, the second end of the inductor L5 is connected to the input voltage VCC3.3V, The first end of resistor R171 is connected to the FPGA module, the second end of resistor R126 is connected to the input voltage VCC1.5V, the second end of resistor R127 is grounded, the second end of resistor R171 is connected to the second end of capacitor C317, the clock output pin CLK* of clock generator U1 is connected to the first end of capacitor C317, the second end of capacitor C137 is connected to the first end of resistor R130, the first end of resistor R155 and the FPGA module, the second end of resistor R130 is connected to the input voltage VCC1.5V, the second end of resistor R155 is grounded, and the ground pin GND of clock generator U1 is grounded.

[0020] The above FPGA modules, such as Fig.11As shown, the processor chip D4 of the XC7K325T-2FFG900I model is used to manage various interface signals such as LVDS, PCIe, and JTAG. The LVDS interface is used for high-speed data transmission, the PCIE X4 interface realizes high-speed data communication with the host system, and the JTAG interface is used for programming and debugging.

[0021] The above PEX8648 switching module, such as Figure 6 As shown, it includes a switching chip U2, 4 PCIE X4 interfaces and a single PCIE X4 interface. The first end of the 4 PCIE X4 interface is connected to the VPX connector, the second end of the 4 PCIE X4 interface is connected to the switching chip U2, the first end of the single PCIE X4 interface is connected to the switching chip, and the second end of the single PCIE X4 interface is connected to the T1042 data processing module.

[0022] The above-mentioned PEX8648 switching module includes a network transmission indication pin of a U2 switching chip connected to an LED lamp holder to indicate the network transmission status.

[0023] The above T1042 data processing module, such as Figure 7As shown, the first end of capacitor C88, the first end of capacitor C89, the first end of capacitor C96, the first end of capacitor C98, the first end of capacitor C100, the first end of capacitor C102, the first end of capacitor C105, the first end of capacitor C108 and the first end of capacitor C111 are connected to the input voltage VCC3.3V and the voltage input pin VCC of processor IC1, the second end of capacitor C88, the second end of capacitor C89, the second end of capacitor C96, the second end of capacitor C98, the second end of capacitor C100, the second end of capacitor C102, the second end of capacitor C105, the second end of capacitor C108 and the second end of capacitor C111 are grounded and connected to the voltage input pin VCC of processor IC1, the first end of capacitor C106, the first end of capacitor C109 and the first end of capacitor C112 are connected to the input voltage VCC1.8V and the voltage input pin VCC of processor IC1 The first end of the resistor R152 is connected to the voltage input pin VCCQ of the processor IC1, the second end of the capacitor C106, the second end of the capacitor C109 and the second end of the capacitor C112 are grounded, the first end of the resistor R152 is connected to the input voltage VCC1.2V, the second end is connected to the first end of the capacitor C90, the first end of the capacitor C97, the first end of the capacitor C99, the first end of the capacitor C101, the first end of the capacitor C103, the first end of the capacitor C107, the first end of the capacitor C110, the first end of the capacitor C113, the voltage input pin VDDC of the processor IC1 and the voltage input pin VDD of the processor IC1, the second end of the capacitor C90, the second end of the capacitor C97, the second end of the capacitor C99, the second end of the capacitor C101, the second end of the capacitor C103, the second end of the capacitor C107, the second end of the capacitor C110 and the second end of the capacitor C113 are grounded;

[0024] The first SATA power supply pin SATA_VDD of the processor IC1 is connected to the first end of the capacitor C120, the first end of the capacitor C122, the first end of the capacitor C124 and the first end of the inductor L11, the second end of the capacitor C120, the second end of the capacitor C122 and the second end of the capacitor C124 are all grounded, and the second end of the inductor L11 is connected to the input voltage VCC1.2V;

[0025] The second SATA power supply pin SATA_VDD of the processor IC1 is connected to the first end of the capacitor C121, the first end of the capacitor C123, the first end of the capacitor C125 and the first end of the inductor L12, the second end of the capacitor C121, the second end of the capacitor C123 and the second end of the capacitor C125 are all grounded, and the second end of the inductor L12 is connected to the input voltage VCC1.2V;

[0026] The SATA voltage pin SATA_VSS of the processor IC1 is grounded, the sleep signal pin DEVSLP of the processor IC1 is connected to the first end of the resistor R155, the second end of the resistor R155 is grounded, when the pin receives the sleep signal, the device will enter the low power mode, the crystal oscillator output pin XTAL_OUT of the processor IC1 and the crystal oscillator input pin XTAL_IN of the processor IC1 are connected to the external crystal oscillator circuit, the power reset pin PWR_RESETN of the processor IC1 is connected to the first end of the resistor R158, the second end of the resistor R158 is connected to the external reset signal, and the power reset pin PWR_RESETN of the processor IC1 is connected to the external SATA power reset signal;

[0027] The spare pin NC34 of the processor IC1 is connected to the LED indicator light, and the spare pin NC37 of the processor IC1 and the spare pin NC38 of the processor IC1 are connected to the SATA device for receiving and sending control commands and data of the SATA device.

[0028] The first end of the above-mentioned VPX connector module is connected to the PEX8648 switching module of the data processing circuit board through a 4-way PCIE X4 interface, the second end of the VPX connector module is connected to the four data acquisition circuit boards through four single-way PCIE X4 interfaces, and the power transmission end of the VPX connector module is connected to the power board.

[0029] The above-mentioned RJ45 network port module includes an Ethernet interface ETH0, a network transmission indicator light and a capacitor filter network. The network signal transmission pins 1 to 8 of the Ethernet interface ETH0 are used for Gigabit Ethernet data transmission. The indicator light pin 9 of the Ethernet interface ETH0 receives the network activity signal GBE0_ACT_N. When there is data transmission, the LED light is on. The indicator light pin 9 of the Ethernet interface ETH0 is connected to the first end of the capacitor C6, and the second end of the capacitor C6 is grounded. The indicator light pin 10 of the Ethernet interface ETH0 is connected to the first end of the resistor R9, and the second end of the resistor R9 is connected to the input voltage LED_2V5.

[0030] The indicator light pin 11 of the Ethernet interface ETH0 receives the network connection signal LINK1000_N. When the link is successful, the LED light is on. The indicator light pin 11 of the Ethernet interface ETH0 is connected to the first end of the capacitor C4, and the second end of the capacitor C4 is grounded. The indicator light pin 12 of the Ethernet interface ETH0 is connected to the first end of the resistor R10, and the second end of the resistor R10 is connected to the input voltage LED_2V5;

[0031] The above data processing circuit board also includes a clock management module, such as Fig.14 and Fig.16The system shown includes a clock distribution chip D1 of model MC100LVE111FA, a clock generator U3, a decoupling capacitor for reducing power supply noise, a resistor network for impedance matching, and a resistor network for voltage division. These parts together constitute a clock management module for ensuring signal integrity and clock signal stability.

[0032] The control pin OE of the clock generator U3 is connected to the first end of the resistor R102, the second end of the resistor R102 is connected to the second end of the inductor L1, the first end of the capacitor C53 and the voltage input pin VDD of the clock generator U3, the first end of the inductor L1 is connected to the input voltage VCC3.3V, the second end of the capacitor C53 is grounded, the clock signal output pin CLK of the clock generator U3 is connected to the first end of the capacitor C58, the second end of the capacitor C58 is connected to the clock input pin CLK0 of the clock distribution chip D1, the clock signal output pin CLK* of the clock generator U3 is connected to the first end of the capacitor C95, the second end of the capacitor C95 is connected to the clock input pin CLK0* of the clock distribution chip D1, and the ground pin GND of the clock generator U3 is grounded.

[0033] The clock input pin CLK0 of the clock distribution chip D1 and the clock input pin CLK0* of the clock distribution chip D1 are connected to the clock signal output pin CLK of the clock generator U3 and the clock signal output pin CLK* of the clock generator U3 to receive the synchronous differential signal from the clock generator U3, the first end of the resistor R86 is connected to the input voltage VCC3.3V, the second end of the resistor R86 is connected to the first end of the resistor R87 and the clock input pin CLK0 of the clock distribution chip D1, the second end of the resistor R87 is grounded, the first end of the resistor R88 is connected to the input voltage VCC3.3V, the second end of the resistor R88 is connected to the first end of the resistor R89 ​​and the clock input pin CLK0* of the clock distribution chip D1, and the second end of the resistor R89 ​​is grounded;

[0034] The first end of the resistor R90 is connected to the clock input pin CLK1 of the clock distribution chip D1, the second end of the resistor R90 is grounded, the first end of the resistor R101 is connected to the clock input pin CLK1* of the clock distribution chip D1, the second end of the resistor R101 is grounded, the first end of the resistor R62 is connected to the clock selection pin CLK_SET of the clock distribution chip D1, the second end of the resistor R62 is grounded, the clock selection pin CLK_SET of the clock distribution chip D1 is connected to the clock selection signal, the first end of the capacitor C54, the first end of the capacitor C55, the The first end of capacitor C56 is connected to the input voltage VCC3.3V, the second end of capacitor C54, the second end of capacitor C55, and the second end of capacitor C56 are all grounded, the first end of capacitor C54 is also connected to the voltage input pin VCC0 of the clock distribution chip D1, the voltage input pin VCC1 of the clock distribution chip D1, the voltage input pin VCC2 of the clock distribution chip D1, the voltage input pin VCC3 of the clock distribution chip D1, and the voltage input pin VCC4 of the clock distribution chip D1, and the voltage pin VEE of the clock distribution chip D1 is grounded;

[0035] A first end of the resistor R103 is connected to a signal output pin Q0 of the clock distribution chip D1 and a first end of the capacitor C18, a second end of the resistor R103 is grounded, and a second end of the capacitor C18 is connected to a VPX connector, a first end of the resistor R104 is connected to a signal output pin Q0* of the clock distribution chip D1 and a first end of the capacitor C60, a second end of the resistor R104 is grounded, and a second end of the capacitor C60 is connected to a VPX connector, a first end of the resistor R1 is connected to a signal output pin Q1 of the clock distribution chip D1 and a first end of the capacitor C21, a second end of the resistor R1 is grounded, and a second end of the capacitor C21 is connected to the VPX connector, a first end of the resistor R8 is connected to a signal output pin Q1* of the clock distribution chip D1 and a first end of the capacitor C61, a second end of the resistor R8 is grounded, and a second end of the capacitor C61 is connected to the VPX connector, A first end of the resistor R21 is connected to a signal output pin Q2 of the clock distribution chip D1 and a first end of the capacitor C38, a second end of the resistor R21 is grounded, and a second end of the capacitor C38 is connected to a VPX connector, a first end of the resistor R35 is connected to a signal output pin Q2* of the clock distribution chip D1 and a first end of the capacitor C62, a second end of the resistor R35 is grounded, and a second end of the capacitor C62 is connected to the VPX connector, a first end of the resistor R36 is connected to a signal output pin Q3 of the clock distribution chip D1 and a first end of the capacitor C44, a second end of the resistor R36 is grounded, and a second end of the capacitor C44 is connected to the VPX connector, a first end of the resistor R57 is connected to a signal output pin Q3* of the clock distribution chip D1 and a first end of the capacitor C17, a second end of the resistor R57 is grounded, and a second end of the capacitor C17 is connected to the VPX connector;

[0036] The second end of the capacitor C18 is connected to the first end of the resistor R58 and the first end of the resistor R59, the second end of the resistor R58 is connected to the input voltage VCC3.3V, and the second end of the resistor R59 is grounded. The second end of the capacitor C60 is connected to the first end of the resistor R60 and the first end of the resistor R61, the second end of the resistor R60 is connected to the input voltage VCC3.3V, and the second end of the resistor R61 is grounded. The second end of the capacitor C21 is connected to the first end of the resistor R63 and the first end of the resistor R64, the second end of the resistor R63 is connected to the input voltage VCC3.3V, and the second end of the resistor R64 is grounded. The second end of the capacitor C61 is connected to the first end of the resistor R66 and the first end of the resistor R67, the second end of the resistor R66 is connected to the input voltage VCC3.3V, and the second end of the resistor R67 is grounded. The second end of capacitor C38 is connected to the first end of resistor R68 and the first end of resistor R69, the second end of resistor R68 is connected to the input voltage VCC3.3V, and the second end of resistor R69 is grounded. The second end of capacitor C62 is connected to the first end of resistor R70 and the first end of resistor R72, the second end of resistor R70 is connected to the input voltage VCC3.3V, and the second end of resistor R72 is grounded. The second end of capacitor C44 is connected to the first end of resistor R73 and the first end of resistor R74, the second end of resistor R73 is connected to the input voltage VCC3.3V, and the second end of resistor R74 is grounded. The second end of capacitor C17 is connected to the first end of resistor R75 and the first end of resistor R76, the second end of resistor R75 is connected to the input voltage VCC3.3V, and the second end of resistor R76 is grounded.

[0037] The clock management module in the utility model inputs a precisely synchronized clock signal to each module, so that the clock signal has a high degree of integrity and anti-interference.

[0038] The above FPGA modules, such as Fig.11 As shown, the processor chip D4 of the XC7K325T-2FFG900I model is used to manage various interface signals such as LVDS, PCIe, and JTAG. The LVDS interface is used for high-speed data transmission, the PCIE X4 interface realizes high-speed data communication with the host system, and the JTAG interface is used for programming and debugging.

[0039] The above SFP interface module, such as Fig.12 , Fig.13 As shown, the SFP module interface is connected to the LVD switch X4 via an Ethernet transmission line, and the LVD switch is connected to the FPGA module.

[0040] Through the combination of the above modules, the circuit board of the utility model realizes the integration of multiple high-speed interfaces, has a sufficiently high transmission bandwidth, efficient power management and precise clock synchronization to ensure higher signal integrity and transmission speed, as well as a user-friendly operation interface, which significantly improves the overall performance and applicability of the TTE network analyzer.

[0041] Additional aspects and advantages of the present invention will be given in part in the following description, and in part will become apparent from the following description, or will be learned through the practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] The above and / or additional aspects and advantages of the present invention will become apparent and easily understood from the description of the embodiments in conjunction with the following drawings, in which:

[0043] Figure 1 It is a circuit system design block diagram of the utility model.

[0044] Figure 2 It is a hardware block diagram of the utility model.

[0045] Figure 3 It is a schematic diagram of the data processing circuit board.

[0046] Figure 4 Figure 1 is a schematic diagram of the data acquisition circuit board.

[0047] Figure 5 This is a partial interface circuit diagram of the backplane.

[0048] Figure 6 This is the circuit diagram of the PEX8648 switching module.

[0049] Figure 7 This is the circuit diagram of the T1042 data processing module.

[0050] Figure 8 Here is a schematic diagram of the VPX connector.

[0051] Fig. 9 This is the circuit diagram of the RJ45 network port.

[0052] Fig.10 This is the circuit diagram of the DB9 serial port.

[0053] Fig.11 This is the circuit diagram of the processor chip in the FPGA module.

[0054] Fig.12 It is the circuit diagram of LVDS switch.

[0055] Fig.13 It is the circuit diagram of the SFP network transmission interface.

[0056] Fig.14 This is the circuit diagram of the clock management module.

[0057] Fig.15 This is the circuit diagram of the power management module.

[0058] Fig.16 is the circuit diagram of the clock generator U3. DETAILED DESCRIPTION

[0059] The embodiments of the present invention are described in detail below, and examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and cannot be understood as limiting the present invention.

[0060] like Figures 1 to 16 As shown, a TTE analyzer working circuit includes a data processing circuit board, a data acquisition circuit board, a backplane, a power board, a PEX8648 switching module, a T1042 data processing module, a VPX connector, an RJ45 network port, a DB9 serial port, an FPGA module, an LVDS switch module, an SFP network transmission interface, a data processing circuit board, a data acquisition circuit board, and a power board are all connected to the backplane through a VPX connector, wherein the network port end of the data processing circuit board is connected to a host computer through an RJ45 network port, the VPX connector end of the data processing circuit board is connected to the backplane, and data is exchanged with the data acquisition circuit board on the backplane, the data acquisition circuit board is connected to the TTE network through the SFP network transmission interface, the data acquisition circuit board is connected to the backplane through the VPX interface and exchanges data with the data processing circuit board on the backplane, and the power board is connected to the backplane to supply power to the data acquisition circuit board and the data processing circuit board.

[0061] In the above scheme: the data processing circuit board includes a T1042 data processing module, a PEX8648 switching module, a DB9 serial port, an RJ54 Ethernet interface, a VPX connector, and a power management module. The PEX8648 switching module is connected to the VPX connector through a 4-way PCIE X4 interface to receive network data transmitted from the 4-way data acquisition circuit board. The PEX8648 switching module is connected to the VPX connector through a 1-way PCIE The X4 interface is connected to the T1042 data processing module, and forwards the data transmitted by the bus to the PEX8648 switching module to the T1042 data processing module. The T1042 data processing module is connected to the Ethernet interface RJ45 and sends the Ethernet signal to the host computer through the RJ45 Ethernet interface. The T1042 data processing module is connected to the DB9 serial port and can accept serial port signals for control and debugging. The PEX8648 is connected to the lamp holder and serves as an indicator for the normal operation of the module. The power management module is connected to the power board through the VPX connector, obtains the 12V power supply voltage from the power board and converts the 12V voltage into 1V, 1.8V or 3.3V voltages to power the entire data processing circuit board. The power management module is connected to the lamp holder and serves as an indicator for normal power supply.

[0062] In the above scheme, the data acquisition circuit board includes an FPGA module, an LVDS switch, an SFP network transmission interface, a VPX connector, two 2GB DDR3 memories, two FLASH (256Mb) and a power management module. The FPGA module interacts with the data processing circuit board through the PCIEX4 interface and interacts with the other three data acquisition circuit boards through the PCIE X4 interface. One of the two FLASHs is used as the program storage of the FPGA, and the other is used to store network parameters. The FPGA module is connected to the SFP network transmission interface through the LVDS switch and interacts with the TTE network environment. The FPGA module is connected to the indicator light through the GPIO interface to indicate the working status. The power management module converts the 12V voltage of the power board into multiple voltages such as 1.8V, 1.5V or 1V for powering the data acquisition circuit board.

[0063] In the above scheme, the data acquisition circuit board includes a power management module. As shown in the figure, the voltage output pin VOUT3_0 of the buck regulator chip D12, the voltage output pin VOUT3_1 of the buck regulator chip D12, the voltage output pin VOUT3_2 of the buck regulator chip D12, the voltage output pin VOUT4_0 of the buck regulator chip D12, the voltage output pin VOUT4_1 of the buck regulator chip D12 and the voltage output pin VOUT4_2 of the buck regulator chip D12 output the power supply voltage VCC1V_VINT and are connected to the first end of the capacitor C281 and the first end of the capacitor C284, the second end of the capacitor C281 and the second end of the capacitor C284 are grounded, and the feedback pin FB3 of the buck regulator chip D12 and the feedback pin FB4 of the buck regulator chip D12 are connected to the resistor The first end of R143 is connected to the first end of the resistor R146, the second end of the resistor R143 and the second end of the resistor R146 are grounded, the voltage tracking and soft-start pin TRACK|SS3 of the buck regulator chip D12 and the voltage tracking and soft-start pin TRACK|SS4 of the buck regulator chip D12 are connected to the first end of the capacitor C278, the second end of the capacitor C278 is grounded, the power good indication terminal PGOOD3 of the buck regulator chip D12 is connected to the first end of the resistor R141, the second end of the resistor R141 is connected to the internal power pin INTVCC3 of the buck regulator chip D12, the power good indication terminal PGOOD4 of the buck regulator chip D12 is connected to the first end of the resistor R142, and the second end of the resistor R142 is connected to the internal power pin INTVCC4 of the buck regulator chip D12;

[0064] The voltage input pin VIN3_0 of the buck regulator chip D12, the voltage input pin VIN3_1 of the buck regulator chip D12, the voltage input pin SVIN3 of the buck regulator chip D12, and the enable pin RUN3 of the buck regulator chip D12 are connected to the power supply voltage VCC5V and the first end of the capacitor C274, the second end of the capacitor C274 is grounded, the voltage input pin VIN4_0 of the buck regulator chip D12, the voltage input pin VIN4_1 of the buck regulator chip D12, and the enable pin RUN3 of the buck regulator chip D12 are connected to the power supply voltage VCC5V and the first end of the capacitor C274, the second end of the capacitor C274 is grounded, and ...1 of the buck regulator chip D12 The voltage input pin SVIN4 of the buck regulator chip D12 and the enable pin RUN4 of the buck regulator chip D12 are connected to the power supply voltage VCC5V and the first end of the capacitor C275, the second end of the capacitor C275 is grounded, the internal power pin INTVCC3 of the buck regulator chip D12 is connected to the working mode configuration pin MODE3 of the buck regulator chip D12, and the internal power pin INTVCC4 of the buck regulator chip D12 is connected to the working mode configuration pin MODE4 of the buck regulator chip D12;

[0065] The ground pin SGND of the buck regulator chip D12, the ground pin GND_0 of the buck regulator chip D12, the ground pin GND_1 of the buck regulator chip D12, the ground pin GND_2 of the buck regulator chip D12, the ground pin GND_3 of the buck regulator chip D12, the ground pin GND_4 of the buck regulator chip D12, the ground pin GND_5 of the buck regulator chip D12, the ground pin GND_6 of the buck regulator chip D12, the ground pin GND_7 of the buck regulator chip D12, the ground pin GND_8 of the buck regulator chip D12, the ground pin GND_9 of the buck regulator chip D The ground pin GND_10 of the buck regulator chip D12, the ground pin GND_11 of the buck regulator chip D12, the ground pin GND_12 of the buck regulator chip D12, the ground pin GND_13 of the buck regulator chip D12, the ground pin GND_14 of the buck regulator chip D12, the ground pin GND_15 of the buck regulator chip D12, the ground pin GND_16 of the buck regulator chip D12, the ground pin GND_17 of the buck regulator chip D12, the ground pin GND_18 of the buck regulator chip D12, the ground pin GND_19 of the buck regulator chip D12, and the ground pin GND_20 of the buck regulator chip D12 are all grounded. The input power supply voltage VCC5V is converted into a stable power supply voltage VCC1V_ for output through the buck regulator chip D12.

[0066] The voltage output pin VOUT1_0 of the buck regulator chip D12, the voltage output pin VOUT1_1 of the buck regulator chip D12 and the voltage output pin VOUT1_2 of the buck regulator chip D12 output the power supply voltage VCC1.8V and are connected to the first end of the capacitor C279 and the first end of the capacitor C282, the second end of the capacitor C279 and the second end of the capacitor C282 are grounded, the feedback pin FB1 of the buck regulator chip D12 is connected to the first end of the resistor R144, the second end of the resistor R144 is grounded, the voltage tracking and soft start pin TRACK|SS1 of the buck regulator chip D12 is connected to the first end of the capacitor C276, the second end of the capacitor C276 is grounded, the power good indication pin PGOOD1 of the buck regulator chip D12 is connected to the first end of the resistor R139, and the second end of the resistor R139 is connected to the internal power pin INTVCC1 of the buck regulator chip D12;

[0067] The voltage output pin VOUT2_0 of the buck regulator chip D12, the voltage output pin VOUT2_1 of the buck regulator chip D12 and the voltage output pin VOUT2_2 of the buck regulator chip D12 output the power supply voltage VCC1.5V and are connected to the first end of the capacitor C280 and the first end of the capacitor C283, the second end of the capacitor C280 and the second end of the capacitor C283 are grounded, the feedback pin FB2 of the buck regulator chip D12 is connected to the first end of the resistor R145, the second end of the resistor R145 is grounded, the voltage tracking and soft start pin TRACK|SS2 of the buck regulator chip D12 is connected to the first end of the capacitor C277, the second end of the capacitor C277 is grounded, the power good indication terminal PGOOD2 of the buck regulator chip D12 is connected to the first end of the resistor R140, and the second end of the resistor R140 is connected to the internal power pin INTVCC2 of the buck regulator chip D12;

[0068] The power good indication terminal PGOOD1 of the buck voltage regulator chip D12 is connected to the enable terminal RUN2 of the buck voltage regulator chip D12;

[0069] The voltage input pin VIN1_0 of the buck voltage regulator chip D12, the voltage input pin VIN1_1 of the buck voltage regulator chip D12, and the voltage input pin SVIN1 of the buck voltage regulator chip D12 are connected to the power supply voltage VCC5V and the first end of the capacitor C272, the second end of the capacitor C272 is grounded, and the power good indication terminal PGOOD3 of the buck voltage regulator chip D12 and the power good indication terminal PGOOD4 of the buck voltage regulator chip D12 are connected to the enable terminal RUN1 of the buck voltage regulator chip D12;

[0070] The voltage input pin VIN2_0 of the buck regulator chip D12, the voltage input pin VIN2_1 of the buck regulator chip D12, and the voltage input pin SVIN2 of the buck regulator chip D12 are connected to the power supply voltage VCC5V and the first end of the capacitor C273, and the second end of the capacitor C273 is grounded;

[0071] The internal power pin INTVCC1 of the buck regulator chip D12 is connected to the working mode configuration pin MODE1 of the buck regulator chip D12, and the internal power pin INTVCC2 of the buck regulator chip D12 is connected to the working mode configuration pin MODE2 of the buck regulator chip D12. The input power supply voltage VCC5V is converted into a stable power supply voltage VCC1.8V and VCC1.5V for output through the buck regulator chip D12.

[0072] In a preferred embodiment of the utility model, the power management module also includes capacitors C272, C273, C274 and C275, each with a capacitance of 22uF, capacitors C276, C277 and C278 with a capacitance of 0.1uF, capacitors C279, C280, C281, C282, C283 and C284.

[0073] In a preferred embodiment of the present utility model, the power management module also includes resistors R139, R140, R141 and R142, each having a resistance value of 10 kΩ, resistors R143 and R146 having a resistance value of 90.9 kΩ, resistor R145 having a resistance value of 40.2 kΩ, and resistor R144 having a resistance value of 30.1 kΩ.

[0074] The above-mentioned data acquisition circuit board includes a PEX8648 switching module, including a switching chip U2, a 4-way PCIE X4 interface and a single-way PCIE X4 interface, the first end of the 4-way PCIE X4 interface is connected to the VPX connector, the second end of the 4-way PCIE X4 interface is connected to the switching chip U2, the first end of the single-way PCIE X4 interface is connected to the switching chip, and the second end of the single-way PCIE X4 interface is connected to the T1042 data processing module.

[0075] The above-mentioned PEX8648 switching module includes a network transmission indication pin of a U2 switching chip connected to an LED lamp holder to indicate the network transmission status.

[0076] The data processing circuit board includes a T1042 data processing module, wherein the first end of capacitor C88, the first end of capacitor C89, the first end of capacitor C96, the first end of capacitor C98, the first end of capacitor C100, the first end of capacitor C102, the first end of capacitor C105, the first end of capacitor C108 and the first end of capacitor C111 are connected to the input voltage VCC3.3V and the voltage input pin VCC of the processor IC1, and the second end of capacitor C88, the second end of capacitor C89, the second end of capacitor C96, the second end of capacitor C98, the second end of capacitor C100, the second end of capacitor C102, the second end of capacitor C105, the second end of capacitor C108 and the second end of capacitor C111 are grounded;

[0077] A first end of capacitor C106, a first end of capacitor C109 and a first end of capacitor C112 are connected to input voltage VCC1.8V and voltage input pin VCCQ of processor IC1, and a second end of capacitor C106, a second end of capacitor C109 and a second end of capacitor C112 are grounded;

[0078] A first end of the resistor R152 is connected to the input voltage VCC1.2V, a second end of the resistor R152 is connected to a first end of a capacitor C90, a first end of a capacitor C97, a first end of a capacitor C99, a first end of a capacitor C101, a first end of a capacitor C103, a first end of a capacitor C107, a first end of a capacitor C110, a first end of a capacitor C113, a voltage input pin VDDC of the processor IC1, and a voltage input pin VDD of the processor IC1, and a second end of the capacitor C90, a second end of the capacitor C97, a second end of the capacitor C99, a second end of the capacitor C101, a second end of the capacitor C103, a second end of the capacitor C107, a second end of the capacitor C110, and a second end of the capacitor C113 are grounded;

[0079] The first SATA power supply pin SATA_VDD of the processor IC1 is connected to the first end of the capacitor C120, the first end of the capacitor C122, the first end of the capacitor C124 and the first end of the inductor L11, the second end of the capacitor C120, the second end of the capacitor C122 and the second end of the capacitor C124 are all grounded, and the second end of the inductor L11 is connected to the input voltage VCC1.2V;

[0080] The second SATA power supply pin SATA_VDD of the processor IC1 is connected to the first end of the capacitor C121, the first end of the capacitor C123, the first end of the capacitor C125 and the first end of the inductor L12, the second end of the capacitor C121, the second end of the capacitor C123 and the second end of the capacitor C125 are all grounded, and the second end of the inductor L12 is connected to the input voltage VCC1.2V;

[0081] The SATA voltage pin SATA_VSS of the processor IC1 is grounded, the sleep signal pin DEVSLP of the processor IC1 is connected to the first end of the resistor R155, the second end of the resistor R155 is grounded, the crystal oscillator output pin XTAL_OUT of the processor IC1 and the crystal oscillator input pin XTAL_IN of the processor IC1 are connected to the crystal oscillator input pin 1 of the crystal oscillator G1 and the crystal oscillator output pin 3 of the crystal oscillator G1, the power reset pin PWR_RESETN of the processor IC1 is connected to the first end of the resistor R158, the second end of the resistor R158 is connected to the external reset signal, and the power reset pin PWR_RESETN of the processor IC1 is connected to the external SATA power reset signal;

[0082] The spare pin NC34 of the processor IC1 is connected to the LED indicator light, and the spare pin NC37 of the processor IC1 and the spare pin NC38 of the processor IC1 are connected to the SATA device for receiving and sending control commands and data of the SATA device.

[0083] The processor module includes a crystal oscillator circuit, wherein a crystal oscillator input pin 1 of a crystal oscillator G1 is connected to a first end of a capacitor C104, a first end of a resistor R153, and a crystal oscillator output pin XTAL_OUT of a processor IC1, a second end of the capacitor C104 is grounded, a crystal oscillator output pin 3 of the crystal oscillator G1 is connected to a first end of the resistor R154, a second end of the resistor R154 is connected to a first end of a capacitor C114, a second end of the resistor R153, and a crystal oscillator input pin STAL_IN of the processor IC1, a second end of the capacitor C114 is grounded, and a ground pin 2 of the crystal oscillator G1 and a ground pin 4 of the crystal oscillator G1 are grounded.

[0084] In a preferred embodiment of the present invention, the processor module further includes: the capacitance of capacitor C88, capacitor C89 and capacitor C96 is 1uF, the capacitance of capacitor C98, capacitor C100, capacitor C102, capacitor C105, capacitor C10 and capacitor C111 is 0.1uF, the capacitance of capacitor C106 is 1uF, the capacitance of capacitor C109 and capacitor C112 is 1uF, the capacitance of capacitor C90, capacitor C99 and capacitor C The capacitance of 101 is 10uF, the capacitance of capacitor C101, capacitor C103, capacitor C107, capacitor C110 and capacitor C113 is 4.7uF, the capacitance of capacitor C120, capacitor C121, capacitor C122 and capacitor C123 is 0.1uF, the capacitance of capacitor C124 and capacitor C125 is 10uF, the inductance of inductor L11 and inductor L12 is 22uH, and the resistance of resistor R155 is 1kΩ.

[0085] The first end of the above-mentioned VPX connector module is connected to the PEX8648 switching module of the data processing circuit board through a 4-way PCIE X4 interface, the second end of the VPX connector module is connected to the four data acquisition circuit boards through four single-way PCIE X4 interfaces, and the power transmission end of the VPX connector module is connected to the power board.

[0086] The above-mentioned RJ45 network port module includes an Ethernet interface ETH0, a network transmission indicator light and a capacitor filter network. The network signal transmission pins 1 to 8 of the Ethernet interface ETH0 are used for Gigabit Ethernet data transmission. The indicator light pin 9 of the Ethernet interface ETH0 receives the network activity signal GBE0_ACT_N. When there is data transmission, the LED light is on. The indicator light pin 9 of the Ethernet interface ETH0 is connected to the first end of the capacitor C6, and the second end of the capacitor C6 is grounded. The indicator light pin 10 of the Ethernet interface ETH0 is connected to the first end of the resistor R9, and the second end of the resistor R9 is connected to the input voltage LED_2V5.

[0087] The indicator light pin 11 of the Ethernet interface ETH0 receives the network connection signal LINK1000_N. When the link is successful, the LED light is on. The indicator light pin 11 of the Ethernet interface ETH0 is connected to the first end of the capacitor C4, and the second end of the capacitor C4 is grounded. The indicator light pin 12 of the Ethernet interface ETH0 is connected to the first end of the resistor R10, and the second end of the resistor R10 is connected to the input voltage LED_2V5;

[0088] In a preferred implementation manner of the present utility model, the RJ45 network port module further includes: the capacitance of capacitor C4 and capacitor C6 is 4700pF, and the resistance of capacitor R9 and capacitor R10 is 330Ω.

[0089] The above-mentioned clock management module includes the MC100LVE111FA clock distribution chip D1, the clock generator U3, the decoupling capacitor for reducing power supply noise, and the resistor network for impedance matching and the resistor network for voltage division. These three parts together constitute the clock management module for ensuring the signal integrity and stability of the clock signal.

[0090] The control pin OE of the clock generator U3 is connected to the first end of the resistor R102, the second end of the resistor R102 is connected to the second end of the inductor L1, the first end of the capacitor C53 and the voltage input pin VDD of the clock generator U3, the first end of the inductor L1 is connected to the input voltage VCC3.3V, the second end of the capacitor C53 is grounded, the clock signal output pin CLK of the clock generator U3 is connected to the first end of the capacitor C58, the second end of the capacitor C58 is connected to the clock input pin CLK0 of the clock distribution chip D1, the clock signal output pin CLK* of the clock generator U3 is connected to the first end of the capacitor C95, the second end of the capacitor C95 is connected to the clock input pin CLK0* of the clock distribution chip D1, and the ground pin GND of the clock generator U3 is grounded.

[0091] The clock input pin CLK0 of the clock distribution chip D1 and the clock input pin CLK0* of the clock distribution chip D1 are connected to the clock signal output pin CLK of the clock generator U3 and the clock signal output pin CLK* of the clock generator U3 to receive the synchronous differential signal from the clock generator U3, the first end of the resistor R86 is connected to the input voltage VCC3.3V, the second end of the resistor R86 is connected to the first end of the resistor R87 and the clock input pin CLK0 of the clock distribution chip D1, the second end of the resistor R87 is grounded, the first end of the resistor R88 is connected to the input voltage VCC3.3V, the second end of the resistor R88 is connected to the first end of the resistor R89 ​​and the clock input pin CLK0* of the clock distribution chip D1, and the second end of the resistor R89 ​​is grounded;

[0092] The first end of the resistor R90 is connected to the clock input pin CLK1 of the clock distribution chip D1, the second end of the resistor R90 is grounded, the first end of the resistor R101 is connected to the clock input pin CLK1* of the clock distribution chip D1, the second end of the resistor R101 is grounded, the first end of the resistor R62 is connected to the clock selection pin CLK_SET of the clock distribution chip D1, the second end of the resistor R62 is grounded, the clock selection pin CLK_SET of the clock distribution chip D1 is connected to the clock selection signal, the first end of the capacitor C54, the first end of the capacitor C55, the The first end of capacitor C56 is connected to the input voltage VCC3.3V, the second end of capacitor C54, the second end of capacitor C55, and the second end of capacitor C56 are all grounded, the first end of capacitor C54 is also connected to the voltage input pin VCC0 of the clock distribution chip D1, the voltage input pin VCC1 of the clock distribution chip D1, the voltage input pin VCC2 of the clock distribution chip D1, the voltage input pin VCC3 of the clock distribution chip D1, and the voltage input pin VCC4 of the clock distribution chip D1, and the voltage pin VEE of the clock distribution chip D1 is grounded;

[0093] A first end of the resistor R103 is connected to a signal output pin Q0 of the clock distribution chip D1 and a first end of the capacitor C18, a second end of the resistor R103 is grounded, and a second end of the capacitor C18 is connected to a VPX connector, a first end of the resistor R104 is connected to a signal output pin Q0* of the clock distribution chip D1 and a first end of the capacitor C60, a second end of the resistor R104 is grounded, and a second end of the capacitor C60 is connected to a VPX connector, a first end of the resistor R1 is connected to a signal output pin Q1 of the clock distribution chip D1 and a first end of the capacitor C21, a second end of the resistor R1 is grounded, and a second end of the capacitor C21 is connected to the VPX connector, a first end of the resistor R8 is connected to a signal output pin Q1* of the clock distribution chip D1 and a first end of the capacitor C61, a second end of the resistor R8 is grounded, and a second end of the capacitor C61 is connected to the VPX connector, A first end of the resistor R21 is connected to a signal output pin Q2 of the clock distribution chip D1 and a first end of the capacitor C38, a second end of the resistor R21 is grounded, and a second end of the capacitor C38 is connected to a VPX connector, a first end of the resistor R35 is connected to a signal output pin Q2* of the clock distribution chip D1 and a first end of the capacitor C62, a second end of the resistor R35 is grounded, and a second end of the capacitor C62 is connected to the VPX connector, a first end of the resistor R36 is connected to a signal output pin Q3 of the clock distribution chip D1 and a first end of the capacitor C44, a second end of the resistor R36 is grounded, and a second end of the capacitor C44 is connected to the VPX connector, a first end of the resistor R57 is connected to a signal output pin Q3* of the clock distribution chip D1 and a first end of the capacitor C17, a second end of the resistor R57 is grounded, and a second end of the capacitor C17 is connected to the VPX connector;

[0094] The second end of the capacitor C18 is connected to the first end of the resistor R58 and the first end of the resistor R59, the second end of the resistor R58 is connected to the input voltage VCC3.3V, and the second end of the resistor R59 is grounded. The second end of the capacitor C60 is connected to the first end of the resistor R60 and the first end of the resistor R61, the second end of the resistor R60 is connected to the input voltage VCC3.3V, and the second end of the resistor R61 is grounded. The second end of the capacitor C21 is connected to the first end of the resistor R63 and the first end of the resistor R64, the second end of the resistor R63 is connected to the input voltage VCC3.3V, and the second end of the resistor R64 is grounded. The second end of the capacitor C61 is connected to the first end of the resistor R66 and the first end of the resistor R67, the second end of the resistor R66 is connected to the input voltage VCC3.3V, and the second end of the resistor R67 is grounded. The second end of capacitor C38 is connected to the first end of resistor R68 and the first end of resistor R69, the second end of resistor R68 is connected to the input voltage VCC3.3V, and the second end of resistor R69 is grounded. The second end of capacitor C62 is connected to the first end of resistor R70 and the first end of resistor R72, the second end of resistor R70 is connected to the input voltage VCC3.3V, and the second end of resistor R72 is grounded. The second end of capacitor C44 is connected to the first end of resistor R73 and the first end of resistor R74, the second end of resistor R73 is connected to the input voltage VCC3.3V, and the second end of resistor R74 is grounded. The second end of capacitor C17 is connected to the first end of resistor R75 and the first end of resistor R76, the second end of resistor R75 is connected to the input voltage VCC3.3V, and the second end of resistor R76 is grounded.

[0095] In a preferred embodiment of the present invention, the clock management module includes: the inductance of the inductor L1 is 22uH, the capacitance of the capacitor C53 is 0.1uF, the resistance of the resistor R102 is 4.7kΩ, the capacitance of the capacitor C58 and the capacitor C95 is 0.1uF, the resistance of the resistor R86 and the resistor R87 is 7.5kΩ, the resistance of the resistor R87, the resistor R89, the resistor R90, the resistor R101 and the resistor R62 is 10kΩ, the capacitance of the capacitor C54 is 10uF, the capacitor C55 and the capacitor C56 are The resistance value of is 0.1uF, the resistance value of resistor R103, resistor R104, resistor R1, resistor R8, resistor R21, resistor R35, resistor R36 and resistor R57 are 120Ω, the resistance value of resistor R59, resistor R61, resistor R64, resistor R67, resistor R69, resistor R72, resistor R74 and resistor R76 are 1kΩ, and the resistance value of resistor R58, resistor R60, resistor R63, resistor R66, resistor R68, resistor R70, resistor R73 and resistor R75 are 10kΩ.

[0096] The above-mentioned FPGA module adopts the processor chip D4 of the XC7K325T-2FFG900I model to manage various interface signals such as LVDS, PCIe, and JTAG. The LVDS interface is used for high-speed data transmission, the PCIE X4 interface realizes high-speed data communication with the host system, and the JTAG interface is used for programming and debugging.

[0097] The above-mentioned SFP interface module includes an SFP module interface connected to the LVD switch X4 through an Ethernet transmission line, and the LVD switch is connected to the FPGA module.

[0098] Although the embodiments of the present invention have been shown and described, those skilled in the art will appreciate that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present invention, and that the scope of the present invention is defined by the claims and their equivalents.

Claims

1. A TTE analyzer working circuit, characterized in that: include: Data processing circuit board, including T1042 data processing module, PEX8648 switching module, DB9 serial port, RJ45 Ethernet interface, VPX connector, clock management module and power management module; Data acquisition circuit board, including FPGA module, LVDS switch, SFP network transmission interface, VPX connector, DDR3 memory, clock management module and power management module; Back panel; Power board; The data processing circuit board, data acquisition circuit board and power board are connected to the backplane through the VPX connector, and data exchange is performed on the backplane. The TTE network data enters the FPGA module of the data acquisition circuit board through the SFP interface, and then the FPGA module transmits the network data to the VPX connector through the PCIE X4 interface. Then the network data enters the PEX8648 switching module of the data processing circuit board from the VPX connector. The PEX8648 switching module transmits the network data to the T1042 data processing module, and the T1042 data processing module transmits the network data to the RJ45 network port. Finally, the RJ45 network port transmits the network data to the host computer. The data processing circuit board includes a PEX8648 switching module connected to the VPX connector via a 4-way PCIE X4 interface, the PEX8648 switching module connected to the T1042 data processing module via a 1-way PCIE X4 interface, the T1042 data processing module connected to the host computer via an RJ45 Ethernet interface, and receiving control and debugging signals via a DB9 serial port; Among them, the data acquisition circuit board, the power management module is connected to the processor module and the FPGA, the clock management module is connected to the FPGA module, the FPGA module is connected to the DDR3 memory, the FPGA module is connected to the VPX connector through the PCIE X4 interface, the FPGA module is connected to the VPX connector through three sets of LVDS X3 switches, the FPGA module is connected to the indicator light through the GPIO interface, the FPGA module is connected to the JTAG interface, the FPGA module is connected to the SFP interface module through the LVDS X4 switch, and the SFP X4 interface is connected to the TTE network; The power management module converts the voltage provided by the power board into the voltage required by each module.

2. The TTE analyzer working circuit according to claim 1, characterized in that: The data processing circuit board and the data acquisition circuit board include a power management module, wherein the power management module includes: Multiple capacitor filtering networks to provide stable voltage input; Buck regulator chip for voltage regulation and clock synchronization; Power good indicator terminal, used to monitor the power status; The voltage output pin VOUT1_0 of the buck regulator chip D12, the voltage output pin VOUT1_1 of the buck regulator chip D12 and the voltage output pin VOUT1_2 of the buck regulator chip D12 output the power supply voltage VCC1.8V and are connected to the first end of the capacitor C279 and the first end of the capacitor C282, the second end of the capacitor C279 and the second end of the capacitor C282 are grounded, the feedback pin FB1 of the buck regulator chip D12 is connected to the first end of the resistor R144, the second end of the resistor R144 is grounded, the voltage tracking and soft start pin TRACK|SS1 of the buck regulator chip D12 is connected to the first end of the capacitor C276, the second end of the capacitor C276 is grounded, the power good indication pin PGOOD1 of the buck regulator chip D12 is connected to the first end of the resistor R139, and the second end of the resistor R139 is connected to the internal power pin INTVCC1 of the buck regulator chip D12; The voltage output pin VOUT2_0 of the buck regulator chip D12, the voltage output pin VOUT2_1 of the buck regulator chip D12 and the voltage output pin VOUT2_2 of the buck regulator chip D12 output the power supply voltage VCC1.5V and are connected to the first end of the capacitor C280 and the first end of the capacitor C283, the second end of the capacitor C280 and the second end of the capacitor C283 are grounded, the feedback pin FB2 of the buck regulator chip D12 is connected to the first end of the resistor R145, the second end of the resistor R145 is grounded, the voltage tracking and soft start pin TRACK|SS2 of the buck regulator chip D12 is connected to the first end of the capacitor C277, the second end of the capacitor C277 is grounded, the power good indication terminal PGOOD2 of the buck regulator chip D12 is connected to the first end of the resistor R140, and the second end of the resistor R140 is connected to the internal power pin INTVCC2 of the buck regulator chip D12; The power good indication terminal PGOOD1 of the buck voltage regulator chip D12 is connected to the enable terminal RUN2 of the buck voltage regulator chip D12; The voltage input pin VIN1_0 of the buck voltage regulator chip D12, the voltage input pin VIN1_1 of the buck voltage regulator chip D12, and the voltage input pin SVIN1 of the buck voltage regulator chip D12 are connected to the power supply voltage VCC5V and the first end of the capacitor C272, the second end of the capacitor C272 is grounded, and the power good indication terminal PGOOD3 of the buck voltage regulator chip D12 and the power good indication terminal PGOOD4 of the buck voltage regulator chip D12 are connected to the enable terminal RUN1 of the buck voltage regulator chip D12; The voltage input pin VIN2_0 of the buck regulator chip D12, the voltage input pin VIN2_1 of the buck regulator chip D12, and the voltage input pin SVIN2 of the buck regulator chip D12 are connected to the power supply voltage VCC5V and the first end of the capacitor C273, and the second end of the capacitor C273 is grounded; The internal power supply pin INTVCC1 of the buck voltage regulator chip D12 is connected to the working mode configuration pin MODE1 of the buck voltage regulator chip D12, and the internal power supply pin INTVCC2 of the buck voltage regulator chip D12 is connected to the working mode configuration pin MODE2 of the buck voltage regulator chip D12; The voltage output pin VOUT3_0 of the buck regulator chip D12, the voltage output pin VOUT3_1 of the buck regulator chip D12, the voltage output pin VOUT3_2 of the buck regulator chip D12, the voltage output pin VOUT4_0 of the buck regulator chip D12, the voltage output pin VOUT4_1 of the buck regulator chip D12 and the voltage output pin VOUT4_2 of the buck regulator chip D12 output the power supply voltage VCC1V_VINT and are connected to the first end of the capacitor C281 and the first end of the capacitor C284, the second end of the capacitor C281 and the second end of the capacitor C284 are grounded, the feedback pin FB3 of the buck regulator chip D12 and the feedback pin FB4 of the buck regulator chip D12 are connected to the first end of the resistor R143 and the resistor R146 The first end of the step-down voltage regulator chip D12 is connected to the first end of the resistor R141, the second end of the resistor R141 is connected to the internal power pin INTVCC3 of the step-down voltage regulator chip D12, the second end of the resistor R143 and the second end of the resistor R146 are grounded, the voltage tracking and soft-start pin TRACK|SS3 of the step-down voltage regulator chip D12 and the voltage tracking and soft-start pin TRACK|SS4 of the step-down voltage regulator chip D12 are connected to the first end of the capacitor C278, the second end of the capacitor C278 is grounded, the power good indication terminal PGOOD3 of the step-down voltage regulator chip D12 is connected to the first end of the resistor R141, the second end of the resistor R141 is connected to the internal power pin INTVCC3 of the step-down voltage regulator chip D12, the power good indication terminal PGOOD4 of the step-down voltage regulator chip D12 is connected to the first end of the resistor R142, and the second end of the resistor R142 is connected to the internal power pin INTVCC4 of the step-down voltage regulator chip D12; The voltage input pin VIN3_0 of the buck regulator chip D12, the voltage input pin VIN3_1 of the buck regulator chip D12, the voltage input pin SVIN3 of the buck regulator chip D12, and the enable pin RUN3 of the buck regulator chip D12 are connected to the power supply voltage VCC5V and the first end of the capacitor C274, the second end of the capacitor C274 is grounded, the voltage input pin VIN4_0 of the buck regulator chip D12, the voltage input pin VIN4_1 of the buck regulator chip D12, and the enable pin RUN3 of the buck regulator chip D12 are connected to the power supply voltage VCC5V and the first end of the capacitor C274, the second end of the capacitor C274 is grounded, and ...1 of the buck regulator chip D12 The voltage input pin SVIN4 of the buck regulator chip D12 and the enable pin RUN4 of the buck regulator chip D12 are connected to the power supply voltage VCC5V and the first end of the capacitor C275, the second end of the capacitor C275 is grounded, the internal power pin INTVCC3 of the buck regulator chip D12 is connected to the working mode configuration pin MODE3 of the buck regulator chip D12, and the internal power pin INTVCC4 of the buck regulator chip D12 is connected to the working mode configuration pin MODE4 of the buck regulator chip D12; The ground pin SGND of the buck regulator chip D12, the ground pin GND_0 of the buck regulator chip D12, the ground pin GND_1 of the buck regulator chip D12, the ground pin GND_2 of the buck regulator chip D12, the ground pin GND_3 of the buck regulator chip D12, the ground pin GND_4 of the buck regulator chip D12, the ground pin GND_5 of the buck regulator chip D12, the ground pin GND_6 of the buck regulator chip D12, the ground pin GND_7 of the buck regulator chip D12, the ground pin GND_8 of the buck regulator chip D12, the ground pin GND_9 of the buck regulator chip D The ground pin GND_10 of buck voltage regulator chip D12, the ground pin GND_11 of buck voltage regulator chip D12, the ground pin GND_12 of buck voltage regulator chip D12, the ground pin GND_13 of buck voltage regulator chip D12, the ground pin GND_14 of buck voltage regulator chip D12, the ground pin GND_15 of buck voltage regulator chip D12, the ground pin GND_16 of buck voltage regulator chip D12, the ground pin GND_17 of buck voltage regulator chip D12, the ground pin GND_18 of buck voltage regulator chip D12, the ground pin GND_19 of buck voltage regulator chip D12, and the ground pin GND_20 of buck voltage regulator chip D12 are all grounded.

3. The TTE analyzer working circuit according to claim 1, characterized in that: The data processing circuit board includes a clock management module; The control pin OE of the clock generator U3 is connected to the first end of the resistor R102, the second end of the resistor R102 is connected to the second end of the inductor L1, the first end of the capacitor C53 and the voltage input pin VDD of the clock generator U3, the first end of the inductor L1 is connected to the input voltage VCC3.3V, the second end of the capacitor C53 is grounded, the clock signal output pin CLK of the clock generator U3 is connected to the first end of the capacitor C58, the second end of the capacitor C58 is connected to the clock input pin CLK0 of the clock distribution chip D1, the clock signal output pin CLK* of the clock generator U3 is connected to the first end of the capacitor C95, the second end of the capacitor C95 is connected to the clock input pin CLK0* of the clock distribution chip D1, and the ground pin GND of the clock generator U3 is grounded; The clock input pin CLK0 of the clock distribution chip D1 and the clock input pin CLK0* of the clock distribution chip D1 are connected to the clock signal output pin CLK of the clock generator U3 and the clock signal output pin CLK* of the clock generator U3 to receive the synchronous differential signal from the clock generator U3, the first end of the resistor R86 is connected to the input voltage VCC3.3V, the second end of the resistor R86 is connected to the first end of the resistor R87 and the clock input pin CLK0 of the clock distribution chip D1, the second end of the resistor R87 is grounded, the first end of the resistor R88 is connected to the input voltage VCC3.3V, the second end of the resistor R88 is connected to the first end of the resistor R89 ​​and the clock input pin CLK0* of the clock distribution chip D1, and the second end of the resistor R89 ​​is grounded; The first end of the resistor R90 is connected to the clock input pin CLK1 of the clock distribution chip D1, the second end of the resistor R90 is grounded, the first end of the resistor R101 is connected to the clock input pin CLK1* of the clock distribution chip D1, the second end of the resistor R101 is grounded, the first end of the resistor R62 is connected to the clock selection pin CLK_SET of the clock distribution chip D1, the second end of the resistor R62 is grounded, the clock selection pin CLK_SET of the clock distribution chip D1 is connected to the clock selection signal, the first end of the capacitor C54, the first end of the capacitor C55, the The first end of capacitor C56 is connected to the input voltage VCC3.3V, the second end of capacitor C54, the second end of capacitor C55, and the second end of capacitor C56 are all grounded, the first end of capacitor C54 is also connected to the voltage input pin VCC0 of the clock distribution chip D1, the voltage input pin VCC1 of the clock distribution chip D1, the voltage input pin VCC2 of the clock distribution chip D1, the voltage input pin VCC3 of the clock distribution chip D1, and the voltage input pin VCC4 of the clock distribution chip D1, and the voltage pin VEE of the clock distribution chip D1 is grounded; A first end of the resistor R103 is connected to a signal output pin Q0 of the clock distribution chip D1 and a first end of the capacitor C18, a second end of the resistor R103 is grounded, and a second end of the capacitor C18 is connected to a VPX connector, a first end of the resistor R104 is connected to a signal output pin Q0* of the clock distribution chip D1 and a first end of the capacitor C60, a second end of the resistor R104 is grounded, and a second end of the capacitor C60 is connected to a VPX connector, a first end of the resistor R1 is connected to a signal output pin Q1 of the clock distribution chip D1 and a first end of the capacitor C21, a second end of the resistor R1 is grounded, and a second end of the capacitor C21 is connected to the VPX connector, a first end of the resistor R8 is connected to a signal output pin Q1* of the clock distribution chip D1 and a first end of the capacitor C61, a second end of the resistor R8 is grounded, and a second end of the capacitor C61 is connected to the VPX connector, A first end of the resistor R21 is connected to a signal output pin Q2 of the clock distribution chip D1 and a first end of the capacitor C38, a second end of the resistor R21 is grounded, and a second end of the capacitor C38 is connected to a VPX connector, a first end of the resistor R35 is connected to a signal output pin Q2* of the clock distribution chip D1 and a first end of the capacitor C62, a second end of the resistor R35 is grounded, and a second end of the capacitor C62 is connected to the VPX connector, a first end of the resistor R36 is connected to a signal output pin Q3 of the clock distribution chip D1 and a first end of the capacitor C44, a second end of the resistor R36 is grounded, and a second end of the capacitor C44 is connected to the VPX connector, a first end of the resistor R57 is connected to a signal output pin Q3* of the clock distribution chip D1 and a first end of the capacitor C17, a second end of the resistor R57 is grounded, and a second end of the capacitor C17 is connected to the VPX connector; The second end of the capacitor C18 is connected to the first end of the resistor R58 and the first end of the resistor R59, the second end of the resistor R58 is connected to the input voltage VCC3.3V, and the second end of the resistor R59 is grounded. The second end of the capacitor C60 is connected to the first end of the resistor R60 and the first end of the resistor R61, the second end of the resistor R60 is connected to the input voltage VCC3.3V, and the second end of the resistor R61 is grounded. The second end of the capacitor C21 is connected to the first end of the resistor R63 and the first end of the resistor R64, the second end of the resistor R63 is connected to the input voltage VCC3.3V, and the second end of the resistor R64 is grounded. The second end of the capacitor C61 is connected to the first end of the resistor R66 and the first end of the resistor R67, the second end of the resistor R66 is connected to the input voltage VCC3.3V, and the second end of the resistor R67 is grounded. The second end of capacitor C38 is connected to the first end of resistor R68 and the first end of resistor R69, the second end of resistor R68 is connected to the input voltage VCC3.3V, and the second end of resistor R69 is grounded. The second end of capacitor C62 is connected to the first end of resistor R70 and the first end of resistor R72, the second end of resistor R70 is connected to the input voltage VCC3.3V, and the second end of resistor R72 is grounded. The second end of capacitor C44 is connected to the first end of resistor R73 and the first end of resistor R74, the second end of resistor R73 is connected to the input voltage VCC3.3V, and the second end of resistor R74 is grounded. The second end of capacitor C17 is connected to the first end of resistor R75 and the first end of resistor R76, the second end of resistor R75 is connected to the input voltage VCC3.3V, and the second end of resistor R76 is grounded.

4. The TTE analyzer working circuit according to claim 1, characterized in that: The data processing circuit board includes a T1042 data processing module, In the above-mentioned T1042 data processing module, the first end of capacitor C88, the first end of capacitor C89, the first end of capacitor C96, the first end of capacitor C98, the first end of capacitor C100, the first end of capacitor C102, the first end of capacitor C105, the first end of capacitor C108 and the first end of capacitor C111 are connected to the input voltage VCC3.3V and the voltage input pin VCC of the processor IC1, and the second end of capacitor C88, the second end of capacitor C89, the second end of capacitor C96, the second end of capacitor C98, the second end of capacitor C100, the second end of capacitor C102, the second end of capacitor C105, the second end of capacitor C108 and the second end of capacitor C111 are grounded; A first end of capacitor C106, a first end of capacitor C109 and a first end of capacitor C112 are connected to input voltage VCC1.8V and voltage input pin VCCQ of processor IC1, and a second end of capacitor C106, a second end of capacitor C109 and a second end of capacitor C112 are grounded; A first end of the resistor R152 is connected to the input voltage VCC1.2V, a second end of the resistor R152 is connected to a first end of a capacitor C90, a first end of a capacitor C97, a first end of a capacitor C99, a first end of a capacitor C101, a first end of a capacitor C103, a first end of a capacitor C107, a first end of a capacitor C110, a first end of a capacitor C113, a voltage input pin VDDC of the processor IC1, and a voltage input pin VDD of the processor IC1, and a second end of the capacitor C90, a second end of the capacitor C97, a second end of the capacitor C99, a second end of the capacitor C101, a second end of the capacitor C103, a second end of the capacitor C107, a second end of the capacitor C110, and a second end of the capacitor C113 are grounded; The first SATA power supply pin SATA_VDD of the processor IC1 is connected to the first end of the capacitor C120, the first end of the capacitor C122, the first end of the capacitor C124 and the first end of the inductor L11, the second end of the capacitor C120, the second end of the capacitor C122 and the second end of the capacitor C124 are all grounded, and the second end of the inductor L11 is connected to the input voltage VCC1.2V; The second SATA power supply pin SATA_VDD of the processor IC1 is connected to the first end of the capacitor C121, the first end of the capacitor C123, the first end of the capacitor C125 and the first end of the inductor L12, the second end of the capacitor C121, the second end of the capacitor C123 and the second end of the capacitor C125 are all grounded, and the second end of the inductor L12 is connected to the input voltage VCC1.2V; The SATA voltage pin SATA_VSS of the processor IC1 is grounded, the sleep signal pin DEVSLP of the processor IC1 is connected to the first end of the resistor R155, the second end of the resistor R155 is grounded, the crystal oscillator output pin XTAL_OUT of the processor IC1 and the crystal oscillator input pin XTAL_IN of the processor IC1 are connected to the crystal oscillator input pin 1 of the crystal oscillator G1 and the crystal oscillator output pin 3 of the crystal oscillator G1, the power reset pin PWR_RESETN of the processor IC1 is connected to the first end of the resistor R158, the second end of the resistor R158 is connected to the external reset signal, and the power reset pin PWR_RESETN of the processor IC1 is connected to the external SATA power reset signal; The spare pin NC34 of the processor IC1 is connected to the LED indicator light, and the spare pin NC37 of the processor IC1 and the spare pin NC38 of the processor IC1 are connected to the SATA device for receiving and sending control commands and data of the SATA device; The processor module includes a crystal oscillator circuit, wherein a crystal oscillator input pin 1 of a crystal oscillator G1 is connected to a first end of a capacitor C104, a first end of a resistor R153, and a crystal oscillator output pin XTAL_OUT of a processor IC1, a second end of the capacitor C104 is grounded, a crystal oscillator output pin 3 of the crystal oscillator G1 is connected to a first end of the resistor R154, a second end of the resistor R154 is connected to a first end of a capacitor C114, a second end of the resistor R153, and a crystal oscillator input pin STAL_IN of the processor IC1, a second end of the capacitor C114 is grounded, and a ground pin 2 of the crystal oscillator G1 and a ground pin 4 of the crystal oscillator G1 are grounded.

5. The TTE analyzer working circuit according to claim 1, characterized in that: The data processing circuit board includes a PEX8648 switching module, and the PEX8648 switching module includes: a switching chip, a multi-channel PCIE X4 interface; The PEX8648 switching module includes a switching chip U2, 4 PCIE X4 interfaces and a single PCIE X4 interface, wherein a first end of the 4 PCIE X4 interface is connected to the VPX connector, a second end of the 4 PCIE X4 interface is connected to the switching chip U2, a first end of the single PCIE X4 interface is connected to the switching chip, and a second end of the single PCIE X4 interface is connected to the T1042 data processing module; The above-mentioned PEX8648 switching module includes a network transmission indication pin of the switching chip U2 connected to an LED lamp holder to indicate the network transmission status.

6. The TTE analyzer working circuit according to claim 1, characterized in that: The data processing circuit board includes an RJ45 network port module, and the RJ45 network port module includes an Ethernet interface, a network transmission indicator light, and a capacitor filter network; The RJ45 network port module includes network signal transmission pins 1 to 8 of the Ethernet interface ETH0 for data transmission of Gigabit Ethernet, an indicator light pin 9 of the Ethernet interface ETH0 receives a network activity signal GBE0_ACT_N, and when data is transmitted, the LED light is on, the indicator light pin 9 of the Ethernet interface ETH0 is connected to a first end of a capacitor C6, a second end of the capacitor C6 is grounded, an indicator light pin 10 of the Ethernet interface ETH0 is connected to a first end of a resistor R9, and a second end of the resistor R9 is connected to an input voltage LED_2V5; The indicator light pin 11 of the Ethernet interface ETH0 receives the network connection signal LINK1000_N. When the link is successful, the LED lights up. The indicator light pin 11 of the Ethernet interface ETH0 is connected to the first end of the capacitor C4, and the second end of the capacitor C4 is grounded. The indicator light pin 12 of the Ethernet interface ETH0 is connected to the first end of the resistor R10, and the second end of the resistor R10 is connected to the input voltage LED_2V5.

7. The TTE analyzer working circuit according to claim 1, characterized in that: The data processing circuit board and the data acquisition circuit board include a VPX connector module, including: The first end of the VPX connector module is connected to the PEX8648 switching module of the data processing circuit board through a 4-way PCIE X4 interface, the second end of the VPX connector module is connected to four data acquisition circuit boards through a 4-way PCIE X4 interface, and the power transmission end of the VPX connector module is connected to the power board.

8. The TTE analyzer working circuit according to claim 1, characterized in that: The data processing circuit board is connected to the host computer through the RJ45 network port, and is connected to the backplane through the VPX connector. The backplane interacts with the data acquisition circuit board, and the data acquisition circuit board is connected to the TTE network through the SFP network transmission interface.

9. The TTE analyzer working circuit according to claim 1, characterized in that: The data acquisition circuit board includes a clock management module, wherein the clock management module includes an enable pin OE of a clock generator U1 connected to a first end of a resistor R114, a second end of the resistor R114 connected to an input voltage VCC3.3V, a voltage input pin VDD of the clock generator U1 connected to a first end of a capacitor C244 and a second end of an inductor L5, a second end of the capacitor C244 grounded, a first end of the inductor L5 connected to the input voltage VCC3.3V, a clock output pin CLK of the clock generator U1 connected to an FPGA module and a first end of a capacitor C255, a second end of the capacitor C255 connected to a first end of a resistor R126, a resistor R1 The first end of resistor R126 is connected to the input voltage VCC1.5V, the second end of resistor R127 is grounded, the second end of resistor R171 is connected to the second end of capacitor C317, the clock output pin CLK* of clock generator U1 is connected to the first end of capacitor C317, the second end of capacitor C137 is connected to the first end of resistor R130, the first end of resistor R155 and the FPGA module, the second end of resistor R130 is connected to the input voltage VCC1.5V, the second end of resistor R155 is grounded, and the ground pin GND of clock generator U1 is grounded.

10. The TTE analyzer working circuit according to claim 1, characterized in that: The data acquisition circuit board includes an FPGA module, and the FPGA module includes a processor chip D4, wherein the GPIO interface of the processor chip D4 is connected to an LED indicator light, the GTX pin of the processor chip D4 is connected to an SFP interface through an LVDS switch, the PCIE X4 interface of the processor chip D4 is connected to a data processing circuit board through a VPX connector, the processor chip D4 is connected to a VPX connector through an LVDS switch, and is connected to other data acquisition circuit boards through the VPX connector.

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