3D packaging, working components and computing devices

Abstract

The embodiment of the present application provides a 3D package, a working component and a computing device, including: a substrate; at least one memory module, the memory module including a first die and a second die stacked in a direction perpendicular to the substrate; the first die is arranged on one side of the substrate, and the second die is arranged on the side of the first die away from the substrate; one of the first die and the second die is a memory die, and the other is a logic processing die; a first protection medium and / or a second protection medium, the first protection medium is used to surround the first die on the side of the first die away from the substrate; in the case where a circuit element die is arranged between the first die and the second die, there is a second protection medium, which is used to surround the circuit element die between the first die and the second die. The technical solution of the embodiment of the present application can achieve ultra-large computing power and ultra-high storage bandwidth.

Description

Technical Field

[0001] The present application relates to the field of chip packaging technology, and in particular to a 3D package, a working component and a computing device. Background Art

[0002] In traditional 2D packaging, chips are packaged on the same plane, limiting further miniaturization and performance improvement. Although 3D packaging technology saves space and improves performance through vertical stacking, there may be problems such as long interconnection distance, insufficient interconnection density, single function or lack of sufficient bare die protection measures. Integrating chips with different functions in one package may have challenges such as insufficient integration, high design complexity, thermal management and signal integrity issues. Utility Model Content

[0003] The embodiments of the present application provide a 3D package, a working component and a computing device to solve or alleviate one or more technical problems in the prior art.

[0004] As one aspect of an embodiment of the present application, an embodiment of the present application provides a 3D package, comprising: a substrate; at least one memory module, the memory module comprising a first die and a second die stacked in a direction perpendicular to the substrate; the first die is arranged on one side of the substrate, and the second die is arranged on a side of the first die away from the substrate; one of the first die and the second die is a memory die, and the other is a logic processing die; a first protective medium and / or a second protective medium, wherein the first protective medium is used to surround the first die on a side of the first die away from the substrate; in the case where a circuit element die is arranged between the first die and the second die, there is a second protective medium, which is used to surround the circuit element die between the first die and the second die.

[0005] In one embodiment, a difference between an orthographic projection area of ​​the second die on the substrate and an orthographic projection area of ​​the first die on the substrate is smaller than a preset threshold.

[0006] In one embodiment, a through-mold via TMV is disposed in the first protection medium and penetrates the first protection medium in a direction perpendicular to the substrate, and signals in the TMV are respectively connected to the second die and the substrate.

[0007] In one implementation, when there are multiple memory modules, the first protection media of the multiple memory modules are an integrated structure.

[0008] In one embodiment, the memory module further includes a first redistribution interposer disposed between the first protection medium and the substrate, and the signal in the TMV is connected to the first redistribution interposer; and / or, the memory module further includes a second redistribution interposer disposed between the first protection medium and the second die, and the signal in the TMV is connected to the second redistribution interposer.

[0009] In one implementation, when there are multiple memory modules, the first redistribution interposers of the multiple memory modules are interconnected, and / or the second redistribution interposers of the multiple memory modules are interconnected.

[0010] In one embodiment, the memory module further includes the circuit element die, and the circuit element die is surrounded by the second protection medium.

[0011] In one embodiment, the orthographic projection of the first die on the substrate covers the orthographic projection of the circuit component die on the substrate, and the orthographic projection of the second die on the substrate covers the orthographic projection of the circuit component die on the substrate.

[0012] In one implementation, the memory module further includes the circuit element die, and the first protection medium surrounds the circuit element die.

[0013] In one embodiment, the memory module further includes the circuit element die, which is disposed between the substrate and the first die.

[0014] As one aspect of an embodiment of the present application, an embodiment of the present application provides a working component, including a 3D package in any one implementation of the embodiment of the present application and a printed circuit board, wherein the 3D package is arranged on one side of the printed circuit board.

[0015] As one aspect of an embodiment of the present application, an embodiment of the present application provides a computing device, including a working component and a power supply module in any implementation manner of the embodiment of the present application.

[0016] The technical solution of the embodiment of the present application provides a 3D packaging solution, which can add some special circuit functions or die protection functions while stacking the first die and the second die in the vertical direction, thereby enriching the application scenarios of 3D packaging while achieving smaller chip area, ultra-large computing power, shorter interconnection distance, and higher interconnection density.

[0017] The above summary is for illustrative purposes only and is not intended to be limiting in any way. In addition to the illustrative aspects, embodiments and features described above, further aspects, embodiments and features of the present application will be readily apparent by reference to the accompanying drawings and the following detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In the accompanying drawings, unless otherwise specified, the same reference numerals throughout the multiple drawings represent the same or similar parts or elements. These drawings are not necessarily drawn to scale. It should be understood that these drawings only depict some embodiments disclosed in the present application and should not be regarded as limiting the scope of the present application.

[0019] Figure 1 , Figure 2A , Figure 2B , Figure 2C and Figure 2D The structural diagrams of 3D packages according to different implementations of the first embodiment of the present application are respectively shown;

[0020] Figure 3A , Figure 3B , Figure 3C and Figure 3D The structural diagrams of 3D packages according to different implementations of the second embodiment of the present application are respectively shown;

[0021] Figure 4A and Figure 4B The structural diagrams of 3D packages according to different implementations of the third embodiment of the present application are respectively shown;

[0022] Figure 5A and Figure 5B The structural diagrams of 3D packages according to different implementations of the fourth embodiment of the present application are respectively shown;

[0023] Fig. 6A , Figure 6B , Fig. 7A , Figure 7B , Fig. 8A and Figure 8B The structural diagrams of 3D packages according to different implementations of the fifth embodiment of the present application are respectively shown;

[0024] Fig. 9 Shown is a structural diagram of the working components according to the sixth embodiment of the present application.

[0025] Description of reference numerals:

[0026] 20: substrate; 100: memory module; 101: first bare chip; 102: second bare chip;

[0027] 401: first protection medium; 501: TMV; 103: TSV;

[0028] 104: C4 bump; 105: micro bump;

[0029] 106: RDL medium; 107: RDL wiring layer;

[0030] 111: a first redistribution intermediary layer; 112: a second redistribution intermediary layer;

[0031] 202: second protective medium; 201: circuit element die;

[0032] 30: PCB board; 50: connecting wire; 109: solder ball;

[0033] 40: 3D package. DETAILED DESCRIPTION

[0034] In the following, only some exemplary embodiments are briefly described. As those skilled in the art will appreciate, the described embodiments may be modified in various ways without departing from the spirit or scope of the present application. Therefore, the drawings and descriptions are considered to be exemplary and non-restrictive in nature.

[0035] As technology develops, the integration of chips becomes higher and higher, and the performance is constantly improving. However, as technology further develops, it becomes more and more challenging to integrate more functions and components on a single chip, which also increases the cost and complexity of manufacturing.

[0036] In order to overcome these challenges, the concept of chiplet began to emerge in the field of semiconductor manufacturing technology. A chiplet can be understood as a small, independent chip module, which usually contains a specific functional unit or processing unit. Unlike traditional single chips, chiplets split the entire system into multiple smaller and more focused parts. These chiplets can be designed, manufactured and tested independently, and then combined together in a package to form a complete functional system or processing system to achieve higher flexibility, performance optimization and cost reduction design and manufacturing methods. Chiplet is an innovative solution to the challenges of complexity and cost in the context of continuous improvement of chip technology and performance.

[0037] Under the technical concept of chiplet, 2.5D packaging solutions have emerged, such as chip-on-wafer-on-substrate (CoWoS). In an exemplary CoWoS solution, the logic processing die and high bandwidth memory (HBM) stack are integrated together, usually by laying out multiple HBM stacks around the Logic die to provide excellent computing and memory performance. Among them, the Logic die is the core computing unit of the CoWoS packaged chip, which contains a large number of graphics processing units (GPUs) for high-performance computing tasks; the HBM stack uses 3D stacking technology to stack multiple memory chip components together and communicate through silicon through holes (TSV) to provide high-bandwidth and low-latency memory access.

[0038] The CoWoS solution allows multiple chips with different functions to be integrated into a single package, providing higher performance and efficiency. However, compared with other packaging solutions with the same computing power and bandwidth, the chip packaging area of ​​its CoWoS solution will also be larger, and the power consumption and cost will be higher.

[0039] Therefore, mature 3D packaging technology is urgently needed in the field of memory packaging to achieve ultra-large computing power and ultra-high storage bandwidth without increasing the chip packaging area. The present application aims to provide a 3D packaging solution that can add some special circuit functions or die protection functions while stacking the first die and the second die in the vertical direction, thereby enriching the application scenarios of 3D packaging while reducing the chip area, ultra-large computing power, shorter interconnection distance, and higher interconnection density. Among them, the 3D packaging solution provided in the embodiment of the present application is based on a memory module, that is, one of the first die and the second die is a memory die, and the other is a logic processing die.

[0040] The memory die may be a chip die of any type of memory, such as dynamic random access memory (DRAM), static random access memory (SRAM), non-volatile random access memory (NVRAM), flash memory, or electrically erasable programmable read-only memory (EEPROM). Exemplarily, the memory die may be a customized chip die or a standardized chip die, which is not limited in the embodiments of the present application.

[0041] The logic processing die may be a chip die responsible for the logic processing function. Exemplarily, the logic processing die may include a memory control unit, may include a processor unit, or may include a memory control unit and a processor unit. Wherein, the processor unit is, for example, a central processing unit (CPU), a graphics processing unit (GPU), a data processor (DPU), or a knowledge processor (KPU), a tensor processor (TPU), an intelligent processor (IPU), a reconfigurable dataflow unit (Reconfigurable Dataflow Unit), a neural network processor (NPU) or other types of processors (Any type Processing Unit, xPU), responsible for executing instructions and performing various calculations and data processing tasks, including simple arithmetic operations and complex logical operations, so as to realize functions such as calculation, control, and decision-making. The memory control unit is responsible for managing and coordinating part of the memory access, such as converting the memory operation requested by the processor into the operation of the memory, and ensuring the correct transmission and storage of data to achieve efficient memory access and data transmission.

[0042] It should be noted that in the embodiment of the present application, a chip (Chip) is a small silicon wafer (or other semiconductor materials) on which multiple electronic components (such as transistors, capacitors, resistors, etc.) and circuit connections are integrated. These components and connections form a complex circuit that can perform various functions, thereby achieving tasks such as computing, storage, control, and signal processing. That is, the chip is a highly integrated electronic device. A die refers to an unpackaged, single chip. In the chip manufacturing process, many identical chips are usually manufactured on a silicon wafer (or a wafer of other materials). Each such chip is called a die, which contains a specific circuit design and function. The die will be separated after manufacturing and can be further packaged into finished chips or used for other applications.

[0043] For example, the 3D package provided in the embodiment of the present application can be used for high-performance computing chips, sensor chips, micro-electro-mechanical systems (MEMS), optical communication chips, etc. It should be noted that the above application scenarios or application examples provided in the embodiment of the present application are for ease of understanding, and the embodiment of the present application does not specifically limit the application of the 3D package.

[0044] The following is a detailed description of the technical solution of the present application and how the technical solution of the present application solves the above-mentioned technical problems with specific embodiments. The listed specific embodiments may be combined with each other, and the same or similar concepts or processes may not be described in detail in some embodiments.

[0045] Embodiment 1

[0046] Figure 1 The structure diagram of the 3D package provided by the embodiment of the present application is shown. Figure 1 As shown, the 3D package includes a substrate 20 and at least one memory module 100 , and the memory module 100 is arranged on one side of the substrate 20 .

[0047] The substrate 20 is used as a packaging substrate, and its material includes an organic substrate, a ceramic substrate, a sapphire substrate, etc. Different applications and requirements may select different types of materials, which are not limited in the embodiments of the present application.

[0048] The memory module 100 includes a first die 101 and a second die 102, one of which is a memory die and the other is a logic processing die. The first die 101 is arranged on one side of the substrate 20, and the second die 102 is arranged on the side of the first die 101 away from the substrate 20.

[0049] In one embodiment, the difference between the orthographic projection area of ​​the second die 102 on the substrate 20 and the orthographic projection area of ​​the first die 101 on the substrate 20 is less than a preset threshold. In other words, the size difference between the second die 102 and the first die 101 is small or the orthographic projection area of ​​the second die 102 on the substrate 20 is equal to the orthographic projection area of ​​the first die 101 on the substrate 20, which is insufficient to horizontally expand multiple second die 102 on the same side of the first die 101.

[0050] It should be noted that in each embodiment of the present application, the horizontal direction is a direction parallel to the substrate 20 , and the vertical direction is a direction perpendicular to the substrate 20 .

[0051] Furthermore, the memory module 100 provided in the embodiment of the present application further includes a first protective medium 401, and the first protective medium 401 is used to surround the first die 101 on a side of the first die 101 away from the substrate 20, such as Figure 1 That is to say, in this embodiment, the side of the first die 101 away from the substrate 20 is surrounded by the first protective medium 401 and is not in contact with the air. This packaging form is more suitable for chip packaging scenarios where the size of the first die 101 is not too large and requires special protection.

[0052] In one embodiment, the material of the first protective medium 401 can be a molding material, or it can be an underfill material or other material used for protective filling, including organic materials or inorganic materials. Molding materials include but are not limited to epoxy resin, silicone rubber, phenolic resin, polyimide, polytetrafluoroethylene (PTFE), etc., and underfill materials include but are not limited to epoxy resin, acrylic resin, silicone rubber, polyurethane, etc. The corresponding molding material or filling material can be selected according to the material characteristics and packaging requirements, and the embodiment of the present application is not limited to this.

[0053] Furthermore, if Figure 1 As shown, a through molding via (TMV) 501 penetrating the first protective medium in a direction perpendicular to the substrate 20 is provided in the first protective medium 401 , and the signal in the TMV 501 is connected to the second die 102 and the substrate 20 respectively.

[0054] Based on this, the second die 102 can be interconnected with the substrate 20 by means of TMV501, and the first die 101 can also be interconnected with the second die 102 by means of TMV501. In semiconductor packaging, TMV is used to form an electrical connection channel during the molding packaging process to interconnect two components. In the embodiment of the present application, based on TMV, the volume of the 3D package can be effectively reduced, the packaging density can be increased, and the electrical performance and thermal performance of the package can also be improved.

[0055] There are many ways to interconnect the first die 101 and the substrate 20 , and there are many ways to interconnect the first die 101 and the second die 102 , such as interconnecting by means of an intermediate layer, a through hole, a bonding, or a bump.

[0056] Specifically, the interposer can help the components of the upper or lower layers to interconnect electrical properties and exchange information. There are many types of interposers, which can be selected according to actual needs. In the embodiment of the present application, the redistribution layer (RDL) interposer is mainly selected. The through hole is, for example, TMV. The bump may include a controlled collapse chip connection bump (Controlled Collapse Chip Connection, referred to as C4 bump or C4 bump) or a micro bump (ubump); the bonding is mainly hybrid bonding (Hybrid Bonding).

[0057] The following will introduce the interconnection method between the first die 101 and the substrate 20, and the interconnection method between the first die 101 and the second die 102 through specific examples. It should be noted that one interconnection method can be used alone in a memory module, or multiple interconnection methods can be used simultaneously in a memory module, which is not limited in the embodiments of the present application.

[0058] In one interconnected approach, Figure 2A As shown, the memory module 100 further includes a first redistribution interposer 111 disposed between the first protection medium 401 and the substrate 20 , and the signal in the TMV 501 is connected to the first redistribution interposer 111 .

[0059] The RDL interposer generally includes an RDL medium 106 and an RDL wiring layer 107 (eg, Figure 2A). The RDL medium 106 is usually made of organic materials; the common material of the RDL wiring layer 107 is electroplated copper (Plated Cu) supplemented with a titanium and copper sputtering layer as a primer; the surface of the copper layer is covered with a corresponding protective layer ink as needed. In other words, based on the RDL wiring layer 107 in the first redistribution interposer 111, the remaining signals other than the interconnection signals of the first die 101 and the second die 102 can be connected to the substrate 20. For example, after the first die 101 and the second die 102 are interconnected, the remaining signals of the first die 101 can be connected to the substrate 20 through the TMV501, and the remaining signals of the second die 102 can be connected to the substrate 20 through the RDL wiring layer 107.

[0060] In one example, the first redistribution interposer 111 and the first die 101 are interconnected by hybrid bonding. In another example, the first redistribution interposer 111 and the first die 101 are interconnected by micro bumps 105 .

[0061] Among them, hybrid bonding can usually realize the transmission of electrical signals and data without the use of solder or conductive materials, thereby reducing the loss of signal transmission. Since the connection is very close, high-density stacking can be achieved through hybrid bonding, thereby realizing more functions in a smaller package size. Microbumps are tiny raised structures, usually made of metal materials, usually manufactured through microelectronic processes, and their size, position and arrangement can be precisely controlled. Based on this, high-density and precise interconnection between the first bare chip 101 and the first redistribution interposer 111 can be achieved.

[0062] In one interconnected approach, Figure 2A As shown, the memory module 100 further includes a second redistribution interposer 112 disposed between the first protection medium 401 and the second die 102, and the signal in the TMV 501 is connected to the second redistribution interposer 112. In other words, the signal of the second die 102 can be connected to the RDL wiring layer in the second redistribution interposer 112 through the TMV 501, thereby realizing the interconnection between the first die 101 and the second die 102 based on the second redistribution interposer 112.

[0063] In one example, the second redistribution interposer 112 is interconnected with the second die 102 by hybrid bonding. In another example, the second redistribution interposer 112 is interconnected with the second die 102 by microbumps 105. Based on this, high-density interconnection between the second die 102 and the second redistribution interposer 112 can be achieved, and the interconnection accuracy can be improved.

[0064] Through the first redistribution interposer 111 and the second redistribution interposer 112 , the signals in the TMV 501 can be connected to the first die 101 and the second die 102 , respectively, so as to realize the interconnection between the first die 101 and the second die 102 .

[0065] In one interconnection method, a C4 bump 104 is connected to the side of the substrate 20 facing the first bare chip 101. The C4 bump is made by a bumping process, and the core process flow is metal deposition, and the most common metal deposition steps include the deposition of the under bump metallization layer (UBM) and the deposition of the bump itself. The deposition of the under bump metallization layer (UBM) is usually achieved by sputtering, electroless plating, plating, etc.; the deposition of the bump itself is usually achieved by electroplating, ball planting, and printing.

[0066] Through the C4 bumps, the signals in the first redistribution interposer 111 can be connected to the substrate 20 with high density, thereby realizing high-density and precise interconnection between the first bare die 101 and the substrate 20; through the C4 bumps and the first redistribution interposer 111, the signals in the TMV501 can be connected to the substrate 20, thereby realizing high-density and precise interconnection between the second bare die 102 and the substrate 20.

[0067] It should be noted that the embodiment of the present application does not limit the projection area size and projection correspondence relationship of the second die 102 and the second redistribution interposer 112 on the substrate 20. For example, the projection areas of the second die 102 and the second redistribution interposer 112 on the substrate 20 may be the same or different, such as the projection area of ​​the second die 102 on the substrate 20 is slightly smaller than the projection area of ​​the second redistribution interposer 112 on the substrate 20. For another example, the projections of the second die 102 and the second redistribution interposer 112 on the substrate 20 may coincide or overlap.

[0068] In one interconnected approach, Figure 2B As shown, the second redistribution interposer 112 and the first die 101 are interconnected by hybrid bonding, or the second redistribution interposer 112 and the first die 101 are interconnected by micro bumps 105 .

[0069] That is, the first die 101 is interconnected with the second redistribution interposer 112. The signal in the second redistribution interposer 112 can be connected to the second die 102, thereby realizing high-density interconnection between the first die 101 and the second die 102; the signal in the second redistribution interposer 112 can be connected to the TMV 501, and then connected to the substrate 20, thereby realizing high-density interconnection between the first die 101 and the substrate 20.

[0070] In one embodiment, when there are multiple memory modules 100 (for example, three memory modules are used as an example in the embodiment of the present application), the first protection mediums of the multiple memory modules 100 are an integrated structure, that is, the first protection mediums of the memory modules 100 are connected into a layer, such as Figure 2C and Figure 2D As shown. In one embodiment, when there are multiple memory modules 100, the first redistribution interposers 111 of the multiple memory modules 100 are interconnected together. In one embodiment, when there are multiple memory modules 100, the second redistribution interposers 112 of the multiple memory modules 100 are interconnected together. Based on this, the process flow in the packaging process can be simplified and the packaging efficiency can be improved.

[0071] According to the 3D package of the embodiment of the present application, a memory module is provided, including a first bare chip molding structure and a second bare chip stacked in a vertical direction. Since the first bare chip is surrounded by a first protective medium and is not in contact with the air, this packaging form is more suitable for the core 3D packaging scenario where the first bare chip is not too large and requires special protection.

[0072] Embodiment 2

[0073] This embodiment provides a 3D package, which adds a circuit element die structure on the basis of the first embodiment. Therefore, all or part of the implementation methods and corresponding technical effects of the first embodiment can be referenced to this embodiment.

[0074] like Figure 3A and Figure 3B As shown, the memory module 100 of the embodiment of the present application further includes a circuit element die 201, and the circuit element die 201 is surrounded by a second protection medium 202. The second protection medium 202 is disposed between the first die 101 and the second die 102. In this embodiment, the second protection medium 202 is specifically disposed between the second redistribution interposer 112 and the second die 102.

[0075] Based on this, some special circuit functions may be added to realize the memory module 100 , and the specific circuit functions realized correspond to the functions of the circuit element die 201 .

[0076] For example, the circuit element die 201 may be a Deep Trench Capacitor (DTC) die. DTC is a capacitor whose capacitance value can be controlled by a digital signal and is widely used in the design of radio frequency and microwave frequency circuits, such as high frequency filters, oscillators, etc.

[0077] For another example, the circuit element die 201 may also be a resistance-inductance-capacitance (RLC) die. The RLC die is an RLC circuit implemented by semiconductor technology and can be used for filters, tuning circuits, oscillators, impedance matching, power management, noise elimination, etc.

[0078] The material of the second protection medium 202 may be a molding material, an underfill material or other materials used for protection and filling, including organic materials or inorganic materials, as long as the second protection medium can protect the circuit element die 201 .

[0079] The circuit element die 201 can be interconnected with the first die 101, or with the second die 102, or with the first die 101 and the second die 102 respectively. The circuit element die 201 can also be interconnected with the substrate 20, which can be configured according to the application scenario, circuit function or product requirements of the 3D package. This will be described in detail below. It should be noted that one interconnection method can be used alone in a memory module, or multiple interconnection methods can be used simultaneously in a memory module, and the embodiments of the present application do not limit this.

[0080] In one interconnected approach, Figure 3A and Figure 3B As shown, the second die 102 and the circuit element die 201 are directly interconnected by hybrid bonding, or the second die 102 and the circuit element die 201 are directly interconnected by micro bumps 105. Based on this, the interconnection distance can be reduced and the effect and efficiency of signal transmission can be improved.

[0081] In one interconnected approach, Figure 3C and Figure 3D As shown, the second redistribution interposer 112 and the circuit element die 201 are interconnected by hybrid bonding, or the second redistribution interposer 112 and the circuit element die 201 are interconnected by micro bumps 105 .

[0082] Specifically, the first die 101 is interconnected with the second redistribution interposer 112 by hybrid bonding (or micro-bumps 105), thereby further realizing the interconnection between the first die 101 and the circuit element die 201. The second die 102 is interconnected with the second redistribution interposer 112 by hybrid bonding (or micro-bumps 105), thereby further realizing the high-density interconnection between the second die 102 and the circuit element die 201. In addition, the first die 101 is connected to the second redistribution interposer 112 by hybrid bonding (or micro-bumps 105), and the second die 102 is connected to the second redistribution interposer 112 by hybrid bonding (or micro-bumps 105), thereby further realizing the high-density connection between the first die 101 and the second die 102.

[0083] For example, the signal in the second redistribution interposer 112 can be connected to the substrate 20 through the TMV 501, or connected to the substrate 20 through the TMV 501 and the first redistribution interposer 111, so as to further realize the high-density interconnection between the substrate 20 and the circuit element die 201. The direction or realization of the above interconnection signal is only an example, and can be wired and configured according to actual needs, and the embodiment of the present application is not limited to this.

[0084] In one embodiment, in order to reduce chip area or package volume, in the same memory module 100 , the orthographic projections of the first die 101 and the second die 102 on the substrate 20 both cover the orthographic projection of the circuit element die 201 on the substrate 20 .

[0085] Combination Figure 3A , Figure 3B , Figure 3C and Figure 3D It can be seen that the interconnection region between the second die 102 and the second redistribution interposer 112 is located outside the circuit element die 101 , so this interconnection will not increase the package volume.

[0086] Embodiment 3

[0087] This embodiment provides a 3D package, which adds a circuit element die structure on the basis of the first embodiment. Therefore, all or part of the implementation methods and corresponding technical effects of the first embodiment can be referenced to this embodiment.

[0088] like Figure 4A and Figure 4B As shown, the memory module 100 of the embodiment of the present application further includes a circuit element die 201 , and the circuit element die 201 is surrounded by a first protective medium 401 .

[0089] That is, the first protection medium 401 surrounds the circuit element die 201 and the first die 101 together, so that the memory module 100 can realize some special circuit functions while reducing the package volume and the interconnection distance.

[0090] The circuit element die 201 can be a DTC die, used as a high-frequency filter, oscillator, etc. of the chip; the circuit element die 201 can also be an RLC die, used as a filter, tuning circuit, oscillator, impedance matching, power management, noise elimination, etc. of the chip.

[0091] The circuit element die 201 can be interconnected with the first die 101, or with the second die 102, or with the first die 101 and the second die 102 respectively. The circuit element die 201 can also be interconnected with the substrate 20, which can be configured according to the application scenario, circuit function or product requirements of the 3D package. This will be described in detail below. It should be noted that one interconnection method can be used alone in a memory module, or multiple interconnection methods can be used simultaneously in a memory module, and the embodiments of the present application do not limit this.

[0092] In one interconnected approach, Figure 4A As shown, the circuit element die 201 is interconnected with the second redistribution interposer 112. For example, the circuit element die 201 can form a high-density interconnection with the second redistribution interposer 112 by hybrid bonding, or the circuit element die 201 can form a high-density interconnection with the second redistribution interposer 112 by micro bumps 105.

[0093] The signal of the second redistribution interposer 112 can be connected to the second die 102, thereby realizing the interconnection between the circuit element die 201 and the second die 102; the signal of the second redistribution interposer 112 can be connected to the substrate 20 through TMV501, or connected to the substrate 20 through TMV501 and the first redistribution interposer 111, thereby realizing the interconnection between the circuit element die 201 and the substrate 20; the signal of the second redistribution interposer 112 can be connected to the first die 101 through TMV501 and the first redistribution interposer 111, thereby realizing the interconnection between the circuit element die 201 and the first die 101. The direction or realization of the above interconnection signals is only an example, and can be wired and configured according to actual needs, and the embodiments of the present application are not limited to this.

[0094] In one interconnected approach, Figure 4BAs shown, the circuit element die 201 is interconnected with the first redistribution interposer 111. Exemplarily, the circuit element die 201 can form a high-density interconnection with the first redistribution interposer 111 by hybrid bonding, or the circuit element die 201 can form a high-density interconnection with the first redistribution interposer 111 by micro bumps 105.

[0095] The signal of the first redistribution interposer 111 can be connected to the second die 102 through TMV501, or connected to the second die 102 through TMV501 and the second redistribution interposer 112, so as to realize the interconnection between the circuit element die 201 and the second die 102; the signal of the first redistribution interposer 111 can be connected to the first die 101 through TMV501 and the second redistribution interposer 112, so as to realize the interconnection between the circuit element die 201 and the first die 101; the signal of the first redistribution interposer 111 can be connected to the substrate 20, so as to realize the interconnection between the circuit element die 201 and the substrate 20. The direction or realization of the above interconnection signals is only an example, and can be wired and configured according to actual needs, and the embodiments of the present application are not limited to this.

[0096] In one embodiment, in order to reduce chip area or package volume, in the same memory module 100 , the orthographic projections of the first die 101 and the second die 102 on the substrate 20 both cover the orthographic projection of the circuit element die 201 on the substrate 20 .

[0097] Combination Figure 4A and Figure 4B It can be seen that the TMV 501 is located outside the circuit element die 101 , so this interconnection will not increase the package volume.

[0098] Embodiment 4

[0099] This embodiment provides a 3D package, which adds a circuit element die structure on the basis of the first embodiment. Therefore, all or part of the implementation methods and corresponding technical effects of the first embodiment can be referenced to this embodiment.

[0100] like Figure 5A and Figure 5B As shown, the memory module 100 of the embodiment of the present application further includes a circuit element die 201 disposed between the substrate 20 and the first die 101 , that is, the circuit element die 201 is disposed between the substrate 20 and the first protective medium 401 .

[0101] Generally speaking, the thickness of the circuit element die 201 is smaller than the thickness of the C4 bump 104 . Therefore, by placing the circuit element die 201 between the substrate 20 and the first protective medium 401 , the memory module 100 can realize some special circuit functions while reducing the package volume.

[0102] The circuit element die 201 can be a DTC die, used as a high-frequency filter, oscillator, etc. of the chip; the circuit element die 201 can also be an RLC die, used as a filter, tuning circuit, oscillator, impedance matching, power management, noise elimination, etc. of the chip.

[0103] The circuit element die 201 can be interconnected with the first die 101, or with the second die 102, or with the first die 101 and the second die 102 respectively. The circuit element die 201 can also be interconnected with the substrate 20, and can be specifically configured according to the application scenario, circuit function or product requirements of the 3D package.

[0104] For example, Figure 5A and Figure 5B As shown, the circuit element die 201 is interconnected with the first redistribution interposer 111. Exemplarily, the circuit element die 201 can form a high-density interconnection with the first redistribution interposer 111 by hybrid bonding, or the circuit element die 201 can form a high-density interconnection with the first redistribution interposer 111 by micro bumps 105.

[0105] In one example, if Figure 5A As shown, the signal of the first die 101 can be connected to the first redistribution interposer 111, thereby realizing the interconnection between the circuit element die 201 and the first die 101; the signal of the second die 102 can be connected to the first redistribution interposer 111 through TMV501, or connected to the first redistribution interposer 111 through TMV501 and the second redistribution interposer 112, thereby realizing the interconnection between the circuit element die 201 and the second die 102; the signal of the first redistribution interposer 111 can be connected to the substrate 20, thereby realizing the interconnection between the circuit element die 201 and the substrate 20. The direction or realization of the above interconnection signals is only an example, and can be wired and configured according to actual needs, and the embodiments of the present application are not limited to this.

[0106] In one example, if Figure 5BAs shown, the signal of the first redistribution interposer 111 can be connected to the second die 102 through TMV501, or connected to the second die 102 through TMV501 and the second redistribution interposer 112, thereby realizing the interconnection between the circuit element die 201 and the second die 102; the signal of the first redistribution interposer 111 can be connected to the first die 101 through TMV501 and the second redistribution interposer 112, thereby realizing the interconnection between the circuit element die 201 and the first die 101; the signal of the first redistribution interposer 111 can be connected to the substrate 20, thereby realizing the interconnection between the circuit element die 201 and the substrate 20.

[0107] In addition, the signal of the first redistribution interposer 111 can be connected to the second die 102 through TMV501, or connected to the second die 102 through TMV501 and the second redistribution interposer 112; the signal of the first redistribution interposer 111 can be connected to the first die 101 through TMV501 and the second redistribution interposer 112, thereby realizing the connection between the first die 101 and the second die 102.

[0108] The direction or implementation of the above interconnection signals is only an example, and can be wired and configured according to actual needs, and the embodiments of the present application are not limited to this.

[0109] In one embodiment, in order to reduce chip area or package volume, in the same memory module 100, the orthographic projections of the first die 101 and the second die 102 on the substrate 20 both cover the orthographic projection of the circuit element die 201 on the substrate 20. Figure 5A and Figure 5B It can be seen that this interconnection does not increase the package size.

[0110] Embodiment 5

[0111] Fig. 6A The structure diagram of the 3D package provided by the embodiment of the present application is shown. Fig. 6A As shown, the 3D package includes a substrate 20 and at least one memory module 100 , and the memory module 100 is arranged on one side of the substrate 20 .

[0112] The memory module 100 includes a first die 101 and a second die 102, one of which is a memory die and the other is a logic processing die. The first die 101 is arranged on one side of the substrate 20, and the second die 102 is arranged on the side of the first die 101 away from the substrate 20.

[0113] Furthermore, the memory module 100 further includes a circuit element die 201 and a second protection medium 202, and the second protection medium 202 is used to surround the circuit element die 201 between the first die 101 and the second die 102. That is, the embodiment of the present application provides a case where the circuit element die 201 is arranged between the first die 101 and the second die 102, in which case the second protection medium 202 exists, the circuit element die 201 is surrounded by the second protection medium 202, and the second protection medium 202 is arranged between the first die 101 and the second die 102.

[0114] Based on this, some special circuit functions can be added to realize the memory module 100, and the specific circuit functions realized correspond to the functions of the circuit element die 201. The circuit element die 201 can be a DTC die, used as a high-frequency filter, oscillator, etc. of the chip; the circuit element die 201 can also be an RLC die, used as a filter, tuning circuit, oscillator, impedance matching, power management, noise elimination, etc. of the chip.

[0115] In one embodiment, the material of the second protection medium 202 may be a molding material, an underfill material or other materials used for protection and filling. That is, the circuit element die 201 is surrounded by the second protection medium, so that the circuit element die 201 can be protected.

[0116] Furthermore, a through silicon via (TSV) 103 is provided in the first die 101, and the signal in the TSV 103 can be connected to the substrate 20, so that the first die 101 and the substrate 20 are interconnected, and the signal in the TSV 103 can also be connected to the second die 102, so that the first die 101 and the second die 102 are interconnected.

[0117] A C4 bump 104 is provided between the first die 101 and the substrate 20 . The second die 102 can connect the signal to the TSV 103 through a micro bump or hybrid bonding. The signal in the TSV 103 is connected to the substrate 20 through the C4 bump 104 , thereby interconnecting the second die 102 and the substrate 20 .

[0118] The circuit element die 201 can be interconnected with the first die 101, or with the second die 102, or with the first die 101 and the second die 102 respectively. The circuit element die 201 can also be interconnected with the substrate 20, which can be configured according to the application scenario, circuit function or product requirements of the 3D package. This will be described in detail below. It should be noted that one interconnection method can be used alone in a memory module, or multiple interconnection methods can be used simultaneously in a memory module, and the embodiments of the present application do not limit this.

[0119] In one interconnected approach, Fig. 6A As shown, the second die 102 and the circuit element die 201 are directly interconnected by hybrid bonding, or the second die 102 and the circuit element die 201 are directly interconnected by micro bumps 105. Based on this, the interconnection distance can be reduced and the effect and efficiency of signal transmission can be improved.

[0120] In one interconnected approach, Figure 6B As shown, the first die 101 and the circuit element die 201 are directly interconnected by hybrid bonding, or the first die 101 and the circuit element die 201 are directly interconnected by micro bumps 105. Based on this, the interconnection distance can be reduced and the effect and efficiency of signal transmission can be improved.

[0121] In one interconnected approach, Fig. 7A and Figure 7B As shown, the memory module 100 further includes a first redistribution interposer 111 disposed between the first die 101 and the substrate 20, and the signal in the TSV 103 is connected to the first redistribution interposer 111. Based on this, a high-density interconnection between the first die 101 (or the second die 102) and the substrate 20 can be achieved, and the interconnection accuracy can be improved.

[0122] In one interconnected approach, Fig. 8A and Figure 8B As shown, the memory module 100 further includes a second redistribution interposer 112 disposed between the first die 101 and the second protection medium 202. The signal in the TSV 103 can be connected to the second redistribution interposer 112, thereby achieving high-density interconnection between the first die 101 and the circuit element die 201 (or the second die 102), and improving the interconnection accuracy.

[0123] Exemplarily, the second redistribution interposer 112 and the circuit element die 201 are interconnected by hybrid bonding, or the second redistribution interposer 112 and the circuit element die 201 are interconnected by micro bumps 105 .

[0124] In one embodiment, in order to reduce the chip area or packaging volume, in the same memory module 100, the orthographic projection of the first bare die 101 on the substrate 20 covers the orthographic projection of the circuit element bare die 201 on the substrate 20, and / or, the orthographic projection of the second bare die 102 on the substrate 20 covers the orthographic projection of the circuit element bare die 201 on the substrate 20.

[0125] It should be noted that the working component may include multiple memory modules 100, and the multiple memory modules 100 are arranged on one side of the substrate 20 to facilitate horizontal expansion of the memory modules 100. The embodiment of the present application does not limit the horizontal expansion method and the method of interconnection of the memory modules 100, and can be configured according to actual needs.

[0126] For example, in the memory module 100, the first die 101 may be a logic processing die. Further, based on the C4 bumps 104 and the substrate 20, a plurality of logic processing dies may be connected to each other, such as Fig. 6A , Figure 6B , Fig. 8A and Figure 8B Alternatively, based on the first redistribution interposer 111, C4 bumps and substrate 20, multiple logic processing dies can be connected to each other, such as Fig. 7A and 7B shown.

[0127] For example, in the memory module 100, the second die 102 may be a logic processing die. Further, based on the TSV 103, C4 bumps 104 and substrate 20 in the first die 101, a plurality of logic processing dies may be connected to each other, such as Fig. 6A and Figure 6B Alternatively, based on the TSV103 in the first die 101, the first redistribution interposer 111, the C4 bumps 104 and the substrate 20, multiple logic processing dies can be connected to each other, such as Fig. 7A and Figure 7B Alternatively, based on the second redistribution interposer 112, the TSV103 in the first die 101, the C4 bump 104 and the substrate 20, multiple logic processing dies can be connected to each other, such as Fig. 8A and Figure 8B shown.

[0128] For example, in the memory module 100, the second die 102 may be a logic processing die. Further, based on the second redistribution interposer 112, a plurality of logic processing dies may be connected to each other, or based on the second redistribution interposer 112, TMV501 and the first redistribution interposer 111, a plurality of logic processing dies may be connected to each other as shown in FIG. Figure 2C and Figure 2D shown.

[0129] For example, in the memory module 100, the first die 101 may be a logic processing die. Further, based on the first redistribution interposer 111, a plurality of logic processing dies may be connected to each other, such as Figure 2C Alternatively, based on the second redistribution interposer 112, multiple logic processing dies may be interconnected, such as Figure 2D Alternatively, based on the second redistribution interposer 112, TMV501 and the first redistribution interposer 111, multiple logic processing dies may be interconnected, such as Figure 2C and Figure 2D shown.

[0130] Embodiment 6

[0131] like Fig. 9 As shown, an embodiment of the present application provides a working component, including a printed circuit board (PCB) 30 and a 3D package 40, wherein at least one 3D package 40 is arranged on one side of the PCB 30.

[0132] The 3D package 40 may be any of the 3D packages described in the above application scenarios or embodiments. It should be noted that the working component may include one 3D package or multiple 3D packages, and the embodiment of the present application does not specifically limit the type, quantity, and interconnection topology of the 3D package 40.

[0133] Exemplarily, the 3D package 40 can be directly arranged on one side of the PCB board 30 without molding the 3D package 40 , that is, there is no need to plastic-encapsulate the memory module 100 on the side of the substrate 20 facing away from the PCB board 30 .

[0134] Exemplarily, the 3D package 40 is connected to the PCB board 30 via the solder balls 109 , thereby interconnecting the memory modules inside different 3D packages 40 on the PCB board 30 .

[0135] There may be multiple 3D packages 40 , and there are interconnected 3D packages among the multiple 3D packages 40 . For example, an interconnection relationship may be established between adjacent 3D packages through a PCB board 30 , thereby achieving PCB board-level interconnection between the 3D packages 40 .

[0136] In one embodiment, the 3D packages 40 are connected to each other on the PCB board 30 via connecting wires 50. Exemplarily, the connecting wires 50 may be any type of interconnection intellectual property (IP) components or modules such as Peripheral Component Interconnect Express (PCIE), Serializer / Deserializer (Serdes), Universal Chiplet Interconnect Express (UCIe), Compute Express Link (CXL), Remote Direct Memory Access (RDMA), Ethernet, etc.

[0137] According to the working components provided in the embodiments of the present application, the disadvantages of small storage bandwidth and small computing power of traditional packaging solutions can be avoided, and advanced packaging technology can be provided to increase storage bandwidth, thereby improving chip computing power.

[0138] Other structures of the 3D package or working components of the above-mentioned embodiments may adopt various technical solutions known to ordinary technicians in this field now and in the future, and will not be described in detail here.

[0139] Embodiment 7

[0140] The embodiment of the present application further provides a computing device, including any working component of the above embodiment and a power supply module, wherein the power supply module is used to provide power to the working component, and the number of the working components can be one or more, which is not limited in the embodiment of the present application. Exemplarily, at least some of the multiple working components are interconnected, which can be electrically connected or physically connected, which is not limited in the embodiment of the present application.

[0141] Illustratively, the computing device provided in the embodiments of the present application can be used in devices and systems that require a large amount of computing power, such as supercomputers, servers in data centers, high-performance workstations, scientific research equipment, etc., and can be applied in the fields of artificial intelligence, deep learning, big data analysis, etc.

[0142] Illustratively, the computing device provided in the embodiments of the present application can be used in various devices that need to monitor and measure physical or chemical changes, such as smart phones, automobiles, industrial automation equipment, medical equipment, and other fields that require high-performance sensor chips.

[0143] Illustratively, the computing device provided in the embodiments of the present application can be used in micro-electromechanical systems, such as gyroscopes and accelerometers of smartphones, airbag triggering systems of cars, micro-lens arrays of projectors, etc.

[0144] Illustratively, the computing device provided in the embodiments of the present application can be used in fiber-optic communication systems, such as fiber-optic network equipment, optical interconnection in data centers, long-distance fiber-optic transmission systems, and other fields that require high-speed data transmission.

[0145] When the computing device is used in different systems or fields, other components of the computing device may be different. Other components of the computing device in the above embodiment may adopt various technical solutions known to ordinary technicians in this field now and in the future, which will not be described in detail here.

[0146] In the description of this specification, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present application.

[0147] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features.

[0148] In this application, unless otherwise clearly specified and limited, the terms "installed", "connected", "connected", "fixed" and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, an electrical connection, or a communication; it can be a direct connection, or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0149] In the present application, unless otherwise clearly specified and limited, a first feature being "above" or "below" a second feature may include that the first and second features are in direct contact, or may include that the first and second features are not in direct contact but are in contact through another feature between them. Moreover, a first feature being "above", "above" and "above" a second feature includes that the first feature is directly above and obliquely above the second feature, or simply indicates that the first feature is higher in level than the second feature. A first feature being "below", "below" and "below" a second feature includes that the first feature is directly above and obliquely above the second feature, or simply indicates that the first feature is lower in level than the second feature.

[0150] The disclosure above provides many different embodiments or examples to realize the different structures of the present application. In order to simplify the disclosure of the present application, the parts and settings of specific examples are described above. Of course, they are only examples, and the purpose is not to limit the present application. In addition, the present application can repeat reference numerals and / or reference letters in different examples, and this repetition is for the purpose of simplification and clarity, which itself does not indicate the relationship between the various embodiments and / or settings discussed.

[0151] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with the technical field can easily think of various changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A 3D package, characterized in that: include: substrate; at least one memory module, the memory module comprising a first die and a second die stacked together; the first die is arranged on one side of the substrate, and the second die is arranged on a side of the first die away from the substrate; one of the first die and the second die is a memory die, and the other is a logic processing die; A first protective medium and / or a second protective medium, wherein the first protective medium is used to surround the first die on a side of the first die away from the substrate; and when a circuit element die is arranged between the first die and the second die, there is a second protective medium, which is used to surround the circuit element die between the first die and the second die.

2. The 3D package according to claim 1, characterized in that: A difference between an orthographic projection area of ​​the second die on the substrate and an orthographic projection area of ​​the first die on the substrate is smaller than a preset threshold.

3. The 3D package according to claim 1, characterized in that: The first protection medium is provided with a through-mold via TMV penetrating the first protection medium in a direction perpendicular to the substrate, and signals in the TMV are respectively connected to the second bare chip and the substrate.

4. The 3D package according to claim 3, characterized in that: When there are multiple memory modules, the first protection media of the multiple memory modules are an integrated structure.

5. The 3D package according to claim 3, characterized in that: The memory module also includes a first redistribution interposer disposed between the first protection medium and the substrate, and the signal in the TMV is connected to the first redistribution interposer; and / or, the memory module also includes a second redistribution interposer disposed between the first protection medium and the second die, and the signal in the TMV is connected to the second redistribution interposer.

6. The 3D package according to claim 5, characterized in that: When there are multiple memory modules, the first redistribution interposers of the multiple memory modules are interconnected, and / or the second redistribution interposers of the multiple memory modules are interconnected.

7. The 3D package according to any one of claims 1 to 6, characterized in that: The memory module further includes the circuit element die, and the circuit element die is surrounded by the second protection medium.

8. The 3D package according to claim 7, characterized in that: The orthographic projection of the first die on the substrate covers the orthographic projection of the circuit component die on the substrate, and the orthographic projection of the second die on the substrate covers the orthographic projection of the circuit component die on the substrate.

9. The 3D package according to any one of claims 1 to 6, characterized in that: The memory module further includes the circuit element die, and the first protection medium surrounds the circuit element die.

10. The 3D package according to any one of claims 1 to 6, characterized in that: The memory module further includes the circuit element die, which is disposed between the substrate and the first die.

11. A working component, characterized in that: include: The 3D package according to any one of claims 1 to 10; A printed circuit board, the 3D package is arranged on one side of the printed circuit board.

12. A computing device, characterized in that: It comprises the working component and the power supply module as claimed in claim 11.

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