Hardware delay circuit

Abstract

The present invention provides a hardware delay circuit, which includes an input circuit and an output circuit. The input circuit includes a first resistor, a third resistor and a control tube, and the output circuit includes a fourth resistor, a sixth resistor and a storage capacitor. When a pulse is at a high level, the control tube is turned on by a voltage divider between the first resistor and the third resistor, and a high-level signal generates a voltage drop at the sixth resistor through a voltage divider between the fourth resistor and the sixth resistor, so that a high level exists at the signal output end; when the pulse is at a low level, the storage capacitor discharges power through the sixth resistor, and the level of the signal output end is kept stable within this time by matching the capacitor resistance value, so that misjudgment is not likely to occur, and the delay circuit is simple and reliable with good stability.

Description

Technical Field

[0001] The present disclosure relates to the technical field of chargers, and in particular to a hardware delay circuit used for charger identification. Background Art

[0002] With the development of charger technology, many chargers on the market have realized the conversion from normal output level to pulse output, such as the existing technology CN112148051A, which can effectively avoid product damage caused by external interface damage. However, in pure hardware design, it is difficult to effectively match and identify pulse signals, and often the charger is mistakenly considered to be disconnected when the pulse is at a low level, resulting in logical judgment errors. Therefore, it is very necessary to design a simple pulse signal to level output hardware delay circuit in the electronic product market.

[0003] Currently, for pulse signal processing on the market, the use of single-chip microcomputer processing is the simplest and most effective; however, in the hardware circuit design without a single-chip microcomputer, either the pulse low-level signal is not processed, resulting in misjudgment, or it is implemented through devices such as triggers, conversion chips, and comparators, which is costly and complex in circuit design. Utility Model Content

[0004] The purpose of the present invention is to overcome the deficiencies in the prior art and to provide a hardware delay circuit and charger that are relatively simple to implement and less prone to misjudgment.

[0005] The purpose of this disclosure is achieved through the following technical solutions:

[0006] A hardware delay circuit, comprising:

[0007] An input circuit includes a first resistor, a third resistor and a control tube, wherein a first end of the first resistor is connected to a positive terminal of a charger, a second end of the first resistor is respectively connected to a control terminal of the control tube and a first end of the third resistor, a second end of the third resistor is connected to a negative terminal of the charger, and a first end of the control tube is connected to a first end of the first resistor;

[0008] The output circuit includes a fourth resistor, a sixth resistor and a storage capacitor. The first end of the fourth resistor is connected to the second end of the control tube, the second end of the fourth resistor is respectively connected to the first end of the sixth resistor and the upper half of the storage capacitor, the upper half of the storage capacitor is connected to the signal output end, the lower half of the storage capacitor is grounded, and the second end of the sixth resistor is connected to the lower half of the storage capacitor.

[0009] In one embodiment, the input circuit further includes a second resistor, a first end of the second resistor is connected to a second end of the first resistor, and a second end of the second resistor is connected to a control end of the control tube.

[0010] In one embodiment, the second resistor is a variable resistor.

[0011] In one embodiment, the input circuit further includes a filter capacitor, an upper end of the filter capacitor is connected to the first end of the first resistor, and a lower end of the filter capacitor is connected to the second end of the second resistor.

[0012] In one embodiment, the output circuit further includes a fifth resistor, a first end of the fifth resistor is connected to the second end of the fourth resistor, and a second end of the fifth resistor is connected to the upper half end of the storage capacitor.

[0013] In one embodiment, the output circuit further includes a universal diode, an anode of the universal diode is connected to the first end of the fifth resistor, and a cathode of the universal diode is connected to the second end of the fifth resistor.

[0014] In one embodiment, the fifth resistor is a variable resistor.

[0015] In one embodiment, at least one of the first resistor and the third resistor is a variable resistor.

[0016] In one embodiment, at least one of the fourth resistor and the sixth resistor is a variable resistor.

[0017] In one embodiment, the control tube is a PNP transistor.

[0018] Compared with the prior art, the present invention has at least the following advantages:

[0019] In the above-mentioned hardware delay circuit, when the pulse is at a high level, the control tube is turned on through the voltage divider of the first resistor and the third resistor, and the high-level signal is divided by the voltage of the fourth resistor and the sixth resistor, resulting in a voltage drop in the sixth resistor, so that a high level exists at the signal output end; when the pulse is at a low level, the storage capacitor discharges power through the sixth resistor, and the level of the signal output end can be kept stable during this time by matching the capacitor resistance value, and it is not easy to make a misjudgment, and the delay circuit is simple and reliable with good stability. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings required for use in the embodiments will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present disclosure and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0021] Figure 1 4 is a circuit diagram of a hardware delay circuit in one embodiment.

[0022] Figure numerals: 10, hardware delay circuit; 100, input circuit; 200, output circuit; R1, first resistor; R2, second resistor; R3, third resistor; R4, fourth resistor; R5, fifth resistor; R6, sixth resistor; C1, filter capacitor; C2, storage capacitor; Q1, control tube; D2, general diode; DOCT, signal output terminal. DETAILED DESCRIPTION

[0023] In order to facilitate the understanding of the present disclosure, the present disclosure will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present disclosure are given in the drawings. However, the present disclosure can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present disclosure more thoroughly and comprehensively understood.

[0024] It should be noted that when an element is referred to as being "fixed to" another element, it may be directly on the other element or there may be a central element. When an element is considered to be "connected to" another element, it may be directly connected to the other element or there may be a central element at the same time. The terms "vertical", "horizontal", "left", "right" and similar expressions used herein are for illustrative purposes only and do not represent the only implementation method.

[0025] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art of the present disclosure. The terms used herein in the specification of the present disclosure are only for the purpose of describing specific embodiments and are not intended to limit the present disclosure. The term "and / or" used herein includes any and all combinations of one or more related listed items.

[0026] In order to better understand the technical solutions and beneficial effects of the present invention, the present invention is further described in detail below in conjunction with specific embodiments:

[0027] like Figure 1 As shown, the present disclosure provides a hardware delay circuit 10 , including an input circuit 100 and an output circuit 200 .

[0028] The input circuit 100 includes a first resistor R1, a third resistor R3 and a control tube Q1, wherein a first end of the first resistor R1 is connected to a positive terminal of a charger, a second end of the first resistor R1 is respectively connected to a control terminal of the control tube Q1 and a first end of the third resistor R3, a second end of the third resistor R3 is connected to a negative terminal of the charger, and a first end of the control tube Q1 is connected to a first end of the first resistor R1;

[0029] The output circuit 200 includes a fourth resistor R4, a sixth resistor R6 and a storage capacitor C2. The first end of the fourth resistor R4 is connected to the second end of the control tube Q1, the second end of the fourth resistor R4 is respectively connected to the first end of the sixth resistor R6 and the upper half end of the storage capacitor C2, the upper half end of the storage capacitor C2 is connected to the signal output end DOCT, the lower half end of the storage capacitor C2 is grounded, and the second end of the sixth resistor R6 is connected to the lower half end of the storage capacitor C2.

[0030] Furthermore, the control tube Q1 is a PNP transistor, a first end of which is an emitter, a second end of which is a collector, and a control end of which is a base.

[0031] In this embodiment, when the charger outputs a high-level pulse, the voltage across the first resistor R1 reaches the conduction condition of the control tube Q1 through the voltage division of the first resistor R1 and the third resistor R3, thereby turning on the control tube Q1. At this time, the high-level signal charges the storage capacitor C2 until a high level exists at the signal output terminal DOCT, and the level is the voltage drop generated at the sixth resistor R6 after the voltage is divided by the fourth resistor R4 and the sixth resistor R6; when the charger outputs a low-level pulse, the voltage cannot reach the conduction condition of the control tube Q1, thereby turning off the control tube Q1. At this time, the storage capacitor C2 is discharged and delayed through the sixth resistor R6. By adjusting the resistance value of the sixth resistor R6, the level of the signal output terminal DOCT can be kept stable during the discharge period, and it is not easy to make a misjudgment. In addition, the delay circuit is simple and reliable, and has good stability.

[0032] Furthermore, the sixth resistor R6 and the storage capacitor C2 form a resistor-capacitor delay circuit, and the circuit is delayed by the charge and discharge characteristics of the capacitor, and the capacitor resistance value can be matched according to the required delay time.

[0033] In one embodiment, the input circuit 100 further includes a second resistor R2, a first end of the second resistor R2 is connected to the second end of the first resistor R1, and a second end of the second resistor R2 is connected to the control end of the control tube Q1. It can be understood that the second resistor R2 is connected to the control end of the control tube Q1 to further protect the control tube Q1 and reduce the possibility of breakdown of the control tube Q1 due to excessive current.

[0034] In one embodiment, the second resistor R2 is a variable resistor. It is understood that when the second resistor R2 is a variable resistor, the conduction condition of the control tube Q1 can be adjusted by adjusting the resistance value of the second resistor R2, so as to further adapt to more models of control tubes Q1.

[0035] In one embodiment, the input circuit 100 further includes a filter capacitor C1, the upper half of the filter capacitor C1 is connected to the first end of the first resistor R1, and the lower half of the filter capacitor C1 is connected to the second end of the second resistor R2. In this embodiment, the second resistor R2 and the filter capacitor C1 are added to form a resistor-capacitor circuit, so that the circuit can filter the charger signal to prevent signal interference from affecting the normal conduction or shutdown of the control tube Q1.

[0036] In one embodiment, the output circuit 200 further includes a fifth resistor R5, a first end of the fifth resistor R5 is connected to the second end of the fourth resistor R4, and a second end of the fifth resistor R5 is connected to the upper half of the storage capacitor C2. It can be understood that the fifth resistor R5 is added to better adjust the discharge speed of the storage capacitor C2 when the charger pulse is at a low level to match the width range of various pulse low levels.

[0037] In one embodiment, the output circuit 200 further includes a general diode D2, the anode of the general diode D2 is connected to the first end of the fifth resistor R5, and the cathode of the general diode D2 is connected to the second end of the fifth resistor R5. It can be understood that the provision of the general diode D2 can ensure that the current flows in one direction, accelerate the charging speed of the storage capacitor C2 when the charger pulse is at a high level, obtain a high-level signal at the signal output terminal DOCT more quickly, and avoid the situation where the circuit components are damaged due to the backflow of current.

[0038] In one embodiment, the fifth resistor R5 is a variable resistor. It can be understood that when the fifth resistor R5 is a variable resistor, the discharge speed of the storage capacitor C2 when the charger pulse is at a low level can be adjusted by adjusting the resistance value of the fifth resistor R5.

[0039] In one embodiment, at least one of the first resistor R1 and the third resistor R3 is a variable resistor. It is understood that when one or both of the first resistor R1 and the third resistor R3 are variable resistors, the resistance value of one or both of the first resistor R1 and the third resistor R3 can be adjusted to adjust the resistance ratio of the first resistor R1 and the third resistor R3, thereby adjusting the conduction condition of the control tube Q1 under the voltage division of the first resistor R1 and the third resistor R3.

[0040] In one embodiment, at least one of the fourth resistor R4 and the sixth resistor R6 is a variable resistor. It is understood that when one or both of the fourth resistor R4 and the sixth resistor R6 are variable resistors, the resistance value of one or both of the fourth resistor R4 and the sixth resistor R6 can be adjusted to adjust the resistance ratio of the fourth resistor R4 and the sixth resistor R6 to obtain different DOCT levels at the signal output end.

[0041] The present disclosure also provides a charger detection technology, including the hardware delay circuit 10 of any of the above embodiments. When the device that needs to detect the insertion of a charger uses the hardware delay circuit 10, no matter the charger outputs a high level pulse or a low level pulse, its DOCT level stability is good.

[0042] Compared with the prior art, the present invention has at least the following advantages:

[0043] In the above-mentioned hardware delay circuit 10, when the pulse is at a high level, the control tube Q1 is turned on through the voltage divider of the first resistor R1 and the third resistor R3, and the high-level signal is divided by the voltage of the fourth resistor R4 and the sixth resistor R6, generating a voltage drop at the sixth resistor R6, so that a high level exists at the signal output terminal DOCT; when the pulse is at a low level, the storage capacitor C2 discharges the power through the sixth resistor R6, and by matching the capacitor resistance value, the level of the signal output terminal DOCT can remain stable during this time, and it is not easy to make a misjudgment, and the delay circuit is simple and reliable, and has good stability.

[0044] The above-mentioned embodiments only express several implementation methods of the present disclosure, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the disclosed patent. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present disclosure, and these all belong to the protection scope of the present disclosure. Therefore, the protection scope of the disclosed patent shall be subject to the attached claims.

Claims

1. A hardware delay circuit, characterized in that: include: An input circuit includes a first resistor, a third resistor and a control tube, wherein a first end of the first resistor is connected to a positive terminal of a charger, a second end of the first resistor is respectively connected to a control terminal of the control tube and a first end of the third resistor, a second end of the third resistor is connected to a negative terminal of the charger, and a first end of the control tube is connected to a first end of the first resistor; The output circuit includes a fourth resistor, a sixth resistor and a storage capacitor. The first end of the fourth resistor is connected to the second end of the control tube, the second end of the fourth resistor is respectively connected to the first end of the sixth resistor and the upper half of the storage capacitor, the upper half of the storage capacitor is connected to the signal output end, the lower half of the storage capacitor is grounded, and the second end of the sixth resistor is connected to the lower half of the storage capacitor.

2. The hardware delay circuit according to claim 1, characterized in that: The input circuit further includes a second resistor, a first end of the second resistor is connected to a second end of the first resistor, and a second end of the second resistor is connected to a control end of the control tube.

3. The hardware delay circuit according to claim 2, characterized in that: The second resistor is a variable resistor.

4. The hardware delay circuit according to claim 2, characterized in that: The input circuit further includes a filter capacitor, wherein an upper end of the filter capacitor is connected to a first end of the first resistor, and a lower end of the filter capacitor is connected to a second end of the second resistor.

5. The hardware delay circuit according to claim 1, characterized in that: The output circuit further includes a fifth resistor, a first end of the fifth resistor is connected to the second end of the fourth resistor, and a second end of the fifth resistor is connected to the upper half end of the storage capacitor.

6. The hardware delay circuit according to claim 5, characterized in that: The output circuit further includes a universal diode, an anode of the universal diode is connected to the first end of the fifth resistor, and a cathode of the universal diode is connected to the second end of the fifth resistor.

7. The hardware delay circuit according to claim 5, characterized in that: The fifth resistor is a variable resistor.

8. The hardware delay circuit according to claim 1, characterized in that: At least one of the first resistor and the third resistor is a variable resistor.

9. The hardware delay circuit according to claim 1, characterized in that: At least one of the fourth resistor and the sixth resistor is a variable resistor.

10. The hardware delay circuit according to claim 1, characterized in that: The control tube is a PNP type triode.

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