A super junction MOS semiconductor device

Abstract

The utility model relates to the technical field of MOS semiconductors, and discloses a super junction MOS semiconductor device, including a MOS semiconductor composed of a plurality of MOS cells, wherein the MOS cell includes a drain, a semiconductor epitaxial layer, a metal source and a gate; wherein the semiconductor epitaxial layer includes a substrate layer, a diffusion layer, a P well layer, a highly doped N well layer and a highly doped P body region; the P well layer includes a highly doped P well layer 1, a highly doped P well layer 2, a low doped P well layer 1 and a low doped P well layer 2; when the voltage of the gate is zero, free carriers exist in the charge channel formed in the low doped P well layer 2 and form a conductive path. The P+ region (high doped P well layer 18 body region) of the super junction structure is used to block the flow of charges between adjacent cells, thereby avoiding the problem that when the conduction states of the cells are different due to process differences, the better cells are subjected to a larger current, thereby causing premature damage, and then damaging the entire device.

Description

Technical Field

[0001] The utility model relates to the technical field of MOS semiconductors, and more specifically to a super junction MOS semiconductor device. Background Art

[0002] MOS semiconductor devices are power electronic devices manufactured using metal oxide semiconductor technology, used to control and regulate electrical energy. They are based on the MOS (metal oxide semiconductor) structure and mainly include types such as MOSFET (metal oxide semiconductor field effect transistor) and IGBT (insulated gate bipolar transistor).

[0003] The existing patent discloses a groove-gate semiconductor power device (publication number CN102723355A), and its technical solution can be summarized as follows: a groove-gate semiconductor power device, which adds two high-K dielectric regions on the left and right sides of the semiconductor drift region, and the two sides of the first semiconductor region in the semiconductor drift region are in contact with the two second semiconductor regions, and the two high-K dielectric regions are in contact with the other sides of the two second semiconductor regions respectively. The beneficial effect of the utility model is to reduce the specific on-resistance and improve the withstand voltage, and it is suitable for MOS devices or MOS-controlled semiconductor devices. In the technology disclosed in the patent, when a surge occurs in the circuit where the MOS device is located, when its pulse current flows into the MOS device, it is very easy to break down the semiconductor epitaxial layer. In addition, there is a phenomenon of charge interaction between the various cells of the MOS device. Once some cells have better conductivity, most of the charge will flow through these cells, thereby exacerbating the loss of the MOS device. Summary of the invention

[0004] The main technical problem solved by the utility model is to provide a super junction MOS semiconductor device, which solves the problems in the above-mentioned background technology.

[0005] To solve the above technical problems, according to one aspect of the utility model, more specifically, a super junction MOS semiconductor device includes a MOS semiconductor composed of a plurality of MOS cells, wherein the MOS cell includes a drain, a semiconductor epitaxial layer, a metal source and a gate;

[0006] Wherein, the semiconductor epitaxial layer includes a substrate layer, a diffusion layer, a P-well layer, a highly doped N-well layer and a highly doped P-body region;

[0007] The P-well layer includes a high-doped P-well layer 1, a high-doped P-well layer 2, a low-doped P-well layer 1 and a low-doped P-well layer 2;

[0008] When the voltage of the gate is zero, free carriers exist in the charge channel formed in the low-doped P-well layer 2 and form a conductive path; and when the gate voltage is applied to the gate, a reverse depletion layer is formed between the gate and the substrate layer and the charge density of the charge channel is reduced.

[0009] Furthermore, the diffusion layer includes a high-doped diffusion layer 1, a low-doped diffusion layer 1, a low-doped diffusion layer 2 and a high-doped diffusion layer 2.

[0010] Furthermore, the highly doped diffusion layer 2 is in contact with the low doped P well layer 2, and the doping concentration of the highly doped diffusion layer 2 is the same as the doping concentration of the highly doped N well layer.

[0011] Furthermore, the doping concentration of the highly doped diffusion layer 2 is higher than that of the highly doped diffusion layer 1; and the doping concentration of the low doped diffusion layer 2 is higher than that of the highly doped diffusion layer 2.

[0012] Furthermore, the first highly doped P-well layer and the second highly doped P-well layer between adjacent MOS cells are integrated as one.

[0013] Furthermore, in the P-well layer, only the highly doped P-well layer 2 is in ohmic contact with the metal source electrode.

[0014] Furthermore, the doping concentration of the highly doped P-well layer 2 is higher than the doping concentration of the highly doped P-well layer 1, and the doping concentration of the low doped P-well layer 2 is higher than the doping concentration of the low doped P-well layer 1.

[0015] Furthermore, the highly doped P body region is in contact with the substrate layer, and the highly doped P body region is located between the drain and the gate.

[0016] Furthermore, a gate oxide layer is deposited between the surface of the gate and the semiconductor epitaxial layer and the metal source.

[0017] The beneficial effects of the super junction MOS semiconductor device of the utility model are:

[0018] 1. The utility model blocks the flow of charges between adjacent cells and increases the service life of the device.

[0019] 2. The utility model improves the voltage resistance characteristics of the device.

[0020] 3. The utility model reduces the on-resistance of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] The utility model is further described in detail below with reference to the accompanying drawings and specific implementation methods.

[0022] Figure 1 It is a schematic diagram of the structure of a super junction MOS semiconductor device;

[0023] Figure 2 It is a schematic diagram of MOS cells in parallel in the utility model.

[0024] In the figure: 1. drain; 2. substrate layer; 3. highly doped P body region; 4. metal source; 5. gate oxide layer; 6. gate; 7. highly doped diffusion layer 1; 8. highly doped P well layer 1; 9. highly doped P well layer 2; 10. highly doped N well layer; 11. low doped P well layer 1; 12. low doped P well layer 2; 13. low doped diffusion layer 1; 14. low doped diffusion layer 2; 15. highly doped diffusion layer 2. DETAILED DESCRIPTION

[0025] The present invention will be described in detail below with reference to the accompanying drawings and in combination with embodiments. It should be noted that the embodiments and features in the embodiments of the present application can be combined with each other without conflict.

[0026] like Figure 1-2 As shown, according to one aspect of the utility model, a super junction MOS semiconductor device is provided, which utilizes the P+ region (highly doped P well layer-8 body region) of the super junction structure to block the flow of charges between adjacent cells, thereby avoiding the problem that when the cells are in different conduction states due to process differences, the better cells are subjected to a larger current, resulting in premature damage, thereby damaging the entire device;

[0027] When the super junction MOS semiconductor device is in a blocking state, the P+ region depletion layer diffuses toward the JFET, and can easily diffuse through the N+ injection region (highly doped diffusion layer 215 region), and cover the entire JFET region, without reducing the blocking characteristics of the device. In addition, the utility model adds a P+ region (highly doped P body region 3 body region) between the epitaxial layer and the substrate layer, so that when the device is in a blocking state, the conductive path is quickly turned off and the electric field is balanced, so that the device has a higher withstand voltage effect;

[0028] Moreover, when the superjunction MOS semiconductor device is in the on state, the P+ region between the substrate and the epitaxy is depleted by the N+ region, and carriers can easily pass through this region without having a negative impact on the on-resistance of the device. In addition, the utility model provides more carriers for the device when it is on by adding an N+ region (N+ concentration is lower than P+ concentration and higher than N- concentration) of a highly doped diffusion layer 7 in the middle of the superjunction structure, so that the device has a lower on-resistance when it is on.

[0029] like Figure 1As shown, a super junction MOS semiconductor device includes a MOS semiconductor composed of a plurality of MOS cells, wherein the MOS cell includes a drain 1, a semiconductor epitaxial layer, a metal source 4 and a gate 6; wherein the semiconductor epitaxial layer includes a substrate layer 2, a diffusion layer, a P well layer, a highly doped N well layer 10 and a highly doped P body region 3; the P well layer includes a highly doped P well layer 1 8, a highly doped P well layer 2 9, a low doped P well layer 1 11 and a low doped P well layer 2 12; the design of depositing a highly doped P body region 3 between the diffusion layer 7 and the substrate layer 2 can improve the voltage resistance of the MOS device without affecting the conductive performance of the MOS device.

[0030] When the voltage of the gate 6 is zero, the charge channel formed in the low-doped P-well layer 2 12 has free carriers and forms a conductive path; when the gate 6 applies a gate voltage, a reverse depletion layer is formed between the gate 6 and the substrate layer 2 and the charge density of the charge channel is reduced. In this way, when the reverse depletion layer expands to a certain extent, the channel region is cut off, and the current cannot pass through, thus reaching the cut-off state; that is, by adjusting the gate voltage, the expansion degree of the reverse depletion layer can be controlled, and then the charge density and current size in the channel can be controlled to achieve current control of the MOS device. By injecting a high concentration of phosphorus elements to form a high-doped diffusion layer 2 15 region with a concentration similar to that of the N-well layer, after the conduction charge is formed, the conduction charge can directly conduct two similar N-body regions. This design can effectively reduce the on-resistance of the MOS device.

[0031] In this embodiment, the diffusion layer includes a highly doped diffusion layer 17, a low doped diffusion layer 13, a low doped diffusion layer 2 14 and a highly doped diffusion layer 2 15. The highly doped diffusion layer 2 15 is in contact with the low doped P well layer 2 12, and the doping concentration of the highly doped diffusion layer 2 15 is the same as the doping concentration of the highly doped N well layer 10. The doping concentration of the highly doped diffusion layer 2 15 is higher than the doping concentration of the highly doped diffusion layer 17; the doping concentration of the low doped diffusion layer 2 14 is higher than the doping concentration of the highly doped diffusion layer 2 15.

[0032] In this embodiment, the highly doped P-well layer 1 8 and the highly doped P-well layer 2 9 between adjacent MOS cells are integrated. In this way, the P-well layer can be divided into more levels according to different doping concentrations. The multi-level design can suppress the intervention of the gate electric field on the internal charge and avoid excessive parasitic charges in the P-well layer.

[0033] In this embodiment, only the highly doped P well layer 2 9 in the P well layer is in ohmic contact with the metal source 4, the doping concentration of the highly doped P well layer 2 9 is higher than the doping concentration of the highly doped P well layer 1 8, the doping concentration of the low doped P well layer 2 12 is higher than the doping concentration of the low doped P well layer 1 11, the highly doped P body region 3 is in contact with the substrate layer 2, and the highly doped P body region 3 is located between the drain 1 and the gate 6.

[0034] In this embodiment, a gate oxide layer 5 is deposited between the surface of the gate 6 and the semiconductor epitaxial layer and the metal source 4. The gate oxide layer 5 is an insulating material that can isolate the gate 6 from the semiconductor epitaxial layer to prevent current leakage and mutual interference. It can effectively prevent electron penetration and leakage and maintain the stability of the circuit.

[0035] Of course, the above description is not a limitation of the present invention, and the present invention is not limited to the above examples. Changes, modifications, additions or substitutions made by ordinary technicians in this technical field within the essential scope of the present invention also fall within the protection scope of the present invention.

Claims

1. A super junction MOS semiconductor device, characterized in that: A MOS semiconductor is comprised of a plurality of MOS cells, wherein the MOS cells include a drain (1), a semiconductor epitaxial layer, a metal source (4) and a gate (6); The semiconductor epitaxial layer comprises a substrate layer (2), a diffusion layer, a P-well layer, a highly doped N-well layer (10) and a highly doped P-body region (3); The P-well layer comprises a highly doped P-well layer 1 (8), a highly doped P-well layer 2 (9), a low doped P-well layer 1 (11) and a low doped P-well layer 2 (12); When the voltage of the gate (6) is zero, free carriers exist in the charge channel formed in the low-doped P-well layer 2 (12) and a conductive path is formed; and when the gate (6) applies a gate voltage, a reverse depletion layer is formed between the gate (6) and the substrate layer (2) and the charge density of the charge channel is reduced.

2. The super junction MOS semiconductor device according to claim 1, characterized in that: The diffusion layer comprises a high-doped diffusion layer 1 (7), a low-doped diffusion layer 1 (13), a low-doped diffusion layer 2 (14) and a high-doped diffusion layer 2 (15).

3. The super junction MOS semiconductor device according to claim 2, characterized in that: The second highly doped diffusion layer (15) is in contact with the second low doped P well layer (12), and the doping concentration of the second highly doped diffusion layer (15) is the same as the doping concentration of the highly doped N well layer (10).

4. The super junction MOS semiconductor device according to claim 3, characterized in that: The doping concentration of the highly doped diffusion layer 2 (15) is higher than the doping concentration of the highly doped diffusion layer 1 (7); the doping concentration of the low doped diffusion layer 2 (14) is higher than the doping concentration of the highly doped diffusion layer 2 (15).

5. The super junction MOS semiconductor device according to claim 1, characterized in that: The high-doped P-well layer 1 (8) and the high-doped P-well layer 2 (9) between adjacent MOS cells are integrated as one.

6. The super junction MOS semiconductor device according to claim 1, characterized in that: In the P-well layer, only the highly doped P-well layer 2 (9) is in ohmic contact with the metal source electrode (4).

7. The super junction MOS semiconductor device according to claim 1, characterized in that: The doping concentration of the highly doped P-well layer 2 (9) is higher than that of the highly doped P-well layer 1 (8), and the doping concentration of the low doped P-well layer 2 (12) is higher than that of the low doped P-well layer 1 (11).

8. The super junction MOS semiconductor device according to claim 1, characterized in that: The highly doped P body region (3) is in contact with the substrate layer (2), and the highly doped P body region (3) is located between the drain (1) and the gate (6).

9. The super junction MOS semiconductor device according to claim 1, characterized in that: A gate oxide layer (5) is deposited between the surface of the gate (6), the semiconductor epitaxial layer and the metal source (4).

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