Semiconductor Die

Abstract

Some embodiments of the present disclosure provide a plurality of semiconductor dies. A semiconductor die includes a plurality of first semiconductor devices having a gate length of 3 nanometers and a plurality of first metal gates, wherein more than 99% of the first semiconductor devices having a gate length of 3 nanometers have a gate height ranging from 10 nanometers to 14 nanometers.

Description

Technical Field

[0001] Some embodiments of the present disclosure provide a semiconductor die. Background Art

[0002] Semiconductor devices are used in a variety of electronic applications, such as personal computers, cell phones, digital cameras, and other electronic equipment. Semiconductor devices are typically manufactured by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor material layers over a semiconductor substrate; and using lithography to pattern the various material layers to form circuit components and elements thereon.

[0003] The semiconductor industry continues to reduce minimum feature sizes to continue to improve the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.), which allows more components to be integrated into a given area. However, as minimum feature sizes shrink, additional problems arise to be solved. Utility Model Content

[0004] Some embodiments of the present disclosure provide a semiconductor die comprising a plurality of first semiconductor devices having a gate length of 3 nanometers and a plurality of first metal gates, wherein more than 99% of the first semiconductor devices having a gate length of 3 nanometers have a gate height ranging from 10 nanometers to 14 nanometers.

[0005] Some embodiments of the present disclosure provide a semiconductor die, including a plurality of first semiconductor devices, a plurality of second semiconductor devices, a plurality of third semiconductor devices, and a plurality of fourth semiconductor devices. The plurality of first semiconductor devices have a gate length of 3 nanometers. The plurality of second semiconductor devices have a gate length of 9 nanometers. The plurality of third semiconductor devices have a gate length of 55 nanometers. The plurality of fourth semiconductor devices have a gate length of 135 nanometers. The maximum gate height difference between these first semiconductor devices and these second semiconductor devices is 11.2 nanometers. The maximum gate height difference between these first semiconductor devices and these third semiconductor devices is 15.4 nanometers. The maximum gate height difference between these first semiconductor devices and these fourth semiconductor devices is 14.3 nanometers. The maximum gate height difference between these second semiconductor devices and these third semiconductor devices is 13.5 nanometers. The maximum gate height difference between these second semiconductor devices and these fourth semiconductor devices is 12.4 nanometers. The maximum gate height difference between these third semiconductor devices and these fourth semiconductor devices is 9.4 nanometers.

[0006] Some embodiments of the present disclosure provide a semiconductor die including a plurality of first semiconductor devices, a plurality of second semiconductor devices, a plurality of third semiconductor devices, and a plurality of fourth semiconductor devices. The first semiconductor device has a gate length of 3 nanometers, a minimum gate height of 6.2 nanometers, and a maximum gate height of 18.4 nanometers. The second semiconductor device has a gate length of 9 nanometers, a minimum gate height of 8.1 nanometers, and a maximum gate height of 17.4 nanometers. The third semiconductor device has a gate length of 55 nanometers, a minimum gate height of 11.1 nanometers, and a maximum gate height of 21.6 nanometers. The fourth semiconductor device has a gate length of 135 nanometers, a minimum gate height of 13.1 nanometers, and a maximum gate height of 20.5 nanometers. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Some aspects of the present disclosure are described in the accompanying Figure 1 The following detailed description is best understood when read together. It should be noted that, in accordance with standard industry practice, various features may not be drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

[0008] Figure 1 illustrates a top view of a device, such as a gate-all-around (GAA) semiconductor device, according to some embodiments;

[0009] FIG. 2A to FIG. 2B A cross-sectional view illustrating forming a multi-layer structure and forming fins in the multi-layer structure according to some embodiments;

[0010] FIG. 3A to FIG. 3B illustrates a cross-sectional view of forming a dummy gate stack over a fin according to some embodiments;

[0011] FIG. 4A to FIG. 4C illustrates a cross-sectional view of forming openings and internal spacers in a multi-layer structure according to some embodiments;

[0012] FIG. 5A to FIG. 5C illustrates a cross-sectional view of forming bottom spacers and source / drain regions according to some embodiments;

[0013] FIG. 6A to FIG. 6B A cross-sectional view illustrating a process of forming an inter-layer dielectric (ILD) layer and planarization according to some embodiments;

[0014] 7A to 7C A cross-sectional view illustrating removal of a dummy gate stack, performing a wire release process, and forming a gate dielectric according to some embodiments;

[0015] FIG. 8A to FIG. 8Billustrates a cross-sectional view of forming a gate electrode and a gate cap according to some embodiments;

[0016] FIG. 9A to FIG. 9B A cross-sectional view illustrating the formation of an opening in a metal gate cutting process according to some embodiments;

[0017] FIG. 10A to FIG. 10B illustrates a cross-sectional view of forming a cut metal gate dielectric plug according to some embodiments;

[0018] FIG. 11A to FIG. 11B A cross-sectional view illustrating the formation of an opening in an intermediate step in forming a continuous poly on diffusion edge (CPODE) structure according to some embodiments;

[0019] FIG. 12A to FIG. 12B illustrates a cross-sectional view of an extended opening in other intermediate steps in forming a CPODE structure according to some embodiments;

[0020] FIG. 13A to FIG. 13B A cross-sectional view illustrating a CPODE structure formed in a GAA semiconductor device according to some embodiments;

[0021] Fig.14 and Fig.15 A cross-sectional view illustrating gate height of a metal gate according to some embodiments;

[0022] Fig.16 The diagram shows a semiconductor die and a device formed on the semiconductor die.

[0023]

Explanation of symbols

[0024] 100: All-around gate semiconductor device

[0025] 103: Multilayer structure

[0026] 105: Fins

[0027] 107: Gate electrode

[0028] 109: Cutting metal gate structure

[0029] 111: Continuous polysilicon structure on diffusion edge

[0030] 201: Substrate / Semiconductor Substrate

[0031] 203: Multi-layer stacking

[0032] 205: First layer / first material layer

[0033] 207: layer / second layer / second material layer / semiconductor layer

[0034] 209: Quarantine

[0035] 211: Dummy gate dielectric

[0036] 301: dummy gate stack

[0037] 303: dummy gate electrode

[0038] 305: First hard mask

[0039] 307: Second hard mask

[0040] 309: Top spacer

[0041] 401: First Opening

[0042] 403: Internal spacer

[0043] 405: Segment

[0044] 501: Bottom spacer

[0045] 503: Source / drain region

[0046] 505: Segment

[0047] 507: spacer interface

[0048] 601: contact etching stop layer

[0049] 603: interlayer dielectric layer

[0050] 701:Nanosheets / Nanostructures

[0051] 703: Gate dielectric

[0052] 705: Segment

[0053] 801: Gate cap

[0054] 806:lower surface

[0055] 807: Gate

[0056] 808:Top surface

[0057] 901: Second opening

[0058] 903: shielding layer

[0059] 1003: The third opening

[0060] 1600:Semiconductor grain / grain

[0061] 1601: Grain area

[0062] 1602: Grain area

[0063] 1603: Grain area

[0064] 1604: Grain area

[0065] 1605: corner

[0066] CL1: Channel length

[0067] CW1: Channel Width

[0068] D1: First Depth

[0069] D2: Second Depth

[0070] H1: First Height

[0071] H2: Second Height

[0072] H3: The third height

[0073] H4: The fourth height

[0074] H5: The fifth height

[0075] H6: Sixth Height

[0076] H7: Seventh Height

[0077] H8: The eighth height

[0078] H9: The ninth height

[0079] H14: Gate height

[0080] L1: First length

[0081] L5: Fifth length

[0082] S1: First spacing

[0083] Th1: First thickness

[0084] Th2: Second thickness

[0085] Th3: The third thickness

[0086] W1: First width

[0087] W2: Second width

[0088] W3: Third width

[0089] W4: Fourth width

[0090] W5: Fifth width DETAILED DESCRIPTION

[0091] The following disclosure provides many different embodiments or examples for implementing the different features of the provided subject matter. Specific examples of components and configurations are described below to simplify some implementations of the present disclosure. Of course, these components and configurations are only examples and are not intended to be limiting.

[0092] For the sake of brevity, known techniques for the manufacture of semiconductor devices may not be described in detail herein. In addition, the various tasks and processes described herein may be incorporated into more complex procedures or processes having additional functionality that is not described in detail herein. In particular, the various processes in the manufacture of semiconductor devices are well known, and therefore, for the sake of brevity, many processes will be briefly mentioned herein, or will be omitted entirely without providing well-known process details. As will be readily apparent to those skilled in the art, after a complete reading of some embodiments of the present disclosure, the structures disclosed herein may be used by a variety of techniques and may be incorporated into a variety of semiconductor devices and products. In addition, it should be noted that the semiconductor device structure includes a varying number of components, and a single component depicted in the accompanying drawings may represent multiple components.

[0093] In addition, spatially relative terms, such as "above," "overlying," "on," "upper," "top," "below," "underlying," "below," "lower," "bottom," and the like, may be used herein for ease of description to describe the relationship of one element or feature to another or other elements or features as illustrated in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation other than the orientation depicted in the figures. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein may likewise be interpreted accordingly. When spatially relative terms, such as those listed above, are used to describe a first element with respect to a second element, the first element may be directly on the other element, or there may be intervening elements or layers. When an element or layer is referred to as being "on" another element or layer, the element or layer is directly on and in contact with the other element or layer.

[0094] In addition, some embodiments of the present disclosure may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not in itself indicate the relationship between the various embodiments and / or configurations discussed.

[0095] In semiconductor manufacturing, the topology of a device after chemical-mechanical planarization (CMP) is a key factor for determining integrated circuit performance and for determining manufacturing difficulties. Topological requirements may depend on layers (i.e., oxide diffusion (OD), polysilicon (PO), CPODE, cut-metal-gate (CMG), and the like), layout (static random-access memory (SRAM), reverse osmosis (RO), breakdown voltage (VBD), and the like), overlay marks, and other factors. Described herein is a method for fabricating a semiconductor device with improved topology.

[0096] As described herein, lower gate heights generally result in better integrated circuit performance, i.e., lower capacitance. However, lower gate heights can make manufacturing more difficult. Specifically, CMP processes can tend to over-polish. Herein, devices with various gate heights are distributed across semiconductor die to improve device performance and device reliability.

[0097] Figure 1 FIG. 1 is a top view of an intermediate structure in forming a gate-all-around (GAA) semiconductor device 100 according to some embodiments. Specifically, Figure 1 The multilayer structure 103 is shown, and the multilayer structure 103 includes a plurality of nanosheets (shown in the following figures) formed on a semiconductor substrate 201 , a fin 105 formed in the multilayer structure 103 , and a plurality of gate electrodes 107 above the fin 105 . Figure 1 Further illustrated are a plurality of cut metal gate structures 109 separating two of the gate electrodes 107 , one of the fins 105 dividing the two cut metal gate structures 109 , and a continuous poly on diffusion edge (CPODE) structure 111 intersecting the cut metal gate structures 109 .

[0098] Although the two fins 105 are shown Figure 1 In the following figures, it should be understood that, depending on the design and the number of GAA semiconductor devices 100, any suitable number of fins 105 can be formed in the multilayer structure 103 to form the desired GAA semiconductor device 100. In addition, any suitable number of gate electrodes 107, CPODE structures 111, and cut metal gate structures 109 are formed to form the desired GAA semiconductor device 100.

[0099] Figure 1 Further illustrated are a first section line (section in the X direction) and a second section line (section in the Y direction) taken through the intermediate structure. The first section line (section in the X direction) is taken through the length of the fin 105 divided into two and through the CPODE structure 111. The second section line (section in the Y direction) is obtained through the length of one of the gate electrodes 107 separated by the two cut metal gate structures 109, through the two cut metal gate structures 109, and through the CPODE structure 111 intersecting the two cut metal gate structures 109.

[0100] FIG. 2A to FIG. 2B The diagram shows a cross-sectional view of forming a multilayer structure 103 and forming a fin 105 in the multilayer structure 103 in an intermediate step of forming a GAA semiconductor device 100 according to some embodiments. Figure 1 A substrate 201 is shown in which dopants may be implanted to form wells. In an embodiment, the substrate 201 is a semiconductor substrate, such as a silicon substrate, a silicon germanium substrate, a germanium substrate, a III-V material substrate (e.g., GaAs, GaP, GaAsP, AlInAs, AlGaAs, GaInAs, InAs, GaInP, InP, InSb and / or GaInAsP; or a combination thereof), or a substrate formed of other semiconductor materials having, for example, high band-to-band tunneling (BTBT). The substrate 201 may be doped or undoped. In some embodiments, the substrate 201 may be a bulk semiconductor substrate, such as a bulk silicon substrate of a wafer, a semiconductor-on-insulator (SOI) substrate, a multilayer or gradient substrate, or the like.

[0101] FIG. 2A to FIG. 2B The following further illustrates a deposition process for forming the multilayer structure 103 in an intermediate stage of manufacturing the GAA semiconductor device 100 according to some embodiments. Figure 2A A series of depositions are shown which are performed to form a multilayer stack 203 of alternating first material layers 205 and second material layers 207 over a substrate 201 .

[0102] According to some embodiments, the first layer 205 may be formed using a first semiconductor material having a first lattice constant, such as SiGe, Ge, Si, GaAs, InSb, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, combinations of these materials, or the like. In some embodiments, the first layer 205 of the first semiconductor material (e.g., SiGe) is epitaxially grown on the substrate 201 using a deposition technique such as epitaxial growth, vapor-phase epitaxy (VPE), molecular beam epitaxy (MBE), although other deposition processes may also be used, such as chemical vapor deposition (CVD), low pressure CVD (LPCVD), atomic layer CVD (ALCVD), ultrahigh vacuum CVD (UHCVD), reduced pressure CVD (RPCVD), combinations thereof, or the like. In some embodiments, the first layer 205 is formed to a first thickness Th1 between 3 nanometers (nm) and about 10 nm. However, any suitable thickness may be utilized while remaining within the scope of the embodiments.

[0103] Once the first layer 205 has been formed over the substrate 201, the second layer 207 can be formed over the first layer 205. According to some embodiments, the second layer 207 can be formed using a second semiconductor material having a second lattice constant different from the first lattice constant of the first layer 205, such as Si, SiGe, Ge, GaAs, InSb, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, combinations of these materials, or the like. In a specific embodiment where the first layer 205 is silicon germanium, the second layer 207 is a material such as silicon. However, any suitable combination of materials can be used for the first layer 205 and the second layer 207.

[0104] In some embodiments, the second layer 207 is epitaxially grown on the first layer 205 using a deposition technique similar to the deposition technique used to form the first layer 205. However, the second layer 207 may use any of the deposition techniques suitable for forming the first layer 205 as described above or any other suitable technique. According to some embodiments, the second layer 207 is formed to a thickness similar to the first layer 205. However, the second layer 207 may also be formed to a thickness different from the first layer 205. According to some embodiments, the second layer 207 may be formed to a second thickness Th2 between 5 nm and about 15 nm. However, any suitable thickness may be used.

[0105] Once the second layer 207 is formed over the first layer 205, the deposition process is repeated to form the remaining layers of material in a series of alternating materials of the first layer 205 and the second layer 207 until the desired top-most layer of the multilayer stack 203 is formed. According to embodiments of the present disclosure, the first layer 205 may be formed to the same or similar first thickness, and the second layer 207 may be formed to the same or similar second thickness. However, the first layers 205 may have different thicknesses from one another, and / or the second layers 207 may have different thicknesses from one another, and any combination of thicknesses may be used for the first layer 205 and the second layer 207. According to embodiments of the present disclosure, the top-most layer of the multilayer stack 203 is formed as the second layer 207; however, in other embodiments, the top-most layer of the multilayer stack 203 may be formed as the first layer 205. Additionally, although embodiments are disclosed herein as including three first layers 205 and three second layers 207, the multilayer stack 203 may have any suitable number of layers (e.g., nanosheets). For example, the multilayer stack 203 may include a plurality of sheets in the range of 2 to 10 sheets. In some embodiments, the multilayer stack 203 may include a number of first layers 205 equal to the number of second layers 207; however, in other embodiments, the number of first layers 205 may be different from the number of second layers 207. According to some embodiments, the multilayer stack 203 may be formed to a first height H1 between about 12 nm and about 100 nm. However, any suitable height may be used.

[0106] FIG. 2A to FIG. 2B Further illustrated is a patterning process of the multilayer structure 103 and the formation of isolation regions 209 in an intermediate stage of manufacturing the GAA semiconductor device 100 according to some embodiments. The patterning process is used to form fins 105 in the multilayer structure 103 and to form trenches between the fins 105 in preparation for forming the isolation regions 209. According to some embodiments, the patterning process for forming the fins 105 includes applying a photoresist on the multilayer stack 203, and then patterning and developing the photoresist to form a mask over the multilayer stack 203. Once formed, the mask is then used during an etching process, such as an anisotropic etching process, to transfer the pattern of the mask into the underlying layers to pass through the multilayer stack 203, and trenches are formed in the substrate 201 to define the fins 105, wherein the fins 105 are separated by the trenches.

[0107] Additionally, while a single mask process has been described, this is intended to be illustrative and not limiting, as the gate all around (GAA) device structure may be patterned by any suitable method. For example, the structure may be patterned using one or more photolithography processes, including double patterning or multiple patterning processes. In general, the double patterning or multiple patterning processes combine photolithography and self-alignment processes, thereby allowing patterns to be produced that have, for example, a pitch that is smaller than that otherwise obtained using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed along the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers may then be used to pattern the GAA structure.

[0108] In an embodiment, the isolation region 209 is formed as a shallow trench isolation region by depositing a dielectric material in the trench. According to some embodiments, the dielectric material used to form the isolation region 209 may be a material such as an oxide material (e.g., a flowing oxide), a high-density plasma (HDP) oxide, or the like. The dielectric material may be formed using a chemical vapor deposition (CVD) method (e.g., a HARP process), a high-density plasma CVD method, or other suitable formation method after optional cleaning and lining of the trench to fill or overfill the area around the fin 105. In some embodiments, a post-placement annealing process (e.g., oxide densification) is performed to densify the material of the isolation region 209 and reduce its wet etch rate. Chemical mechanical polishing (CMP), etching, a combination of these operations, or the like may be performed to remove any excess material of the isolation region 209.

[0109] Once the dielectric material has been deposited to fill or overfill the area around the fin 105, the dielectric material may then be recessed away from the surface of the fin 105 to form the isolation region 209. The recessing operation may be performed to expose at least a portion of the sidewalls of the fin 105 adjacent to the top surface of the fin 105. The dielectric material may be recessed using wet etching by immersing the top surface of the fin 105 in an etchant that is selective to the material of the dielectric material, although other methods such as reactive ion etching, dry etching, chemical oxide removal, or dry chemical cleaning may be used.

[0110] FIG. 2A to FIG. 2BFurther illustrated is the formation of a dummy gate dielectric 211 over the exposed portion of the fin 105. Once the isolation region 209 has been formed, the dummy gate dielectric 211 may be formed by thermal oxidation, chemical vapor deposition, sputtering, or any other method known and used in the prior art for forming gate dielectrics. Depending on the technique of gate dielectric formation, the thickness of the dummy gate dielectric 211 on the top may be different than the thickness of the dummy dielectric on the sidewalls. In some embodiments, the dummy gate dielectric 211 may be formed by depositing a material such as silicon and then oxidizing or nitriding the silicon layer to form a dielectric such as silicon dioxide or silicon oxynitride. In such embodiments, the dummy gate dielectric 211 may be formed to a thickness in the range of about to about Such as In other embodiments, the dummy gate dielectric 211 may also be made of a high dielectric constant (high-k) material, such as lanthanum oxide (La 2 O 3 ), aluminum oxide (Al 2 O 3 ), hafnium oxide (HfO 2 ), hafnium oxynitride (HfON) or zirconium oxide (ZrO 2 ) or a combination thereof, wherein the equivalent oxide thickness is between about About Between, such as about In addition, any combination of silicon dioxide, silicon oxynitride and / or high-k materials may also be used for the dummy gate dielectric 211 .

[0111] See FIG. 3A to FIG. 3B , these figures illustrate forming a dummy gate stack 301 over the fin 105 according to some embodiments. According to some embodiments, the dummy gate stack 301 includes a dummy gate dielectric 211, a dummy gate electrode 303 over the dummy gate dielectric 211, a first hard mask 305 over the dummy gate electrode 303, and a second hard mask 307 over the first hard mask 305.

[0112] In some embodiments, the dummy gate electrode 303 includes a conductive material and can be selected from the group consisting of polysilicon, W, Al, Cu, AlCu, W, Ti, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, TiN, Ta, TaN, Co, Ni, combinations of these materials, or the like. The dummy gate electrode 303 can be deposited by chemical vapor deposition (CVD), sputtering deposition, or other techniques known and used in the art for depositing conductive materials. The thickness of the dummy gate electrode 303 can be about 1000 Å. to about The top surface of the dummy gate electrode 303 may have a non-planar top surface and be planarized before patterning the dummy gate electrode 303 or gate etching. Ions may or may not be introduced into the dummy gate electrode 303 at this point. The ions may be introduced, for example, by ion implantation techniques.

[0113] Once the dummy gate electrode 303 has been formed, the dummy gate dielectric 211 and the dummy gate electrode 303 may be patterned. In an embodiment, the patterning may be performed by initially forming a first hard mask 305 over the dummy gate electrode 303 and forming a second hard mask 307 over the first hard mask 305 .

[0114] According to some embodiments, the first hard mask 305 includes a dielectric material such as silicon nitride (SiN), oxide (OX), silicon oxide (SiO), titanium nitride (TiN), silicon nitride oxide (SiON), combinations thereof, or the like. The first hard mask 305 can be formed using a process such as chemical vapor deposition, plasma enhanced chemical vapor deposition, atomic layer deposition, or the like. However, any other suitable materials and formation methods can be utilized. The first hard mask 305 can be formed to a thickness between about About Between, such as about Thickness.

[0115] The second hard mask 307 includes a dielectric material that is separate from the first hard mask 305. The second hard mask 307 may include any of the materials and use any of the processes suitable for forming the first hard mask 305, and may be formed to the same or similar thickness as the first hard mask 305. In embodiments where the first hard mask 305 includes silicon nitride (SiN), the second hard mask 307 may be, for example, oxide (OX). However, any suitable dielectric material, process, and thickness may be used to form the second hard mask.

[0116] Once the first hard mask 305 and the second hard mask 307 have been formed, the first hard mask 305 and the second hard mask 307 may be patterned. In an embodiment, the first hard mask 305 and the second hard mask 307 may be patterned by initially placing a photoresist (not shown individually) over the first hard mask 305 and the second hard mask 307 and exposing the photoresist to a patterned energy source (e.g., light) to initiate a chemical reaction that modifies the physical properties of the exposed portions of the first photoresist. The first photoresist may then be developed by applying a first developer (also not shown individually) to utilize the modified physical properties between the exposed and unexposed areas to selectively remove the exposed or unexposed areas.

[0117] Once the photoresist has been patterned, the photoresist may be used as a mask to pattern the underlying first hard mask 305 and the second hard mask 307. In an embodiment, the first hard mask 305 and the second hard mask 307 may be patterned using, for example, one or more reactive ion etching (RIE) processes with the photoresist as a mask. The patterning process may continue until the dummy gate electrode 303 is exposed under the first hard mask 305.

[0118] Once the first hard mask 305 and the second hard mask 307 have been patterned, the photoresist may be removed using, for example, an ashing process, whereby the temperature of the photoresist is elevated until the photoresist undergoes thermal decomposition and can be readily removed using one or more cleaning processes. However, any other suitable removal process may be used.

[0119] Once the first hard mask 305 and the second hard mask 307 have been patterned, the dummy gate electrode 303 and the dummy gate dielectric 211 may be patterned to form a series of dummy gate stacks 301. In an embodiment, the dummy gate electrode 303 and the dummy gate dielectric 211 are patterned using an anisotropic etching process, such as reactive ion etching, although any suitable process may be utilized.

[0120] FIG. 3A to FIG. 3B The formation of top spacer 309 is further illustrated. According to an embodiment, the spacer material is formed by blanket deposition over dummy gate stack 301 and multilayer structure 103. Thus, the spacer material is deposited over the top surface and sidewalls of dummy gate stack 301, the top surface and sidewalls of fin 105, and the top surface of isolation region 209. According to some embodiments, the spacer material comprises a dielectric material and is formed using a method such as chemical vapor deposition (CVD), plasma enhanced CVD, sputtering, thermal oxidation, and any other suitable method. According to some embodiments, the spacer material comprises a dielectric material such as silicon oxide (SiO 2 ), silicon oxynitride (SiON), silicon nitride (Si 3 N 4 ), silicon oxycarbide (SiOC), silicon oxycarbonitride (SiOCN), although any suitable material may be utilized, such as a low-k material having a k value less than about 4.0, combinations thereof, or the like.

[0121] Once formed, the spacer material may be etched to shape the top spacers 309 on the dummy gate stack 301 and the fins 105 to expose the tops of the dummy gate stack 301 and the fins 105. According to some embodiments, the spacer material may be etched using an anisotropic etching process (e.g., a dry etching process) such as a reactive ion etching (RIE) process, an isotropic etching process (e.g., a wet etching process), a combination thereof, or the like. In some embodiments, the spacer material formed above the fins 105 in the source / drain regions is recessed during the etching process and / or during subsequent etching processes such that portions of the sidewalls of the fins 105 in those source / drain regions are exposed.

[0122] However, while the embodiments are described using a single spacer material, this is intended to be illustrative and not limiting. Rather, any number of spacer materials and any combination of deposition and removal processes may be used, and all such processes are fully intended to be included within the scope of the embodiments.

[0123] FIG. 4A to FIG. 4C A cross-sectional view of forming a first opening 401 and inner spacers 403 in the fin 105 is shown in accordance with some embodiments. During the formation of the top spacer 309, the multilayer stack 203 will be re-exposed by removing the spacer material used for the top spacer 309. Once exposed, an etching process to remove material from the multilayer stack 203 and the substrate may be performed to form a first opening 401 (e.g., a trench, recess, channel, or the like) extending through the multilayer stack 203 and into the semiconductor substrate 201 to prepare for the formation of source / drain regions therein. In embodiments, the etching may be performed using one or more anisotropic etches, such as reactive ion etching, although any suitable process may be utilized.

[0124] In an embodiment, the first opening 401 may be formed to have a first width W1 between 10 nm and about 40 nm, such as about 20 nm. Additionally, the first opening 401 may be formed to extend into the substrate 201 to a first depth D1 between 3 nm and about 40 nm, such as about 10 nm. However, any suitable dimensions may be utilized.

[0125] FIG. 4A to FIG. 4C The formation of the inner spacer 403 in the first layer 205 is further illustrated. In detail, Figure 4C An enlarged view of section 405 is shown, with section 405 emphasized by a dashed line. Figure 4A, and reference may be made to the following discussion regarding the formation of the inner spacer 403. In some embodiments, the inner spacer 403 is formed by patterning the recess using wet etching, which employs an etchant that is more selective for the material of the first layer 205 (e.g., silicon germanium (SiGe)) than for the material of the second layer 207 (e.g., silicon (Si)) or the material of the substrate 201 (e.g., silicon (Si)). For example, in an embodiment where the first layer 205 is silicon germanium and the second layer 207 is silicon, the wet etching process may use an etchant such as hydrofluoric acid (HCl).

[0126] In an embodiment, the wet etching process may be an immersion process, a spray coating process, a spin coating process, or the like, and may be performed using any suitable process temperature (e.g., between about 400° C. and about 600° C.) and any suitable process time (e.g., between about 100 seconds and about 1000 seconds, such as 300 seconds). However, any suitable process conditions and parameters may be utilized. The etching process may be continued such that a recess having a faceted confined surface is formed in each of the first layers 205 to any desired distance from the sidewalls of the first opening 401.

[0127] In addition, the selectivity of the etchant may be selected. According to some embodiments, the etching process may also be performed to remove portions of the second layer 207 and the substrate 201 such that the size of the recess extends vertically in the direction of the sidewalls of the first opening 401 to any suitable height (described further below).

[0128] However, a wet etching process is not the only process that may be used to recess the first layer 205. For example, in another embodiment, the recessing of the first layer 205 may be performed by an isotropic dry etching process or a combination of a dry etching process and a wet etching process. Any suitable process for recessing the first layer 205 may be utilized, and all such processes are fully intended to be included within the scope of the embodiments.

[0129] Once the recesses are formed in each of the first layers 205, a spacer material is formed over the multilayer structure 103. In some embodiments, the spacer material may be different from the material of the top spacer 309 and may be a dielectric material including silicon, such as silicon nitride (SiN), silicon oxide (SiO 2 ), silicon oxynitride (SiON), silicon oxycarbonitride (SiOCN), silicon carbonitride (SiCN), silicon oxycarbide (SiOC), although any suitable material, such as a low-k material having a k value of less than about 4.0 or even an air gap, or a combination thereof, may be utilized. The spacer material may be deposited to a thickness of between about 2 nm and about 10 nm, such as about 5 nm, using a deposition process such as chemical vapor deposition, physical vapor deposition, or atomic layer deposition. However, any suitable thickness or deposition process may be utilized.

[0130] By depositing the spacer material over the multi-layer structure 103, the spacer material will line the sidewalls of the first opening 401 and will also fill in the recesses in the first layer 205. Once the recesses have been filled with the spacer material, a removal process is then performed to remove any excess spacer material from the first opening 401 while leaving the inner spacers 403. In one embodiment, the removal of the excess spacer material may be performed using an etching process such as, for example, an anisotropic dry etching process (such as a reactive ion etching process). However, any suitable etching process may be utilized that removes excess spacer material from the first opening 401 while leaving the inner spacers 403.

[0131] By filling the recess with spacer material and removing excess spacer material from the first opening 401, the inner spacer 403 will be in the shape of the recess. In addition, although the embodiment of forming the inner spacer 403 to the face shape is described, this situation is intended to be illustrative and not intended to be restrictive. Specifically, any suitable shape of the inner spacer 403 such as a concave shape or a convex shape or even a concave shape can be utilized. All such shapes are fully intended to be included in the scope of the embodiment. According to some embodiments, the inner spacer 403 can be formed to a second width W2 between about 2nm and about 10nm, such as about 5nm, and a second height H2 between about 5nm and about 20nm, such as about 10nm. In addition, the inner spacer 403 can be separated by a first spacing S1 between about 3nm and about 10nm, such as about 5nm. However, any suitable width, height and distance can be utilized.

[0132] Figure 4C The relative dimensions between the first layer 205, the second layer 207, and the inner spacer 403 are further illustrated. According to some embodiments, the second height H2 of the inner spacer 403 is greater than the height (e.g., the first thickness Th1) of the first layer 205. In some embodiments, the first spacing S1 between the inner spacers 403 is less than the second thickness Th2 of the second layer 207. However, any suitable dimensions may be utilized.

[0133] FIG. 5A to FIG. 5C The diagram shows a cross-sectional view of forming a bottom spacer 501 and a source / drain region 503 according to some embodiments. Figure 5C The dashed line shows Figure 5A Magnified view of section 505 highlighted in FIG.

[0134] Once the inner spacers 403 have been formed, the bottom spacers 501 are formed at the bottom of the first openings 401 using a semiconductor material, such as silicon germanium (SiGe), although other suitable materials may be utilized, such as those suitable for forming the first layer 205. According to some embodiments, the bottom spacers 501 are formed using SiGe and epitaxially grown at the bottom of the first openings 401 using a deposition technique such as epitaxial growth, vapor-phase epitaxy (VPE), molecular beam epitaxy (MBE). However, any other deposition process suitable for forming the first layer 205 may also be used.

[0135] Once deposited, an oxidation process may be performed to increase the density and / or dielectric constant of the bottom spacer 501. Thus, the bottom spacer 501 may be formed as silicon germanium oxide (eg, SiGeO x , SiGeON, SiGeOCN or the like). After the oxidation process, an etching process (e.g., wet etching) may be performed to remove any oxide formed along the sidewalls of the first opening 401 and / or to recess the bottom spacer 501 to a desired height. According to some embodiments, the bottom spacer 501 is formed to a third height H3 between about 3 nm and about 30 nm, such as about 20 nm. However, any suitable height may be used.

[0136] Once the bottom spacer 501 has been formed to a desired height, a post-annealing process may be performed to remove germanium (Ge) from the material of the bottom spacer 501. According to some embodiments, the annealing process may include one or more processes (e.g., steam annealing, high temperature annealing, a combination, or the like) that may be performed in a furnace or in a rapid thermal processing (RTP) chamber. According to some embodiments, the post-annealing process includes a dry annealing at a process temperature in a range between about 500° C. and about 700° C., such as about 600° C., using, for example, nitrogen (N 2 ) for a duration of about 30 minutes to about 180 minutes, such as about 60 minutes. However, any suitable oxygen source, process temperature, and process time may be utilized. Once the post-placement annealing process is completed, the germanium has been removed and the bottom spacer 501 has been transformed into a dielectric material, such as silicon nitride (SiN), oxide (OX), silicon oxynitride (SiON), silicon oxycarbonitride (SiOCN), silicon carbonitride (SiCN), or the like.

[0137] Figure 5CFurther illustrated is a spacer interface 507 between the topmost spacer in the inner spacer 403 and the bottom spacer 501. According to some embodiments, the spacer interface 507 has a first length L1 between about 3 nm and about 15 nm, such as 5 nm. However, any suitable length may be used for the spacer interface 507.

[0138] In some other embodiments, the bottom spacer 501 may be formed by depositing a second spacer material such as SiON using a process such as chemical vapor deposition (CVD), atomic layer deposition (ALD), plasma enhanced chemical vapor deposition (PECVD), etc. However, any suitable spacer material and deposition process may be used, such as the material and process suitable for forming the top spacer 309. According to some embodiments, the second spacer material is different from the material of the top spacer 309 and the inner spacer 403, and is deposited to fill and / or overfill the first opening 401.

[0139] Once deposited, the second spacer material may be etched so as to recess the bottom spacer 501 to the desired third height H3 and expose the sidewalls of the first opening 401 above the bottom spacer 501. According to some embodiments, the second spacer material may be etched using an anisotropic etching process (e.g., a dry etching process) such as a reactive ion etching (RIE) process, an isotropic etching process (e.g., a wet etching process), a combination thereof, etc. The etchant used to recess the bottom spacer 501 is selective to the second spacer material without significantly removing the material of the top spacer 309, the second layer 207, and the inner spacer 403.

[0140] Once the bottom spacer 501 is formed, source / drain regions 503 may be formed over the bottom spacer 501. The source / drain regions 503 may be formed using a growth process, such as a selective epitaxial process with semiconductor materials suitable for the device to be formed. For example, in an embodiment where the source / drain regions 503 are used to form an N-type metal-oxide-semiconductor (NMOS) device, the source / drain regions 503 may be a semiconductor material such as silicon, silicon phosphorus, silicon carbon phosphorus, combinations of these materials, and the like.

[0141] The epitaxial growth process may use precursors such as silane, dioxysilane, germane, and the like, and may continue for a period of between about 5 minutes and about 120 minutes, such as about 30 minutes. According to some embodiments, the source / drain region 503 is formed to a fourth height H4 between about 30 nm and about 90 nm, such as 50 nm. However, any suitable height and / or suitable depth may be used.

[0142] Once the source / drain regions 503 are formed, dopants may be implanted into the source / drain regions 503 by implanting appropriate dopants to supplement the dopants in the remaining portion of the first semiconductor device region. For example, n-type dopants such as phosphorus (P), carbon (C), arsenic (As), silicon (Si), antimony (Sb), etc. and combinations thereof (e.g., SiP, SiC, SiPC, SiAs, Si, Sb, etc.) may be implanted to form a Metal-Oxide-Semiconductor Field-Effect Transistor (NMOSFET) device. These dopants may be implanted using the dummy gate stack 301 and the top spacer 309 as a mask.

[0143] In another embodiment, the dopant of the source / drain region 503 may be placed during the growth of the source / drain region 503. For example, phosphorus may be placed in situ as the source / drain region 503 is formed. Any suitable process for placing dopants in the source / drain region 503 may be utilized, and all such processes are fully intended to be included within the scope of the embodiments. In addition, an annealing process may be performed to activate the dopants in the source / drain region 503. During the annealing process, the dopants of the source / drain region 503 may diffuse laterally into the second layer 207 at the interface between the second layer 207 and the source / drain region 503. Thus, a lightly doped drain (LDD) region may be formed in the second layer 207.

[0144] FIG. 6A to FIG. 6B FIG. 1 is a cross-sectional view showing the formation of a contact etch stop layer 601 and an interlayer dielectric layer 603 according to some embodiments. FIG. 6A to FIG. 6B The diagram further illustrates the removal of the first hard mask 305 and the second hard mask 307 , and the planarization of the contact etching stop layer 601 , the interlayer dielectric layer 603 , the dummy gate electrode 303 , and the top spacer 309 .

[0145] The contact etching stop layer 601 is formed in the FIG. 5A to FIG. 5C, and an interlayer dielectric layer 603 is formed over the contact etch stop layer 601. The contact etch stop layer 601 serves as an etch stop layer in a subsequent etching process, and may include a suitable material such as silicon nitride (SiN), silicon oxynitride (SiON), silicon carbon nitride (SiCN), a combination thereof, etc., and may be formed by a suitable formation method such as chemical vapor deposition (CVD), physical vapor deposition (PVD), a combination thereof, etc.

[0146] The interlayer dielectric layer 603 may include: a material such as silicon dioxide; a low-k dielectric material (e.g., a material having a lower dielectric constant than silicon dioxide), such as silicon oxynitride, phosphosilicate glass (PSG), borosilicate glass (BSG), borosilicate glass (BPSG), undoped silicate glass (USG), fluorosilicate glass (FSG), organosilicate glass (OSG), SiO x C y , spin-on glass, spin-on polymer, silicon carbon material, compounds thereof, composites thereof, the like, or combinations thereof, although any suitable dielectric material may be used. The interlayer dielectric layer 603 may be formed using a process such as plasma enhanced chemical vapor deposition (PECVD), although other processes such as low pressure chemical vapor deposition (LPCVD) may also be used.

[0147] Once formed, the interlayer dielectric layer 603 and the contact etch stop layer 601 may be planarized using a planarization process such as chemical mechanical planarization (CMP) with the dummy gate electrode 303 and the top spacer 309. However, any suitable planarization process may be utilized. Additionally, the first hard mask 305 and the second hard mask 307 may be removed during the planarization process. According to some embodiments, one or more etching processes and / or chemical mechanical planarization (CMP) may be used to remove the first hard mask 305 and the second hard mask 307. Thus, the dummy gate electrode 303 is exposed after the first hard mask 305 is removed.

[0148] FIG. 7A to FIG. 7B A cross-sectional view showing the removal of the dummy gate electrode 303 and the dummy gate dielectric 211 is shown. FIG. 7A to FIG. 7BFurther illustrated is a wire release process for forming the nanostructure 701 from the second layer 207 according to some embodiments. FIG. 7A to FIG. 7B Further illustrated is the formation of a gate dielectric 703 over the nanostructure 701 in accordance with some embodiments.

[0149] Once exposed, the dummy gate electrode 303 may be removed so as to expose the underlying dummy gate dielectric 211. In an embodiment, the dummy gate electrode 303 is removed using, for example, one or more wet or dry etching processes that utilize a dopant that is selective to the material of the dummy gate electrode 303. However, any suitable removal process may be utilized.

[0150] Once the dummy gate dielectric 211 has been exposed, the dummy gate dielectric 211 may be removed. In an embodiment, the dummy gate dielectric 211 may be removed using, for example, a wet etching process, although any suitable etching process may be utilized.

[0151] FIG. 7A to FIG. 7B As further illustrated, once the dummy gate dielectric 211 has been removed (which also exposes the sides of the first layer 205), the first layer 205 can be removed from between the substrate 201 and from between the second layer 207 in a wire release process step. The wire release process step may also be referred to as a sheet release process step, a sheet formation process step, a nanosheet formation process step, or a wire formation process step. In an embodiment, the first layer 205 can be removed using a wet etching process that selectively removes the material of the first layer 205 (e.g., silicon germanium (SiGe)) without significantly removing the material of the substrate 201 and the material of the second layer 207 (e.g., silicon (Si)). However, any suitable removal process may be utilized.

[0152] For example, in an embodiment, an etchant such as high temperature HCl may be used to selectively remove the material of the first layer 205 (e.g., SiGe) without substantially removing the material of the substrate 201 and / or the material of the second layer 207 (e.g., Si). In addition, the wet etching process may be performed at a temperature between about 400° C. and about 600° C., such as about 560° C., and for a time between about 100 seconds and about 600 seconds, such as about 300 seconds. However, any suitable etchant, process parameters, and time may be utilized.

[0153] By removing the material of the first layer 205, the side surfaces of the second layer 207 are exposed ( FIG. 7A to FIG. 7B4 and 5). The nanostructures 701 are separated from each other by internal spacers 403. According to some embodiments, the nanostructures 701 are separated by a spacing between about 5 nm and about 15 nm, such as 10 nm. The nanostructures 701 include a channel region between opposing regions of the source / drain regions 503 and have a channel length CL1 between about 5 nm and about 180 nm, such as about 10 nm, and a channel width CW1 between about 8 nm and about 100 nm, such as about 30 nm. In an embodiment, the nanostructures 701 are formed to have a thickness that is the same as the original thickness of the second layer 207, such as between about 3 nm and about 15 nm, such as about 8 nm, although an etching process may also be used to reduce the thickness.

[0154] In some embodiments, the wire release step may include an optional step of partially removing the material of the second layer 207 (e.g., by over-etching) during the removal of the first layer 205. Therefore, the thickness of the nanostructure 701 is formed to have a reduced thickness compared to the original thickness of the second layer 207. Therefore, the nanostructure 701 may have a third thickness Th3 that is less than the thickness of the original second layer 207 (e.g., the second thickness Th2). In addition, during this partial removal, the top spacer 309, the inner spacer 403 may be removed to protect the adjacent material of the second layer 207. Therefore, the thickness of the nanostructure 701 at the distal portion of the nanostructure 701 is protected during the wire release step and is not further reduced.

[0155] In addition, although 7A to 7C Three nanostructures 701 are shown formed, but any suitable number of nanostructures 701 may be formed from the nanosheets provided in the multilayer stack 203. For example, the multilayer stack 203 may be formed to include any suitable number of first layers 205 and any suitable number of second layers 207. Thus, a multilayer stack 203 including fewer first layers 205 and fewer second layers 207 forms one or both of the nanosheets 701 after removing the first layer 205. Thus, a multilayer stack 203 including many first layers 205 and many second layers 207 forms four or more nanostructures 701 after removing the first layer 205.

[0156] FIG. 7A to FIG. 7B The formation of a gate dielectric 703 over the nanostructure 701 is further illustrated according to some embodiments. In an embodiment, the gate dielectric 703 comprises a high-k material (eg, K>=9), such as Ta, deposited via a process such as atomic layer deposition, chemical vapor deposition, etc. 2 O 5 、Al 2 O 3, Hf oxide, Ta oxide, Ti oxide, Zr oxide, Al oxide, La oxide (for example, HfO 2 , HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, LaO, ZrO, TiO), combinations of these materials, etc. In some embodiments, the gate dielectric 703 comprises a nitrogen-doped oxide dielectric that is initially formed prior to forming the metal-content high-K (e.g., K value>13) dielectric material. The gate dielectric 703 can be deposited to a thickness between about 1 nm and about 3 nm, although any suitable material and thickness can be utilized. As shown, the gate dielectric 703 encapsulates the nanostructure 701, thereby forming a channel region between the source / drain regions 503.

[0157] FIG. 8A to FIG. 8B A cross-sectional view of forming a gate electrode 107 and a gate cap 801 is shown in accordance with some embodiments. Once the gate dielectric 703 has been formed, the gate electrode 107 is formed to surround the nanostructure 701. In some embodiments, the gate electrode 107 is formed using multiple layers, each layer being sequentially deposited adjacent to each other using a highly conformal deposition process such as atomic layer deposition, although any suitable deposition process may be utilized. According to some embodiments, the gate electrode 107 may include a cap layer, a barrier layer, an n-type metal work function layer, a p-type metal work function layer, and a fill material.

[0158] A cap layer may be formed adjacent to the gate dielectric 703, although any suitable deposition process may be used, and the cap layer may be formed of a metallic material such as TaN, Ti, TiAlN, TiAl, Pt, TaC, TaCN, TaSiN, Mn, Zr, TiN, Ru, Mo, WN, other metal oxides, metal nitrides, metal silicates, transition metal oxides, transition metal nitrides, transition metal silicates, metal oxynitrides, metal aluminates, zirconium silicate, zirconium aluminate, combinations of these materials, etc. The metallic material may be deposited using a deposition process such as atomic layer deposition, chemical vapor deposition, etc.

[0159] The barrier layer may be formed adjacent to the cap layer and may be formed of a different material than the cap layer. For example, the barrier layer may be formed of a material, such as one or more layers of a metallic material, such as TiN, TaN, Ti, TiAlN, TiAl, Pt, TaC, TaCN, TaSiN, Mn, Zr, TiN, Ru, Mo, WN, other metal oxides, metal nitrides, metal silicates, transition metal oxides, transition metal nitrides, transition metal silicates, metal oxynitrides, metal aluminates, zirconium silicate, zirconium aluminate, combinations of these materials, etc., although any suitable deposition process may be used. The barrier layer may be deposited using a deposition process such as atomic layer deposition, chemical vapor deposition, etc.

[0160] The n-type metal work function layer may be formed adjacent to the barrier layer. In an embodiment, the n-type metal work function layer is a material such as W, Cu, AlCu, TiAlC, TiAlN, TiAl, Pt, Ti, TiN, Ta, TaN, Co, Ni, Ag, Al, TaAl, TaAlC, TaC, TaCN, TaSiN, Mn, Zr, other suitable n-type work function materials, or combinations thereof. For example, the first n-type work function layer may be deposited using an atomic layer deposition (ALD) process, a CVD process, etc. However, any suitable material and process may be used to form the n-type metal work function layer.

[0161] The p-type metal work function layer may be formed adjacent to the n-type metal work function layer. In an embodiment, the first p-type metal work function layer may be formed of a metal material such as W, Al, Cu, TiN, Ti, TiAlN, TiAl, Pt, Ta, TaN, Co, Ni, TaC, TaCN, TaSiN, TaSi 2 、NiSi 2 、Mn、Zr、ZrSi 2 , TaN, Ru, AlCu, Mo, MoSi 2 , WN, other metal oxides, metal nitrides, metal silicates, transition metal oxides, transition metal nitrides, transition metal silicates, metal oxynitrides, metal aluminates, zirconium silicate, zirconium aluminate, combinations of these materials, etc. In addition, the p-type metal work function layer may be deposited using a deposition process such as atomic layer deposition, chemical vapor deposition, etc., although any suitable deposition process may be used.

[0162] Once the p-type metal work function layer has been formed, a fill material is deposited to fill the remainder of the opening. In an embodiment, the fill material may be a material such as tungsten, Al, Cu, AlCu, W, Ti, TiAlN, TiAl, Pt, TaC, TaCN, TaSiN, Mn, Zr, TiN, Ta, TaN, Co, Ni, a combination of these materials, or the like, and may be formed using a deposition process such as electroplating, chemical vapor deposition, atomic layer deposition, physical vapor deposition, a combination of these processes, etc. However, any suitable material may be utilized.

[0163] Once the opening left by removing the dummy gate electrode 303 has been filled, the material of the gate electrode 107 and the gate dielectric 703 can be planarized to remove any material outside the opening left by removing the dummy gate electrode 303. In a particular embodiment, the removal can be performed using a planarization process such as chemical mechanical polishing, although any suitable planarization and removal process can be utilized. According to some embodiments, the gate electrode 107 can be formed to a fifth length L5 between about 8 nm and about 30 nm. However, any suitable length can be used.

[0164] Once formed, the gate electrode 107 may be recessed below the planarized surface of the interlayer dielectric layer 603. According to some embodiments, the gate electrode 107 may be recessed using an etching process such as wet etching, dry etching, a combination, etc. Once recessed, the height of the gate electrode 107 above the topmost structure of the nanostructure 701 is a fifth height H5. According to some embodiments, the fifth height H5 is between about 8 nm and about 30 nm. However, any suitable height may be used.

[0165] The gate cap 801 may be formed by initially depositing a dielectric material over the gate electrode 107 to fill and / or overfill the recess. In some embodiments, the gate cap 801 is formed using a dielectric material such as silicon nitride (SiN), oxide (OX), silicon oxynitride (SiON), silicon oxycarbonitride (SiOCN), silicon carbonitride (SiCN), etc. According to some embodiments, the gate cap 801 is formed using a material such as a metal oxide of zirconium (Zr), hafnium (Hf), aluminum (Al), etc. In addition, the gate cap 801 may be formed using a suitable deposition process such as chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), a combination of these processes, etc. However, any suitable material and deposition process may be utilized. Once deposited, the gate cap 801 may be planarized with the interlayer dielectric layer 603 using a planarization process such as a chemical mechanical polishing process. Once planarized, the gate cap 801 has a sixth height H6 between about 10 nm and about 30 nm. However, any suitable height may be used.

[0166] FIG. 9A to FIG. 9BA cross-sectional view of forming a second opening 901 in a cut metal gate process according to some embodiments is shown. Once the gate cap 801 has been planarized with the interlayer dielectric layer 603, a shielding layer 903 may be deposited over the planar surfaces of the gate cap 801, the interlayer dielectric layer 603, the contact etch stop layer 601, the top spacer 309, and the gate dielectric 703. Once deposited, the shielding layer 903 is patterned to expose underlying materials, including the gate cap 801 and the interlayer dielectric layer 603, in the desired portions of the cut metal gate structure 109 that are not formed.

[0167] Once patterned, the masking layer 903 is used as an etch mask to etch the underlying material to form the second opening 901 (e.g., a trench, a recess, a channel, etc.). In the etching process, the material of the gate cap 801 and the gate electrode 107 is etched using an anisotropic etching process and may stop on the top surface of the gate dielectric 703 and the top surface of the isolation region 209. The second opening 901 may be formed between adjacent ones of the fins 105 and may be formed to cut through one or more gate electrodes 107. According to some embodiments, two of the second openings 901 are formed to cut through two adjacent ones of the gate electrodes 107 and are located on opposite sides of one of the fins 105, such as Figure 1 According to some embodiments, the second opening 901 is located between the top spacers 309 of two adjacent devices. Once the second opening 901 has been formed, the masking layer 903 is removed.

[0168] FIG. 10A to FIG. 10B A cross-sectional view of forming a cut metal gate structure 109 according to some embodiments is shown. Once the second opening 901 has been formed, the cut metal gate structure 109 is formed by initially depositing a dielectric material to fill and overfill the second opening 901. According to some embodiments, the cut metal gate structure 109 is formed using any dielectric material and deposition process suitable for forming the gate cap 801. In some embodiments, the dielectric material used to form the cut metal gate structure 109 is the same as the dielectric material used to form the gate cap 801, although the dielectric material may be different. For example, in an embodiment where the gate cap 801 is formed using silicon nitride (SiN), the cut metal gate structure 109 may also be formed using silicon nitride (SiN) in a deposition process such as atomic layer deposition (ALD). However, any suitable dielectric material and deposition process may be used. According to some embodiments, the cut metal gate structure 109 is formed to a third width W3 between about 5 nm and about 50 nm, such as 10 nm. However, any suitable width may be used.

[0169] The cut metal gate structure 109 divides the two relatively long gate electrodes 107 into a plurality of relatively short gate electrodes 107, and isolates the plurality of gate electrodes 107 from each other. In addition, the excess dielectric material of the cut metal gate structure 109 outside the second opening 901 can be retained and used as a shielding layer in the continuous polysilicon on diffusion edge (Continuous Poly On Diffusion Edge, CPODE) process. Fig. 10B , where excess dielectric material remains outside the second opening 901 .

[0170] FIG. 11A to FIG. 11B A cross-sectional view of forming a third opening 1003 in an initial step in forming a continuous poly on diffusion edge (CPODE) structure 111 according to some embodiments is shown. The CPODE structure 111 may also be referred to herein as an isolation structure, a cut-poly structure, or a cut-PODE structure, and is discussed in more detail in the following figures.

[0171] Once the cut metal gate structure 109 has been formed, a photoresist may be formed over the excess dielectric material, and an opening may be formed in the photoresist at the desired location of the CPODE structure 111 to be formed. The opening in the photoresist is formed to expose a portion of the gate cap 801 between the two cut metal gate structures 109. In addition, an edge portion of the cut metal gate structure 109 may also be exposed through the opening in the photoresist in order to provide some process space for the CPODE structure 111. According to some embodiments, the width of the exposed edge portion may be between about 3 nm and about 25 nm, such as a fourth width W4 of 5 nm. However, any suitable width may be used.

[0172] The photoresist is then used as an etching mask to etch excess dielectric material, cut edge portions of the metal gate structure 109, the gate cap 801, and the gate electrode 107, so that a third opening 1003 (e.g., a trench, a recess, a channel, etc.) is formed in a desired location of the CPODE structure 111. According to some embodiments, the etching process may stop on the gate dielectric 703. Therefore, the gate dielectric 703 and the nanostructure 701 remain at the bottom of the third opening 1003. According to some embodiments, the etching process for forming the third opening 1003 may be an isotropic etching process (e.g., a wet etching process) using an etchant, and the etchant stops on the gate dielectric 703. However, other suitable etching processes may also be used, including an anisotropic etching process (e.g., a dry etching process or a reactive ion etching (RIE) process), a combination of isotropic etching and anisotropic etching, etc. According to some embodiments, third opening 1003 is formed to a fifth width W5 between about 20 nm and about 200 nm, such as about 70 nm. However, any suitable width may be used.

[0173] FIG. 12A to FIG. 12B A cross-sectional view of another etching process in an intermediate step of performing a CPODE process according to some embodiments is shown. Once the gate dielectric 703 has been exposed, another etching process is performed to remove the material of the gate dielectric 703 within the third opening 1003 and expose the nanostructure 701, the fin 105, and the isolation region 209 within the third opening 1003. According to some embodiments, wet etching, dry etching, combinations, etc. may be used to remove the material of the gate dielectric 703 without substantially removing the material of the top spacer 309 and the inner spacer 403 along the vertical sidewalls of the third opening 1003. However, any suitable etching process may be used.

[0174] Once the nanostructure 701 and the portion of the fin 105 protruding above the isolation region 209 are exposed, another etching process can be used to remove the material of the nanostructure 701 and form a recess in the fin 105. According to some embodiments, an etching process such as wet etching, dry etching, a combination, etc., can be used to remove these materials without substantially removing the material of the top spacer 309, the inner spacer 403, and the isolation region 209 in the third opening 1003. According to an embodiment, the portion of the fin 105 protruding above the isolation region 209 can be recessed to a second depth D2 between about 2nm and about 20nm, such as about 10nm. However, any suitable depth can be used. According to some embodiments, the first ratio R1 of the second depth D2 of the bottom spacer 501 to the third height H3 can be between about 0.05:1 and about 1:1. Once the nanostructure 701 has been removed and the portion of the fin 105 protruding above the isolation region 209 has been recessed, the photoresist can be removed, for example, by an ashing process.

[0175] FIG. 13A to FIG. 13B A cross-sectional view of forming a CPODE structure 111 according to some embodiments is shown. The CPODE structure 111 may be formed by depositing a dielectric material to fill and / or overfill the third opening 1003. The CPODE structure 111 may be formed using dielectric materials such as silicon nitride (SiN), oxide (OX), silicon oxynitride (SiON), silicon oxycarbonitride (SiOCN), silicon carbonitride (SiCN), etc. According to some embodiments, the CPODE structure 111 is formed using materials such as metal oxides of zirconium (Zr), hafnium (Hf), aluminum (Al), etc. In addition, the CPODE structure 111 may be formed using a suitable deposition process such as chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), a combination of these processes, etc. The CPODE structure 111 may be formed using any of the dielectric materials and processes suitable for forming the cut metal gate structure 109. According to some embodiments, the dielectric material used to form the CPODE structure 111 is formed of the same material as the dielectric material used to form the cut metal gate structure 109, although the dielectric material may also be different. For example, in an embodiment where the cut metal gate structure 109 is formed using silicon nitride (SiN), the CPODE structure 111 may be formed using silicon nitride (SiN) via a deposition process such as chemical vapor deposition (CVD), atomic layer deposition (ALD), sputtering, etc.

[0176] Once formed, excess material of the CPODE structure 111 outside the third opening 1003 may be removed by a chemical mechanical planarization (CMP) process. According to some embodiments, the chemical mechanical planarization (CMP) process may continue to planarize the surface of the CPODE structure 111 with the gate electrode 107 and the interlayer dielectric layer 603. Once planarized, the CPODE structure 111 above the fin 105 has a seventh height H7 between about 55nm and about 140nm, such as about 70nm. However, any suitable height may be used. The gate cap 801 has an eighth height H8 between 10nm and about 30nm, such as about 15nm. However, any suitable height may be used. In addition, the cut metal gate structure 109 has a ninth height H9 between 50nm and about 120nm, such as about 60nm. However, any suitable height may be used.

[0177] According to some embodiments, a method for manufacturing a semiconductor device may continue with operations such as: forming source / drain contacts to source / drain regions; forming a second ILD layer; forming source / drain vias and gate vias through the second ILD layer to provide electrical connectivity to the source / drain regions and the gate electrode.

[0178] The method herein provides gate height distribution optimization. Post-CMP topology is one of the key factors determining IC performance and manufacturing difficulty. Topology requirements depend on layers (i.e., OD / PO / CPODE / CMG, etc.), layout (SRAM / RO / VBD, etc.), lithography, overlay marks, etc. Optimized topology distribution can satisfy all topology requirements to achieve the best performance / yield.

[0179] For example, for gate height, i.e., the final height after the CMP process used to grind the CPODE structure 111 above the fin 105, lower gate heights produce better IC performance (lower capacitance) but also make manufacturing more difficult (i.e., CMP tends to over-grind). Optimizing gate height distribution balances performance and reliability.

[0180] See also Fig.14 and Fig.15 , showing the gate height of two embodiments. Fig.14 and Fig.15 In both, gate 807 may represent gate electrode 107 and gate cap 801 together, or alternatively may represent only gate electrode 107 .

[0181] In addition, Fig.14In some embodiments, gate 807 is formed on alternating semiconductor layers 207 so as to overlap fin 105, such as in a GAA semiconductor device. Fig.15 According to some embodiments, the gate 807 is formed on the fin 105 in a semiconductor device such as a FinFET.

[0182] In each case, gate 807 extends from a lowermost surface 806, such as at the interface with fin 105 or layer 207, to an uppermost surface 808, which may be formed by a post-CPODE CMP process. As depicted, lowermost surface 806 and uppermost surface 808 are separated by gate height H14.

[0183] The gate height H14 may vary according to the gate length of the semiconductor device. In addition, semiconductor devices with different gate lengths are manufactured on the semiconductor die. For example, the die may include semiconductor devices having gate lengths of 3 nanometers (nm), 9 nanometers (nm), 55 nanometers (nm), and 135 nanometers (nm).

[0184] Fig.16 FIG. 1 is a semiconductor device density map of a semiconductor die 1600 on which semiconductor devices are formed. As shown, the die 1600 includes die regions 1601, 1602, 1603, and 1604 where semiconductor devices of different gate lengths are formed. Generally speaking, semiconductor devices with a gate length of 3 nm form dense regions, while semiconductor devices with longer gate lengths form less dense regions. In an exemplary embodiment, semiconductor devices with a gate length of 135 nm form more than 45% of the area of ​​the die 1600, semiconductor devices with a gate length of 55 nm form 25% to 35% of the area of ​​the die 1600, and semiconductor devices with a gate length of 3 nm are formed on 0 to 25% of the area of ​​the die 1600.

[0185] in addition, Fig.16 The die 1600 is shown having corners 1605. During semiconductor manufacturing, the gate height in the corners 1605 of the die 1600 is typically lower than in the center or other areas of the die. This is because of the nature of the manufacturing process and the underlying physics of the materials involved. For example, during the patterning process, it may be difficult to achieve uniform coverage and thickness of the gate material at the corners of the die due to various factors such as the angle of the patterning mask or the deposition process used. Therefore, the gate height may be slightly lower in these areas compared to the center or other areas of the die.

[0186] In various embodiments, the minimum height of a semiconductor device having a certain gate length is located in a corner 1605 of the die 1600 in such semiconductor device.

[0187] In some embodiments, the semiconductor die 1600 has a large number of semiconductor devices having a gate length of 3 nanometers. Of the total number of semiconductor devices having a gate length of 3 nanometers, more than 95% have a gate height H14 from 10 nanometers to 14 nanometers (nm). For example, of the total number of semiconductor devices having a gate length of 3 nanometers, more than 96%, more than 97%, more than 98%, more than 98.5%, more than 98.8%, more than 98.9%, more than 99%, more than 99.1%, or 99.15% have a gate height H14 from 10 nanometers to 14 nanometers (nm). In addition, of the total number of semiconductor devices having a gate length of 3 nanometers, less than 99.9%, less than 99.8%, less than 99.7%, less than 99.6%, less than 99.5%, less than 99.4%, less than 99.3%, less than 99.2% or 99.15% have a gate height H14 from 10 to 14 nanometers (nm).

[0188] In addition, among the total number of semiconductor devices having a gate length of 3 nanometers, more than 0.2% have a gate height H14 greater than 14 nanometers (nm). For example, among the total number of semiconductor devices having a gate length of 3 nanometers, more than 0.3%, more than 0.4%, more than 0.5%, more than 0.55%, more than 0.6%, or 0.65% have a gate height H14 greater than 14 nanometers (nm). In addition, among the total number of semiconductor devices having a gate length of 3 nanometers, less than 1%, less than 0.9%, less than 0.8%, less than 0.75%, less than 0.7%, or 0.65% have a gate height H14 greater than 14 nanometers (nm).

[0189] In some embodiments, in a population of semiconductor devices having a gate length of 3 nanometers, the maximum gate height H14 is at least 16 nm, at least 16.5 nm, at least 17 nm, at least 17.5 nm, at least 18 nm, at least 18.1 nm, at least 18.2 nm, at least 18.3 nm, or at least 18.4 nm. In some embodiments, in a population of semiconductor devices having a gate length of 3 nanometers, the maximum gate height H14 is no greater than 21 nm, no greater than 20.5 nm, no greater than 20 nm, no greater than 19.5 nm, no greater than 19 nm, no greater than 18.9 nm, no greater than 18.8 nm, no greater than 18.7 nm, no greater than 18.6 nm, no greater than 18.5 nm, or no greater than 18.4 nm. In some embodiments, in a population of semiconductor devices having a gate length of 3 nanometers, the maximum gate height H14 is 18.4 nm.

[0190] In addition, among the total number of semiconductor devices having a gate length of 3 nanometers, more than 0.05% have a gate height H14 less than 10 nanometers (nm). For example, among the total number of semiconductor devices having a gate length of 3 nanometers, more than 0.1%, more than 0.12%, more than 0.14%, more than 0.16%, more than 0.18%, or 0.2% have a gate height H14 less than 10 nanometers (nm). In addition, among the total number of semiconductor devices having a gate length of 3 nanometers, less than 1%, less than 0.8%, less than 0.6%, less than 0.5%, less than 0.4%, less than 0.35%, less than 0.3%, less than 0.25%, or 0.2% have a gate height H14 less than 10 nanometers (nm).

[0191] In some embodiments, in the total number of semiconductor devices having a gate length of 3 nanometers, the minimum gate height H14 is at least 4 nm, at least 4.5 nm, at least 5 nm, at least 5.2 nm, at least 5.4 nm, at least 5.6 nm, at least 5.8 nm, at least 6 nm, or at least 6.2 nm. In some embodiments, in the total number of semiconductor devices having a gate length of 3 nanometers, the minimum gate height H14 is no greater than 10 nm, no greater than 9 nm, no greater than 8.5 nm, no greater than 8 nm, no greater than 7.5 nm, no greater than 7 nm, no greater than 6.8 nm, no greater than 6.6 nm, no greater than 6.4 nm, or no greater than 6.2 nm. In some embodiments, in the total number of semiconductor devices having a gate length of 3 nanometers, the minimum gate height H14 is 6.2 nm.

[0192] In some embodiments, the semiconductor die 1600 has a large number of semiconductor devices having a gate length of 9 nanometers. Of the total number of semiconductor devices having a gate length of 9 nanometers, more than 90% have a gate height H14 from 10 to 13 nanometers (nm). For example, of the total number of semiconductor devices having a gate length of 9 nanometers, more than 91%, more than 92%, more than 93%, more than 94%, more than 94.2%, more than 94.4%, more than 94.5%, more than 94.6%, or 94.7% have a gate height H14 from 10 to 13 nanometers (nm). In addition, less than 99%, less than 98%, less than 97%, less than 96%, less than 95%, less than 94.9%, less than 94.8%, or 94.7% of the total number of semiconductor devices having a gate length of 9 nanometers have a gate height H14 from 10 to 13 nanometers (nm).

[0193] In addition, among the total number of semiconductor devices having a gate length of 9 nanometers, more than 2% have a gate height H14 greater than 13 nanometers (nm). For example, among the total number of semiconductor devices having a gate length of 9 nanometers, more than 2.5%, more than 3%, more than 3.2%, more than 3.4%, more than 3.6%, or 3.8% have a gate height H14 greater than 13 nanometers (nm). In addition, among the total number of semiconductor devices having a gate length of 9 nanometers, less than 6%, less than 5.5%, less than 5%, less than 4.8%, less than 4.6%, less than 4.4%, less than 4.2%, less than 4.1%, less than 4%, less than 3.9%, or 3.8% have a gate height H14 greater than 13 nanometers (nm).

[0194] In some embodiments, in a population of semiconductor devices having a gate length of 9 nanometers, the maximum gate height H14 is at least 16 nm, at least 16.5 nm, at least 17 nm, at least 17.1 nm, at least 17.2 nm, at least 17.3 nm, or at least 17.4 nm. In some embodiments, in a population of semiconductor devices having a gate length of 9 nanometers, the maximum gate height H14 is no greater than 21 nm, no greater than 20 nm, no greater than 19 nm, no greater than 18.5 nm, no greater than 18 nm, no greater than 17.9 nm, no greater than 17.8 nm, no greater than 17.7 nm, no greater than 17.6 nm, no greater than 17.5 nm, or no greater than 17.4 nm. In some embodiments, in a population of semiconductor devices having a gate length of 9 nanometers, the maximum gate height H14 is 17.4 nm.

[0195] In addition, among the total number of semiconductor devices having a gate length of 9 nanometers, more than 0.5% have a gate height H14 less than 10 nanometers (nm). For example, among the total number of semiconductor devices having a gate length of 9 nanometers, more than 0.75%, more than 1%, more than 1.1%, more than 1.2%, more than 1.3%, more than 1.4%, or 1.5% have a gate height H14 less than 10 nanometers (nm). In addition, among the total number of semiconductor devices having a gate length of 9 nanometers, less than 3%, less than 2.75%, less than 2.5%, less than 2.25%, less than 2%, less than 1.9%, less than 1.8%, less than 1.7%, less than 1.6%, or 1.5% have a gate height H14 less than 10 nanometers (nm).

[0196] In some embodiments, in the total number of semiconductor devices having a gate length of 9 nanometers, the minimum gate height H14 is at least 4 nm, at least 5 nm, at least 6 nm, at least 6.5 nm, at least 7 nm, at least 7.5 nm, at least 7.6 nm, at least 7.7 nm, at least 7.8 nm, at least 7.9 nm, at least 8 nm, or at least 8.1 nm. In some embodiments, in the total number of semiconductor devices having a gate length of 9 nanometers, the minimum gate height H14 is no greater than 10 nm, no greater than 9.5 nm, no greater than 9 nm, no greater than 8.9 nm, no greater than 8.8 nm, no greater than 8.7 nm, no greater than 8.6 nm, no greater than 8.5 nm, no greater than 8.4 nm, no greater than 8.3 nm, no greater than 8.2 nm, or no greater than 8.1 nm. In some embodiments, in the total number of semiconductor devices having a gate length of 9 nanometers, the minimum gate height H14 is 8.1 nm.

[0197] In some embodiments, the semiconductor die 1600 has a large number of semiconductor devices having a gate length of 55 nanometers. Of the total number of semiconductor devices having a gate length of 55 nanometers, more than 90% have a gate height H14 from 14 to 19 nanometers (nm). For example, of the total number of semiconductor devices having a gate length of 55 nanometers, more than 90.5%, more than 91%, more than 91.5%, more than 92%, more than 92.2%, more than 92.4%, more than 92.6%, more than 92.8%, more than 92.9%, or 93% have a gate height H14 from 14 to 19 nanometers (nm). In addition, of the total number of semiconductor devices having a gate length of 55 nanometers, less than 99%, less than 98%, less than 97%, less than 96%, less than 95%, less than 94.5%, less than 94%, less than 93.75%, less than 93.5%, less than 93.25% or 93% have a gate height H14 from 14 to 19 nanometers (nm).

[0198] In addition, among the total number of semiconductor devices having a gate length of 55 nanometers, more than 2% have a gate height H14 greater than 19 nanometers (nm). For example, among the total number of semiconductor devices having a gate length of 55 nanometers, more than 2.5%, more than 2.75%, more than 3%, more than 3.1%, more than 3.2%, more than 3.3%, more than 3.4%, or 3.5% have a gate height H14 greater than 19 nanometers (nm). In addition, among the total number of semiconductor devices having a gate length of 55 nanometers, less than 6%, less than 5%, less than 4.5%, less than 4%, less than 3.9%, less than 3.8%, less than 3.7%, less than 3.6%, or 3.5% have a gate height H14 greater than 19 nanometers (nm).

[0199] In some embodiments, in a population of semiconductor devices having a gate length of 55 nanometers, the maximum gate height H14 is at least 16 nm, at least 17 nm, at least 18 nm, at least 19 nm, at least 19.5 nm, at least 20 nm, at least 20.5 nm, at least 21 nm, at least 21.1 nm, at least 21.2 nm, at least 21.3 nm, at least 21.4 nm, at least 21.5 nm, or at least 21.6 nm. In some embodiments, in a population of semiconductor devices having a gate length of 55 nanometers, the maximum gate height H14 is no greater than 24 nm, no greater than 23 nm, no greater than 22.5 nm, no greater than 22 nm, no greater than 21.9 nm, no greater than 21.8 nm, no greater than 21.7 nm, or no greater than 21.6 nm. In some embodiments, in a population of semiconductor devices having a gate length of 55 nanometers, the maximum gate height H14 is 21.6 nm.

[0200] In addition, among the total number of semiconductor devices having a gate length of 55 nanometers, more than 1% have a gate height H14 less than 14 nanometers (nm). For example, among the total number of semiconductor devices having a gate length of 55 nanometers, more than 1.5%, more than 2%, more than 2.5%, more than 3%, more than 3.5%, more than 3.75%, more than 4%, more than 4.25%, or more than 4.5% have a gate height H14 less than 14 nanometers (nm). In addition, among the total number of semiconductor devices having a gate length of 55 nanometers, less than 8%, less than 7%, less than 6%, less than 5.5%, less than 5%, less than 4.9%, less than 4.8%, less than 4.7%, less than 4.6%, or less than 4.5% have a gate height H14 less than 14 nanometers (nm).

[0201] In some embodiments, in a population of semiconductor devices having a gate length of 55 nanometers, the minimum gate height H14 is at least 6 nm, at least 7 nm, at least 8 nm, at least 9 nm, at least 9.5 nm, at least 10 nm, at least 10.5 nm, at least 10.6 nm, at least 10.7 nm, at least 10.8 nm, at least 10.9 nm, at least 11 nm, or at least 11.1 nm. In some embodiments, in a population of semiconductor devices having a gate length of 55 nanometers, the minimum gate height H14 is no greater than 15 nm, no greater than 14 nm, no greater than 13 nm, no greater than 12.5 nm, no greater than 12 nm, no greater than 11.9 nm, no greater than 11.8 nm, no greater than 11.7 nm, no greater than 11.6 nm, no greater than 11.5 nm, no greater than 11.4 nm, no greater than 11.3 nm, no greater than 11.2 nm, or no greater than 11.1 nm. In some embodiments, in a population of semiconductor devices having a gate length of 55 nanometers, the minimum gate height H14 is 11.1 nm.

[0202] In some embodiments, the semiconductor die 1600 has a large number of semiconductor devices having a gate length of 135 nanometers. Of the total number of semiconductor devices having a gate length of 135 nanometers, more than 85% have a gate height H14 from 16 to 19 nanometers (nm). For example, of the total number of semiconductor devices having a gate length of 135 nanometers, more than 88%, more than 89%, more than 90%, more than 90.5%, more than 91%, more than 91.2%, more than 91.4%, more than 91.5%, more than 91.6%, more than 91.7%, or more than 91.8% have a gate height H14 from 16 to 19 nanometers (nm). In addition, of the total number of semiconductor devices having a gate length of 135 nanometers, less than 98%, less than 96%, less than 94%, less than 93%, less than 93.5%, less than 93%, less than 92.5%, less than 92.4%, less than 92.3%, less than 92.2%, less than 92.1%, less than 92%, less than 91.9% or 91.8% have a gate height H14 from 16 to 19 nanometers (nm).

[0203] In addition, among the total number of semiconductor devices having a gate length of 135 nanometers, more than 2% have a gate height H14 greater than 19 nanometers (nm). For example, among the total number of semiconductor devices having a gate length of 135 nanometers, more than 2.5%, more than 2.75%, more than 3%, more than 3.1%, more than 3.2%, more than 3.3%, more than 3.4%, or 3.5% have a gate height H14 greater than 19 nanometers (nm). In addition, with respect to the total number of semiconductor devices having a gate length of 135 nanometers, less than 6%, less than 5%, less than 4.5%, less than 4%, less than 3.9%, less than 3.8%, less than 3.7%, less than 3.6%, or 3.5% have a gate height H14 greater than 19 nanometers (nm).

[0204] In some embodiments, in a population of semiconductor devices having a gate length of 135 nanometers, the maximum gate height H14 is at least 16 nm, at least 17 nm, at least 18 nm, at least 19 nm, at least 19.5 nm, at least 20 nm, at least 20.1 nm, at least 20.2 nm, at least 20.3 nm, at least 20.4 nm, or at least 20.5 nm. In some embodiments, in a population of semiconductor devices having a gate length of 135 nanometers, the maximum gate height H14 is no greater than 24 nm, no greater than 23 nm, no greater than 22.5 nm, no greater than 22 nm, no greater than 21.5 nm, no greater than 21 nm, no greater than 20.9 nm, no greater than 20.8 nm, no greater than 20.7 nm, no greater than 20.6 nm, or no greater than 20.5 nm. In some embodiments, in a population of semiconductor devices having a gate length of 135 nanometers, the maximum gate height H14 is 20.5 nm.

[0205] In addition, among the total number of semiconductor devices having a gate length of 135 nanometers, more than 3% have a gate height H14 less than 16 nanometers (nm). For example, among the total number of semiconductor devices having a gate length of 135 nanometers, more than 3.5%, more than 4%, more than 4.5%, more than 5%, more than 5.1%, more than 5.2%, more than 5.3%, more than 5.4%, more than 5.5%, more than 5.6%, or 5.7% have a gate height H14 less than 16 nanometers (nm). In addition, among the total number of semiconductor devices having a gate length of 135 nanometers, less than 10%, less than 9%, less than 8%, less than 7%, less than 6.5%, less than 6%, less than 5.9%, less than 5.8%, or 5.7% have a gate height H14 less than 16 nanometers (nm).

[0206] In some embodiments, in a population of semiconductor devices having a gate length of 135 nanometers, the minimum gate height H14 is at least 6 nm, at least 7 nm, at least 8 nm, at least 9 nm, at least 10 nm, at least 11 nm, at least 11.5 nm, at least 12 nm, at least 12.5 nm, at least 12.6 nm, at least 12.7 nm, at least 12.8 nm, at least 12.9 nm, at least 13 nm, or at least 13.1 nm. In some embodiments, in a population of semiconductor devices having a gate length of 135 nanometers, the minimum gate height H14 is no greater than 15 nm, no greater than 14.5 nm, no greater than 14 nm, no greater than 13.5 nm, no greater than 13.4 nm, no greater than 13.3 nm, no greater than 13.2 nm, or no greater than 13.1 nm. In some embodiments, in a population of semiconductor devices having a gate length of 135 nanometers, the minimum gate height H14 is 13.1 nm.

[0207] The maximum gate height difference between semiconductor devices with different gate lengths is obtained by calculating the maximum difference between the respective maximum gate height and the minimum gate height. For example, for a semiconductor device with a gate length of 3 nanometers, the maximum gate height is 18.4nm, and the minimum is 6.2nm. For a semiconductor device with a gate length of 9 nanometers, the maximum gate height is 17.4nm, and the minimum is 8.1nm. The difference between 18.4nm and 8.1nm is 10.3nm, and the difference between 17.4nm and 6.2nm is 11.2nm. Therefore, the maximum difference between a semiconductor device with a gate length of 3 nanometers and a semiconductor device with a gate length of 9nm is 11.2nm.

[0208] Therefore, it can be seen that the maximum difference between a semiconductor device with a gate length of 3 nanometers and a semiconductor device with a gate length of 55 nanometers is 15.4 nm; the maximum difference between a semiconductor device with a gate length of 3 nanometers and a semiconductor device with a gate length of 135 nanometers is 14.3 nm; the maximum difference between a semiconductor device with a gate length of 9 nanometers and a semiconductor device with a gate length of 55 nanometers is 13.5 nm; the maximum difference between a semiconductor device with a gate length of 9 nanometers and a semiconductor device with a gate length of 135 nanometers is 12.4 nm; and the maximum difference between a semiconductor device with a gate length of 55 nanometers and a semiconductor device with a gate length of 135 nanometers is 9.4 nm.

[0209] As described herein, semiconductor dies are designed with an optimized distribution of gate heights for performance and yield.

[0210] In one embodiment, a method for manufacturing a semiconductor device on a die includes the steps of forming a plurality of semiconductor devices having a gate length of 3 nanometers (nm) and having a plurality of metal gates, wherein more than 99% of the semiconductor devices having a gate length of 3 nanometers (nm) have a gate height from 10 to 14 nanometers (nm).

[0211] In certain embodiments of the method, such semiconductor devices with a gate length of 3 nanometers (nm) located at a corner of the die have a minimum gate height of 6.2 nanometers (nm).

[0212] In certain embodiments of the method, such semiconductor devices having a gate length of 3 nanometers (nm) have a maximum gate height of 18.4 nanometers (nm).

[0213] In some embodiments, the method further includes the step of forming a plurality of semiconductor devices having a gate length of 9 nanometers (nm) and having a plurality of metal gates, wherein more than 90% of the semiconductor devices having a gate length of 9 nanometers (nm) have a gate height from 10 to 13 nanometers (nm).

[0214] In certain embodiments of the method, such semiconductor devices with a gate length of 9 nanometers (nm) located at the corners of the die have a minimum gate height of 8.1 nanometers (nm).

[0215] In certain embodiments of the method, such semiconductor devices having a gate length of 9 nanometers (nm) have a maximum gate height of 17.4 nanometers (nm).

[0216] In some embodiments, the method further includes the step of forming a plurality of semiconductor devices having a gate length of 55 nanometers (nm) and having a plurality of metal gates, wherein more than 90% of the semiconductor devices having a gate length of 55 nanometers (nm) have a gate height from 14 to 19 nanometers (nm).

[0217] In certain embodiments of the method, such semiconductor devices with a gate length of 55 nanometers (nm) located at the corners of the die have a minimum gate height of 11.1 nanometers (nm).

[0218] In certain embodiments of the method, such semiconductor devices having a gate length of 55 nanometers (nm) have a maximum gate height of 21.6 nanometers (nm).

[0219] In some embodiments, the method further includes the step of forming a plurality of semiconductor devices having a gate length of 135 nanometers (nm) and having a plurality of metal gates, wherein more than 90% of the semiconductor devices having a gate length of 135 nanometers (nm) have a gate height from 16 to 19 nanometers (nm).

[0220] In some embodiments of the method, the semiconductor devices with a gate length of 135 nanometers (nm) located at a corner of the die have a minimum gate height of 13.1 nanometers (nm).

[0221] In certain embodiments of the method, the semiconductor devices having a gate length of 135 nanometers (nm) have a maximum gate height of 20.5 nanometers (nm).

[0222] In certain embodiments of the method, the gate height of such semiconductor devices having less than 1% of a gate length of 3 nanometers (nm) is greater than 14 nanometers (nm).

[0223] In certain embodiments of the method, the gate height of such semiconductor devices having less than 0.5% of a gate length of 3 nanometers (nm) is less than 10 nanometers (nm).

[0224] In another embodiment, a method for manufacturing semiconductor devices on a die includes the following steps: forming a plurality of semiconductor devices having a gate length of 3 nanometers (nm) and having a plurality of metal gates, wherein more than 99% of the semiconductor devices having a gate length of 3 nanometers (nm) have a gate height of from 10 to 14 nanometers (nm); forming a plurality of semiconductor devices having a gate length of 9 nanometers (nm) and having a plurality of metal gates, wherein more than 90% of the semiconductor devices having a gate length of 9 nanometers (nm) have a gate height of from 10 to 13 nanometers (nm); The invention relates to a method for forming a semiconductor device having a gate length of 55 nanometers (nm) and a gate height of 14 to 19 nanometers (nm); forming a plurality of semiconductor devices having a gate length of 55 nanometers (nm) and a plurality of metal gates, wherein more than 90% of the semiconductor devices having a gate length of 55 nanometers (nm) have a gate height of 14 to 19 nanometers (nm); and forming a plurality of semiconductor devices having a gate length of 135 nanometers (nm) and a plurality of metal gates, wherein more than 90% of the semiconductor devices having a gate length of 135 nanometers (nm) have a gate height of 16 to 19 nanometers (nm).

[0225] In some embodiments of the method, the semiconductor devices having a gate length of 3 nanometers (nm) have a minimum gate height of 6.2 nanometers (nm) and a maximum gate height of 18.4 nanometers (nm).

[0226] In certain embodiments of the method, such semiconductor devices having a gate length of 9 nanometers (nm) have a minimum gate height of 8.1 nanometers (nm) and a maximum gate height of 17.4 nanometers (nm); such semiconductor devices having a gate length of 55 nanometers (nm) have a minimum gate height of 11.1 nanometers (nm) and a maximum gate height of 21.6 nanometers (nm); and such semiconductor devices having a gate length of 135 nanometers (nm) have a minimum gate height of 13.1 nanometers (nm) and a maximum gate height of 20.5 nanometers (nm).

[0227] In another embodiment, a semiconductor die includes: a plurality of semiconductor devices having a gate length of 3 nanometers (nm), a minimum gate height of 6.2 nanometers (nm) and a maximum gate height of 18.4 nanometers (nm); a plurality of semiconductor devices having a gate length of 9 nanometers (nm), a minimum gate height of 8.1 nanometers (nm) and a maximum gate height of 17.4 nanometers (nm); a plurality of semiconductor devices having a gate length of 55 nanometers (nm), a minimum gate height of 11.1 nanometers (nm) and a maximum gate height of 21.6 nanometers (nm); and a plurality of semiconductor devices having a gate length of 135 nanometers (nm), a minimum gate height of 13.1 nanometers (nm) and a maximum gate height of 20.5 nanometers (nm).

[0228] In certain embodiments of the semiconductor die, more than 99% of such semiconductor devices having a gate length of 3 nanometers (nm) have a gate height of from 10 to 14 nanometers (nm); more than 90% of such semiconductor devices having a gate length of 9 nanometers (nm) have a gate height of from 10 to 13 nanometers (nm); more than 90% of such semiconductor devices having a gate length of 55 nanometers (nm) have a gate height of from 14 to 19 nanometers (nm); and more than 90% of such semiconductor devices having a gate length of 135 nanometers (nm) have a gate height of from 16 to 19 nanometers (nm).

[0229] In certain embodiments of the semiconductor die, 99.15% of these semiconductor devices having a gate length of 3 nanometers (nm) have a gate height from 10 to 14 nanometers (nm); 94.7% of these semiconductor devices having a gate length of 9 nanometers (nm) have a gate height from 10 to 13 nanometers (nm); 93% of these semiconductor devices having a gate length of 55 nanometers (nm) have a gate height from 14 to 19 nanometers (nm); and 91.8% of these semiconductor devices having a gate length of 135 nanometers (nm) have a gate height from 16 to 19 nanometers (nm).

[0230] In some embodiments of the semiconductor die, the maximum gate height difference between these semiconductor devices having a gate length of 3 nanometers (nm) and these semiconductor devices having a gate length of 9 nanometers (nm) is 11.2 nanometers (nm); the maximum gate height difference between these semiconductor devices having a gate length of 3 nanometers (nm) and these semiconductor devices having a gate length of 55 nanometers (nm) is 15.4 nanometers (nm); the maximum gate height difference between these semiconductor devices having a gate length of 3 nanometers (nm) and these semiconductor devices having a gate length of 135 nanometers (nm) is 14.3 nanometers (nm); meters (nm); the maximum gate height difference between these semiconductor devices with a gate length of 9 nanometers (nm) and these semiconductor devices with a gate length of 55 nanometers (nm) is 13.5 nanometers (nm); the maximum gate height difference between these semiconductor devices with a gate length of 9 nanometers (nm) and these semiconductor devices with a gate length of 135 nanometers (nm) is 12.4 nanometers (nm); and the maximum gate height difference between these semiconductor devices with a gate length of 55 nanometers (nm) and these semiconductor devices with a gate length of 135 nanometers (nm) is 9.4 nanometers (nm).

[0231] Some embodiments of the present disclosure provide a method for manufacturing a semiconductor die, the method comprising: forming a plurality of first semiconductor devices, the first semiconductor devices having a gate length of 3 nanometers and having a plurality of first metal gates, wherein more than 99% of these first semiconductor devices having a gate length of 3 nanometers have a gate height ranging from 10 nanometers to 14 nanometers.

[0232] In some embodiments, such first semiconductor devices located at corners of a semiconductor die with a gate length of 3 nanometers have a minimum gate height of 6.2 nanometers.

[0233] In some embodiments, a first semiconductor device having a gate length of 3 nanometers has a maximum gate height of 18.4 nanometers.

[0234] In some embodiments, the method further includes the step of forming a plurality of second semiconductor devices having a gate length of 9 nanometers and having a plurality of second metal gates, wherein more than 90% of the second semiconductor devices having a gate length of 9 nanometers have a gate height from 10 nanometers to 13 nanometers.

[0235] In some embodiments, such second semiconductor devices located at corners of the semiconductor die with a gate length of 9 nanometers have a minimum gate height of 8.1 nanometers.

[0236] In some embodiments, such second semiconductor devices having a gate length of 9 nanometers have a maximum gate height of 17.4 nanometers.

[0237] In some embodiments, the method further includes the step of forming a plurality of third semiconductor devices having a gate length of 55 nanometers and having a plurality of third metal gates, wherein more than 90% of the third semiconductor devices having a gate length of 55 nanometers have a gate height from 14 nanometers to 19 nanometers.

[0238] In some embodiments, such third semiconductor devices located at corners of the semiconductor die with a gate length of 55 nanometers have a minimum gate height of 11.1 nanometers.

[0239] In some embodiments, such third semiconductor devices having a gate length of 55 nanometers have a maximum gate height of 21.6 nanometers.

[0240] In some embodiments, the method further includes the step of forming a plurality of fourth semiconductor devices having a gate length of 135 nanometers and having a plurality of fourth metal gates, wherein more than 90% of the fourth semiconductor devices having a gate length of 135 nanometers have a gate height from 16 nanometers to 19 nanometers.

[0241] In some embodiments, such fourth semiconductor devices located at corners of the semiconductor die with a gate length of 135 nanometers have a minimum gate height of 13.1 nanometers.

[0242] In some embodiments, such fourth semiconductor devices having a gate length of 135 nanometers have a maximum gate height of 20.5 nanometers.

[0243] In some embodiments, less than 1% of the first semiconductor devices having a gate length of 3 nanometers have a gate height greater than 14 nanometers.

[0244] In some embodiments, less than 0.5% of the first semiconductor devices having a gate length of 3 nanometers have a gate height less than 10 nanometers.

[0245] Some embodiments of the present disclosure provide a method for manufacturing a semiconductor die, the method comprising: forming a plurality of first semiconductor devices, the first semiconductor devices having a gate length of 3 nanometers and having a plurality of first metal gates, wherein more than 99% of the first semiconductor devices having a gate length of 3 nanometers have a gate height of from 10 nanometers to 14 nanometers; forming a plurality of second semiconductor devices, the second semiconductor devices having a gate length of 9 nanometers and having a plurality of second metal gates, wherein more than 90% of the second semiconductor devices having a gate length of 9 nanometers have a gate height of from 10 nanometers to 13 nanometers; forming a plurality of third semiconductor devices, the third semiconductor devices having a gate length of 55 nanometers and having a plurality of third metal gates, wherein more than 90% of the third semiconductor devices having a gate length of 55 nanometers have a gate height of from 14 nanometers to 19 nanometers; and forming a plurality of fourth semiconductor devices, the fourth semiconductor devices having a gate length of 135 nanometers and having a plurality of fourth metal gates, wherein more than 90% of the fourth semiconductor devices having a gate length of 135 nanometers have a gate height of from 16 nanometers to 19 nanometers.

[0246] In some embodiments, these first semiconductor devices with a gate length of 3 nanometers have a minimum gate height of 6.2 nanometers and a maximum gate height of 18.4 nanometers; these second semiconductor devices with a gate length of 9 nanometers have a minimum gate height of 8.1 nanometers and a maximum gate height of 17.4 nanometers; these third semiconductor devices with a gate length of 55 nanometers have a minimum gate height of 11.1 nanometers and a maximum gate height of 21.6 nanometers; and these fourth semiconductor devices with a gate length of 135 nanometers have a minimum gate height of 13.1 nanometers and a maximum gate height of 20.5 nanometers.

[0247] Some embodiments of the present disclosure provide a semiconductor die comprising: a plurality of first semiconductor devices having a gate length of 3 nanometers, having a minimum gate height of 6.2 nanometers and a maximum gate height of 18.4 nanometers; a plurality of second semiconductor devices having a gate length of 9 nanometers, having a minimum gate height of 8.1 nanometers and a maximum gate height of 17.4 nanometers; a plurality of third semiconductor devices having a gate length of 55 nanometers, having a minimum gate height of 11.1 nanometers and a maximum gate height of 21.6 nanometers; and a plurality of fourth semiconductor devices having a gate length of 135 nanometers, having a minimum gate height of 13.1 nanometers and a maximum gate height of 20.5 nanometers.

[0248] In some embodiments, more than 99% of these first semiconductor devices having a gate length of 3 nanometers have a gate height from 10 nanometers to 14 nanometers; more than 90% of these second semiconductor devices having a gate length of 9 nanometers have a gate height from 10 nanometers to 13 nanometers; more than 90% of these third semiconductor devices having a gate length of 55 nanometers have a gate height from 14 nanometers to 19 nanometers; and more than 90% of these fourth semiconductor devices having a gate length of 135 nanometers have a gate height from 16 nanometers to 19 nanometers.

[0249] In some embodiments, 99.15% of these first semiconductor devices having a gate length of 3 nanometers have a gate height from 10 nanometers to 14 nanometers; 94.7% of these second semiconductor devices having a gate length of 9 nanometers have a gate height from 10 nanometers to 13 nanometers; 93% of these third semiconductor devices having a gate length of 55 nanometers have a gate height from 14 nanometers to 19 nanometers; and 91.8% of these fourth semiconductor devices having a gate length of 135 nanometers have a gate height from 16 nanometers to 19 nanometers.

[0250] In some embodiments, the maximum gate height difference between these first semiconductor devices having a gate length of 3 nanometers and these second semiconductor devices having a gate length of 9 nanometers is 11.2 nanometers; the maximum gate height difference between these first semiconductor devices having a gate length of 3 nanometers and these third semiconductor devices having a gate length of 55 nanometers is 15.4 nanometers; the maximum gate height difference between these first semiconductor devices having a gate length of 3 nanometers and these fourth semiconductor devices having a gate length of 135 nanometers is 14.3 nanometers; the maximum gate height difference between these second semiconductor devices having a gate length of 9 nanometers and these third semiconductor devices having a gate length of 55 nanometers is 13.5 nanometers; the maximum gate height difference between these second semiconductor devices having a gate length of 9 nanometers and these fourth semiconductor devices having a gate length of 135 nanometers is 12.4 nanometers; and the maximum gate height difference between these third semiconductor devices having a gate length of 55 nanometers and these fourth semiconductor devices having a gate length of 135 nanometers is 9.4 nanometers.

[0251] Some embodiments of the present disclosure provide a semiconductor die comprising a plurality of first semiconductor devices having a gate length of 3 nanometers and a plurality of first metal gates, wherein more than 99% of the first semiconductor devices having a gate length of 3 nanometers have a gate height ranging from 10 nanometers to 14 nanometers.

[0252] In some embodiments, the semiconductor die further comprises a plurality of second semiconductor devices, the second semiconductor devices having a gate length of 9 nanometers and having a plurality of second metal gates, wherein more than 90% of the second semiconductor devices having a gate length of 9 nanometers have a gate height of from 10 nanometers to 13 nanometers. In some embodiments, the semiconductor die further comprises a plurality of third semiconductor devices, the third semiconductor devices having a gate length of 55 nanometers and having a plurality of third metal gates, wherein more than 90% of the third semiconductor devices having a gate length of 55 nanometers have a gate height of from 14 nanometers to 19 nanometers. In some embodiments, the semiconductor die further comprises a plurality of fourth semiconductor devices, the fourth semiconductor devices having a gate length of 135 nanometers and having a plurality of fourth metal gates, wherein more than 90% of the fourth semiconductor devices having a gate length of 135 nanometers have a gate height of from 16 nanometers to 19 nanometers. In some embodiments, less than 1% of the first semiconductor devices having a gate length of 3 nanometers have a gate height greater than 14 nanometers. In some embodiments, less than 0.5% of the first semiconductor devices having a gate length of 3 nanometers have a gate height less than 10 nanometers.

[0253] Some embodiments of the present disclosure provide a semiconductor die, including a plurality of first semiconductor devices, a plurality of second semiconductor devices, a plurality of third semiconductor devices, and a plurality of fourth semiconductor devices. The plurality of first semiconductor devices have a gate length of 3 nanometers. The plurality of second semiconductor devices have a gate length of 9 nanometers. The plurality of third semiconductor devices have a gate length of 55 nanometers. The plurality of fourth semiconductor devices have a gate length of 135 nanometers. The maximum gate height difference between these first semiconductor devices and these second semiconductor devices is 11.2 nanometers. The maximum gate height difference between these first semiconductor devices and these third semiconductor devices is 15.4 nanometers. The maximum gate height difference between these first semiconductor devices and these fourth semiconductor devices is 14.3 nanometers. The maximum gate height difference between these second semiconductor devices and these third semiconductor devices is 13.5 nanometers. The maximum gate height difference between these second semiconductor devices and these fourth semiconductor devices is 12.4 nanometers. The maximum gate height difference between these third semiconductor devices and these fourth semiconductor devices is 9.4 nanometers.

[0254] Some embodiments of the present disclosure provide a semiconductor die including a plurality of first semiconductor devices having a gate length of 3 nanometers, a plurality of second semiconductor devices having a gate length of 9 nanometers, a plurality of third semiconductor devices having a gate length of 55 nanometers, and a plurality of fourth semiconductor devices having a gate length of 135 nanometers. The plurality of first semiconductor devices have a minimum gate height of 6.2 nanometers and a maximum gate height of 18.4 nanometers. The plurality of second semiconductor devices have a minimum gate height of 8.1 nanometers and a maximum gate height of 17.4 nanometers. The plurality of third semiconductor devices have a minimum gate height of 11.1 nanometers and a maximum gate height of 21.6 nanometers. The plurality of fourth semiconductor devices have a minimum gate height of 13.1 nanometers and a maximum gate height of 20.5 nanometers.

[0255] In some embodiments, 99.15% of the gate heights of these first semiconductor devices with a gate length of 3 nanometers are from 10 nanometers to 14 nanometers; 94.7% of the gate heights of these second semiconductor devices with a gate length of 9 nanometers are from 10 nanometers to 13 nanometers. 93% of the gate heights of these third semiconductor devices with a gate length of 55 nanometers are from 14 nanometers to 19 nanometers. 91.8% of the gate heights of these fourth semiconductor devices with a gate length of 135 nanometers are from 16 nanometers to 19 nanometers. In some embodiments, the maximum gate height difference between these first semiconductor devices with a gate length of 3 nanometers and these second semiconductor devices with a gate length of 9 nanometers is 11.2 nanometers. In some embodiments, the maximum gate height difference between these first semiconductor devices with a gate length of 3 nanometers and these third semiconductor devices with a gate length of 55 nanometers is 15.4 nanometers. The maximum gate height difference between these first semiconductor devices having a gate length of 3 nanometers and these fourth semiconductor devices having a gate length of 135 nanometers is 14.3 nanometers. The maximum gate height difference between these second semiconductor devices having a gate length of 9 nanometers and these third semiconductor devices having a gate length of 55 nanometers is 13.5 nanometers. The maximum gate height difference between these second semiconductor devices having a gate length of 9 nanometers and these fourth semiconductor devices having a gate length of 135 nanometers is 12.4 nanometers. The maximum gate height difference between these third semiconductor devices having a gate length of 55 nanometers and these fourth semiconductor devices having a gate length of 135 nanometers is 9.4 nanometers.

[0256] The foregoing summarizes the features of several embodiments so that those skilled in the art can better understand the aspects of some embodiments of the present disclosure. Those skilled in the art will appreciate that they can readily use some embodiments of the present disclosure as a basis for designing or modifying other processes and structures for implementing the same purposes and / or achieving the same advantages of the embodiments introduced herein. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of some embodiments of the present disclosure, and such equivalent constructions may be variously changed, substituted, and replaced herein without departing from the spirit and scope of some embodiments of the present disclosure.

Claims

1. A semiconductor crystal grain, characterized in that: Include: A plurality of first semiconductor devices having a gate length of 3 nanometers and a plurality of first metal gates, wherein more than 99% of the plurality of first semiconductor devices having a gate length of 3 nanometers have a gate height from 10 nanometers to 14 nanometers.

2. The semiconductor crystal grain according to claim 1, characterized in that Further included are a plurality of second semiconductor devices having a gate length of 9 nanometers and a plurality of second metal gates, wherein more than 90% of the second semiconductor devices having a gate length of 9 nanometers have a gate height from 10 nanometers to 13 nanometers.

3. The semiconductor crystal grain according to claim 1, characterized in that Further included are a plurality of third semiconductor devices having a gate length of 55 nanometers and a plurality of third metal gates, wherein more than 90% of the third semiconductor devices having a gate length of 55 nanometers have a gate height ranging from 14 nanometers to 19 nanometers.

4. The semiconductor crystal grain according to claim 1, characterized in that Further included are a plurality of fourth semiconductor devices having a gate length of 135 nanometers and a plurality of fourth metal gates, wherein more than 90% of the fourth semiconductor devices having a gate length of 135 nanometers have a gate height from 16 nanometers to 19 nanometers.

5. The semiconductor crystal grain according to claim 1, characterized in that Less than 1% of the plurality of first semiconductor devices having a gate length of 3 nanometers have a gate height greater than 14 nanometers.

6. The semiconductor crystal grain according to claim 5, characterized in that Less than 0.5% of the plurality of first semiconductor devices having a gate length of 3 nanometers have a gate height less than 10 nanometers.

7. A semiconductor crystal grain, characterized in that: Include: A plurality of first semiconductor devices having a gate length of 3 nanometers; a plurality of second semiconductor devices having a gate length of 9 nanometers; a plurality of third semiconductor devices having a gate length of 55 nanometers; and A plurality of fourth semiconductor devices having a gate length of 135 nanometers, wherein The maximum gate height difference between the plurality of first semiconductor devices and the plurality of second semiconductor devices is 11.2 nanometers; A maximum gate height difference between the plurality of first semiconductor devices and the plurality of third semiconductor devices is 15.4 nanometers; A maximum gate height difference between the plurality of first semiconductor devices and the plurality of fourth semiconductor devices is 14.3 nanometers; A maximum gate height difference between the plurality of second semiconductor devices and the plurality of third semiconductor devices is 13.5 nanometers; A maximum gate height difference between the plurality of second semiconductor devices and the plurality of fourth semiconductor devices is 12.4 nanometers; and A maximum gate height difference between the third plurality of semiconductor devices and the fourth plurality of semiconductor devices is 9.4 nanometers.

8. A semiconductor crystal grain, characterized in that: Include: A plurality of first semiconductor devices having a gate length of 3 nanometers, a minimum gate height of 6.2 nanometers and a maximum gate height of 18.4 nanometers; a plurality of second semiconductor devices having a gate length of 9 nanometers, a minimum gate height of 8.1 nanometers and a maximum gate height of 17.4 nanometers; A plurality of third semiconductor devices having a gate length of 55 nanometers, a minimum gate height of 11.1 nanometers and a maximum gate height of 21.6 nanometers; and The fourth plurality of semiconductor devices having a gate length of 135 nanometers have a minimum gate height of 13.1 nanometers and a maximum gate height of 20.5 nanometers.

9. The semiconductor crystal grain according to claim 8, characterized in that in 99.15% of the plurality of first semiconductor devices having a gate length of 3 nanometers have a gate height ranging from 10 nanometers to 14 nanometers; 94.7% of the plurality of second semiconductor devices having a gate length of 9 nanometers have a gate height ranging from 10 nanometers to 13 nanometers; 93% of the plurality of third semiconductor devices having a gate length of 55 nanometers have a gate height ranging from 14 nanometers to 19 nanometers; and 91.8% of the fourth semiconductor devices having a gate length of 135 nanometers have a gate height ranging from 16 nanometers to 19 nanometers.

10. The semiconductor crystal grain according to claim 8, characterized in that in A maximum gate height difference between the plurality of first semiconductor devices having a gate length of 3 nanometers and the plurality of second semiconductor devices having a gate length of 9 nanometers is 11.2 nanometers; A maximum gate height difference between the plurality of first semiconductor devices having a gate length of 3 nanometers and the plurality of third semiconductor devices having a gate length of 55 nanometers is 15.4 nanometers; A maximum gate height difference between the plurality of first semiconductor devices having a gate length of 3 nanometers and the plurality of fourth semiconductor devices having a gate length of 135 nanometers is 14.3 nanometers; A maximum gate height difference between the plurality of second semiconductor devices having a gate length of 9 nanometers and the plurality of third semiconductor devices having a gate length of 55 nanometers is 13.5 nanometers; A maximum gate height difference between the plurality of second semiconductor devices having a gate length of 9 nanometers and the plurality of fourth semiconductor devices having a gate length of 135 nanometers is 12.4 nanometers; and A maximum gate height difference between the third plurality of semiconductor devices having a gate length of 55 nanometers and the fourth plurality of semiconductor devices having a gate length of 135 nanometers is 9.4 nanometers.

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