Image sensor device

Abstract

The present disclosure describes an image sensor device. In some embodiments, an apparatus comprises: a substrate; a contact pad structure extending from the contact pad region to the black level correction region; the dielectric layer is arranged above the substrate in the black level correction area; and the light blocking structure is arranged on the dielectric layer in the black level correction area and penetrates through the dielectric layer. A first portion of the contact pad structure disposed in the black level correction region is in contact with the light blocking structure, and the light blocking structure is in contact with the substrate.

Description

Technical Field

[0001] Some embodiments of the present disclosure provide image sensor devices. Background Art

[0002] Semiconductor image sensors are used to sense incoming visible or non-visible radiation, such as visible light, infrared light, etc. Complementary metal-oxide-semiconductor (CMOS) image sensors (CIS) and charge-coupled device (CCD) sensors are used in various applications, such as digital still cameras, mobile phones, tablet computers, goggles, etc. These image sensors utilize an array of pixels that absorb (e.g., sense) incoming radiation and convert the incoming radiation into electrical signals. An example of an image sensor is a backside illuminated (BSI) image sensor, which detects radiation from the "back side" of the substrate of the BSI image sensor.

[0003] Improvements have been made to semiconductor image sensors. For example, power consumption can be reduced to achieve smaller size and higher performance. However, reduced power consumption can result in reduced full-well capacity (FWC). Therefore, improved image sensors are needed. Utility Model Content

[0004] Some embodiments of the present disclosure provide an image sensor device, comprising: a substrate, a contact pad structure, a dielectric layer, and a light blocking structure. The contact pad structure extends from a contact pad region to a black level correction region. The dielectric layer is disposed above the substrate in the black level correction region. The light blocking structure is disposed on the dielectric layer in the black level correction region and passes through the dielectric layer, wherein a first portion of the contact pad structure is disposed in the black level correction region and contacts the light blocking structure, and the light blocking structure contacts the board.

[0005] Some embodiments of the present disclosure provide an image sensor device, comprising a substrate, a conductive layer, a dielectric layer, and a metal layer. The conductive layer extends from a contact pad region to a black level correction region. The dielectric layer is disposed above the substrate in the black level correction region. The metal layer is disposed on the dielectric layer in the black level correction region and passes through the dielectric layer, wherein a portion of the conductive layer disposed in the black level correction region contacts the metal layer, and the metal layer contacts the substrate.

[0006] Some embodiments of the present disclosure provide an image sensor device, comprising a substrate, a contact pad structure, a dielectric layer, a buffer oxide layer, and a light blocking structure. The contact pad structure extends from a contact pad region to a black level correction region. The dielectric layer is disposed above the substrate in the black level correction region. The buffer oxide layer is disposed above the dielectric layer. The light blocking structure is disposed on the dielectric layer in the black level correction region and passes through the dielectric layer, wherein a portion of the contact pad structure is disposed in the black level correction region and contacts the light blocking structure, the dielectric layer, and the buffer oxide layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The aspects of this disclosure are as follows: Figure 1 The following detailed description is best understood when read together. It should be noted that, in accordance with standard industry practice, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

[0008] Figures 1 to 13 illustrates a method for forming an image sensor device at various intermediate manufacturing stages according to some embodiments;

[0009] Fig.14 FIG. 1 shows a diagram of applying a negative voltage to the Fig.13 Method for an image sensor device in;

[0010] Fig.15A and Fig. 15B illustrates the effect of applying a negative voltage to ground through a reduced power supply according to some embodiments;

[0011] Fig.16A and Fig. 16B FIG. 1 shows a contact pad structure according to some embodiments. Fig.13 a top view of a portion of an image sensor device above a light blocking structure;

[0012] Fig.17 and Fig.18 illustrates a method for forming an image sensor device at various intermediate manufacturing stages according to an alternative embodiment;

[0013] Fig.19A and Fig.19B The diagram shows a configuration according to some embodiments. Fig.18 a top view of a portion of a contact pad structure above a light blocking structure of an image sensor device;

[0014] Fig. 20A and Fig. 20B FIG. 1 is a top view of a portion of an image sensor device according to some embodiments.

[0015]

Explanation of symbols

[0016] 100: Image sensor device

[0017] 102: Pixel array area

[0018] 104: Black level correction area / BLC area

[0019] 106: Contact pad area

[0020] 108: Alignment mark area

[0021] 110:Substrate

[0022] 110A: front surface

[0023] 110B: Rear surface

[0024] 110T: Groove

[0025] 132: Isolation Structure

[0026] 134: Isolation layer

[0027] 150: Interconnection structure

[0028] 152: Interlayer dielectric layer / ILD layer

[0029] 154: Intermetallic dielectric layer / IMD layer

[0030] 154M: Conductive wiring

[0031] 160: Dielectric layer

[0032] 160I: Isolation Structure

[0033] 160T1: Open

[0034] 160T2: Open

[0035] 160T3: Open

[0036] 162: Charge accumulation layer

[0037] 164: Buffer layer

[0038] 170: Light blocking layer

[0039] 170O1: Opening

[0040] 170O2: Opening

[0041] 172: Light blocking grid

[0042] 174: Light blocking structure

[0043] 174A: Part

[0044] 174B: Part

[0045] 178: Light blocking structure

[0046] 180: Dielectric layer

[0047] 180O: Open

[0048] 180O1: Opening

[0049] 190: Buffer oxide layer

[0050] 190O: Open

[0051] 192: Conductive layer

[0052] 194: Contact pad structure

[0053] 196: Probe

[0054] D1: Distance

[0055] D2: Distance

[0056] X: X-axis

[0057] Y: Y axis

[0058] Z: Z axis DETAILED DESCRIPTION

[0059] The following disclosure provides many different embodiments or examples for implementing the different features of the subject matter provided. Specific examples of components and configurations are described below to simplify the present disclosure. Of course, these components and configurations are only examples and are not intended to be restrictive. For example, in the following description, forming a first feature above or on a second feature may include an embodiment in which the first and second features are formed in direct contact, and may also include an embodiment in which additional features may be formed between the first and second features so that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0060] Additionally, spatially relative terms, such as "below," "beneath," "lower," "above," "on," "up," "top," "upper," and the like may be used herein for ease of description to describe the relationship of one element or feature to another element or feature as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

[0061] An image sensor device and method of forming the same according to some embodiments of the present disclosure are provided, the image sensor device including a contact pad structure extending from a contact pad region to a black level correction (BLC) region. Multiple intermediate manufacturing stages of manufacturing the image sensor device are illustrated. Throughout the various views and illustrative embodiments, like reference numerals are used to designate like elements.

[0062] Figures 1 to 13 A method for forming an image sensor device 100 at various intermediate manufacturing stages according to some embodiments of the present disclosure is illustrated. Some components of the image sensor device 100 are omitted for simplicity. The illustrations are merely illustrative and are not intended to be limiting beyond what is specifically recited in the claims. It should be understood that additional operations may be performed by Figures 1 to 13 The depicted operations are provided before, during, and after, and some of the operations described below may be replaced or eliminated for additional embodiments of the method. The order of operations / processes may be interchangeable.

[0063] like Figure 1 As shown in FIG. 1 , image sensor device 100 may include a pixel array region 102 , a black level correction (BLC) region 104 , a contact pad region 106 , and an alignment mark region 108 . Figures 1 to 13 The dashed line in indicates the approximate boundary between the pixel array region 102 and the alignment mark region 108. Light-sensitive pixels (not shown) are formed in the pixel array region 102. Light-sensitive pixels (not shown) are formed in the BLC region 104 and serve as reference signals for generating reference black level signals, thereby establishing a baseline for the light intensity of the image sensor device 100. The contact pad region 106 may include one or more contact pad structures, through which electrical connections between the image sensor device 100 and external circuits may be established.

[0064] like Figure 1, light-sensitive pixels (not shown) are formed in a substrate 110. The substrate 110 may include, for example, bulk silicon, doped or undoped, or an active layer of a semiconductor-on-insulator (SOI) substrate. Typically, an SOI substrate includes a layer of semiconductor material, such as silicon, formed on an insulator layer. The insulator layer may be, for example, a buried oxide (BOX) layer or a silicon oxide layer. The insulator layer is disposed on a substrate, such as a silicon or glass substrate. Alternatively, the substrate 110 may include another elemental semiconductor, such as germanium; a compound semiconductor, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; an alloy semiconductor, including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or a combination thereof. Other substrates, such as multilayer or gradient substrates, may also be used.

[0065] The photosensitive pixels are formed at the front surface 110A of the substrate 110. The photosensitive pixels may include individual photosensitive regions (not shown), which may be formed, for example, by implanting suitable impurity ions from the front surface 110A of the substrate 110 into the substrate 110. In some embodiments, the impurity ions may be implanted into an epitaxial layer (not shown) within the substrate 110. The photosensitive regions are used to convert optical signals (e.g., photons) into electrical signals, and may be PN junction photodiodes, PNP photodiodes, NPN phototransistors, or the like. For example, the photosensitive regions may include n-type implanted regions formed within a p-type semiconductor layer (e.g., at least a portion of the substrate 110). In such embodiments, the p-type semiconductor layer may isolate and reduce electrical crosstalk between adjacent photoactive regions of the photosensitive pixels. In some embodiments, the photosensitive regions may include p-type implanted regions formed within an n-type semiconductor layer (e.g., at least a portion of the substrate 110).

[0066] Prior to forming the photosensitive region, an isolation structure (not shown) may be formed at the front surface 110A of the substrate 110. In some embodiments, the isolation structure may include a shallow trench isolation (STI) structure. In some embodiments, the STI structure may be formed by patterning the front surface 110A of the substrate 110 to form a trench in the substrate 110, and filling the trench with a suitable dielectric material to form the STI structure. The dielectric material may include silicon oxide. In some embodiments, the substrate 110 is patterned using a suitable optical lithography and etching process. In other embodiments, the isolation structure 132 may include various doped regions formed using a suitable implantation process. In some embodiments, an isolation layer 134 may be formed in the contact pad region 106 and the alignment mark region 108. The isolation layer 134 may be formed simultaneously with the isolation structure. In some other embodiments, the isolation structure may be omitted.

[0067] The interconnect structure 150 may be formed on the front surface 110A of the substrate 110, thereby forming a circuit having light-sensitive pixels. The interconnect structure 150 may include an inter-layer dielectric (ILD) layer 152 and / or an inter-metal dielectric (IMD) layer 154, thereby containing conductive features (e.g., conductive wires and vias including copper, aluminum, tungsten, combinations thereof, and the like) formed using any suitable method, such as damascene, dual damascene, or the like. For example, the interconnect structure 150 includes the following: Figure 1 154M is shown in FIG. 154B . The ILD layer 152 and the IMD layer 154 may include a low-k dielectric material having a k value of, for example, less than 4.0 or even 2.0 disposed between such conductive features. In some embodiments, the ILD layer 152 and the IMD layer 154 may be formed of, for example, phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), fluorosilicate glass (FSG), SiOxCy, spin-on glass, spin-on polymer, silicon-carbon material, compounds thereof, composites thereof, combinations thereof, or the like, the foregoing layers being formed by any suitable method, such as spin coating, chemical vapor deposition (CVD), plasma-enhanced CVD (PECVD), or the like.

[0068] In some embodiments, before forming the interconnect structure 150, in addition to the photosensitive pixels including the photosensitive region, the transfer gate transistor (not shown), and the floating diffusion capacitor (not shown), one or more active and / or passive devices may be formed on the front surface 110A of the substrate 110. The one or more active and / or passive devices may include various N-type metal-oxide semiconductor (NMOS) and / or P-type metal-oxide semiconductor (PMOS) devices, such as transistors, capacitors, resistors, diodes, photodiodes, fuses, and the like. Those skilled in the art will appreciate that the above examples are provided for illustrative purposes only and are not intended to limit the present disclosure in any way. Other circuits may be appropriately used for a given application.

[0069] like Figure 2 As shown in Figure 1 The structure of the substrate 110 is flipped and optionally bonded to a carrier substrate (not shown) such that the front surface 110A of the substrate 110 faces the carrier substrate and the rear surface 110B of the substrate 110 is exposed for further processing. In some embodiments, the carrier substrate may provide mechanical support for processing steps performed on the rear surface 110B of the substrate 110. In some embodiments, the carrier substrate may be formed of silicon or glass and may have no circuits formed thereon. In such embodiments, the carrier substrate provides temporary support and is debonded from the image sensor device 100 after the process steps performed on the rear surface 110B of the substrate 110 are completed. In other embodiments, the carrier substrate may include a semiconductor substrate, one or more active devices (not shown) on the semiconductor substrate, and interconnect structures (not shown) above the one or more active devices. In such embodiments, in addition to providing mechanical support, the carrier substrate may provide additional electrical functionality to the image sensor device 100 according to design requirements.

[0070] After flipping the structure, a thinning process may be performed on the rear surface 110B of the substrate 110 to thin the substrate 110. In some embodiments, the thinning process is used to allow more light to pass from the rear surface 110B of the substrate 110 to the light-sensitive region of the light-sensitive pixel without being absorbed by the substrate 110. The thinning process may be performed by using a suitable technique such as grinding, polishing, and / or chemical etching.

[0071] like Figure 3, the rear surface 110B of the substrate 110 is patterned to form a plurality of trenches 110T in the substrate 110. In some embodiments, the rear surface 110B of the substrate 110 is patterned using a suitable anisotropic wet etching process while using a patterned mask (e.g., a photoresist or a non-photosensitive material such as silicon nitride) as an etching mask. In some embodiments where the substrate 110 is formed of silicon, the anisotropic wet etching may be formed using potassium hydroxide (KOH), ethylenediamine pyrocatechol (EDP), tetramethylammonium hydroxide (TMAH), or the like. The patterned mask is removed after the etching process. In some embodiments where the patterned mask is formed of a photoresist, the patterned mask may be removed using an ashing process followed by a wet cleaning process. In other embodiments where the patterned mask is formed of a non-photosensitive material, the patterned mask may be removed using a suitable etching process.

[0072] like Figure 4 As shown in FIG. 1 , after forming the trench 110T, a dielectric layer 160 is formed on the rear surface 110B of the substrate 110 to fill the trench 110T. The dielectric layer 160 may include a charge accumulation layer 162 conformally formed on the rear surface 110B of the substrate 110, and a buffer layer 164 is formed on the charge accumulation layer 162.

[0073] In some embodiments, the charge accumulation layer 162 may include one or more high-k dielectric materials. For example, the charge accumulation layer 162 may include HfO 2 layer, and HfO 2 Ta above the layer 2 O 5 The charge accumulation layer 162 helps to accumulate negative or positive charges in the substrate 110 to the interface between the charge accumulation layer 162 and the substrate 110 to form electric dipoles, which act as carrier barriers to capture defects such as dangling bonds. The configuration of the charge accumulation layer 162 can reduce the leakage current of the image sensor device.

[0074] In some embodiments, the buffer layer 164 may be formed of silicon oxide, although other suitable dielectric materials may be used. In some embodiments, the buffer layer 164 may be formed using atomic layer deposition (ALD), CVD, PECVD, the like, or a combination thereof. In some embodiments, the charge accumulation layer 162 and the buffer layer 164 are planarized using a grinding process, a chemical mechanical polishing (CMP) process, an etching process, or the like. With this configuration, the charge accumulation layer 162 and the buffer layer 164 form an isolation structure 160I between adjacent photosensitive pixels in multiple portions in the trench 110T of the substrate 110. The isolation structure 160I may prevent electrical crosstalk between photosensitive pixels. The isolation structure 160I may be referred to as a backside deep trench isolation (BDTI) structure. In some other embodiments, the charge accumulation layer 162 may be omitted.

[0075] like Figure 5 , the dielectric layer 160 is patterned to form one or more openings 160T1 and openings 160T2, which expose the rear surface 110B of the substrate 110 in the BLC region 104 and the alignment mark region 108, respectively. In some embodiments, the dielectric layer 160 can be patterned using suitable optical lithography and etching processes. For example, a photoresist is coated over the dielectric layer 160, and then patterned using optical lithography techniques to expose portions of the dielectric layer 160 in the BLC region 104 and the alignment mark region 108. Subsequently, an etching process is performed to remove the exposed portions of the dielectric layer 160, thereby exposing the underlying substrate 110.

[0076] like Figure 6As shown in , the light blocking layer 170 is formed above the dielectric layer 160. The light blocking layer 170 may be a metal layer. In some embodiments, the light blocking layer 170 is made of a reflective metal material or a light absorbing material. For example, the light blocking layer 170 may include Cu, Au, Ag, Al, Ni, W, alloys thereof, or the like, and may be formed using physical vapor deposition (PVD), electroplating, or the like. In some embodiments, before forming the light blocking layer 170, a barrier / adhesion layer (not shown) may be conformally formed above the dielectric layer 160. The barrier / adhesion layer may include titanium, titanium nitride, tantalum, tantalum nitride, or a multilayer thereof, and may be formed using PVD, CVD, metal-organic chemical vapor deposition (MOCVD), plasma enhanced CVD (PECVD), atomic layer deposition (ALD), electroplating, and / or the like. The light blocking layer 170 is made of a conductive material. In some embodiments, the light blocking layer 170 in the BLC region 104 may include a groove corresponding to the opening 160T1. The groove may be formed in the top surface of the light blocking layer 170.

[0077] like Figure 7 As shown in FIG. 1 , the light blocking layer 170 ( Figure 6 ) is patterned into a light blocking grid 172 in the pixel array area 102, a light blocking structure 174 in the BLC area 104, and a light blocking structure 178 in the alignment mark area 108. The patterning process may include suitable optical lithography and etching processes. For example, a patterned mask (e.g., a photoresist) is formed over the light blocking layer 170 and the exposed portion of the light blocking layer 170 in the pixel array area 102 and a portion of the light blocking layer 170 in the contact pad area 106. Subsequently, an etching process is performed to remove the exposed portion of the light blocking layer 170. The etching process may include wet etching, dry etching, or a combination thereof. For example, the etching process may include using a process such as Cl 2 , HBr, CF 4 or the like. The etching process is performed until the dielectric layer 160 is exposed. In some embodiments, the exposed portion of the dielectric layer 160 may be consumed by the etching process and thus recessed below the lateral interface between the light blocking layer 170 and the dielectric layer 160. Through the patterning process, the dielectric layer 160 is exposed through the opening 170O1 and the opening 170O2 in the light blocking layer 170. In some embodiments, during the etching process, the BLC region 104 and the alignment mark region 108 are protected from being etched, and the layers therein are not etched.

[0078] The light blocking structure 174 in the BLC region 104 blocks light that would otherwise be received by the reference light-sensitive pixel. The light blocking structure 174 can be electrically coupled to the substrate 110, for example, the light blocking structure 174 is in contact with the back surface 110B of the substrate 110. Such electrical coupling provides grounding. The grounding can release unwanted charges in the BLC region 104. In some embodiments, the light blocking structure 174 can be a ring-shaped structure in a top view that laterally surrounds or encloses the pixel array region 102.

[0079] The light blocking grid 172 has openings 170O1 aligned with individual light-sensitive pixels. For example, in some embodiments, as viewed from the top, the walls of the light blocking grid 172 can enclose each active light-sensitive pixel. Through configuration, the light blocking grid 172 prevents optical crosstalk between adjacent active light-sensitive pixels.

[0080] The light blocking structure 178 located in the alignment mark region 108 may be referred to as an alignment mark (e.g., a scribe lane primary mark (SPM) or an overlay (OVL) mark). In some embodiments, the light blocking structure 178 may include a groove corresponding to the opening 160T2. For example, the groove formed in the light blocking structure 178 allows alignment correction to detect mismatch during the optical lithography process. In an alternative embodiment, the entirety of the light blocking layer 170 in the alignment mark region 108 is removed by the patterning process.

[0081] like Figure 8 As shown in FIG. 1 , the dielectric layer 180 is formed over the light blocking grid 172, the light blocking structures 174, 178, and the dielectric layer 160. In some embodiments, the dielectric layer 180 may be formed using the above-described Figure 4 The dielectric layer 180 is formed by materials and methods similar to those described for the buffer layer 164, and the description is not repeated herein. In some embodiments, the dielectric layer 180 and the buffer layer 164 may be formed of the same material. In other embodiments, the dielectric layer 180 and the buffer layer 164 may be formed of different materials. Subsequently, the dielectric layer 180 is planarized using a grinding process, a chemical mechanical polishing (CMP) process, an etching process, or the like.

[0082] like Fig. 9 As shown in FIG. 1 , an etching process is performed to remove a portion of the dielectric layer 180, a portion of the dielectric layer 160, and a portion of the substrate 110 in the contact pad region 106, thereby forming an opening 180O in the contact pad region 106. The isolation layer 134 is exposed in the opening 180O, as shown in FIG. Fig. 9Subsequently, a buffer oxide layer 190 is formed over the remaining portions of the dielectric layer 180 in the pixel array region 102, the black level correction region 104, the contact pad region 106, and the alignment mark region 108, and extends over the exposed portion of the isolation layer 134 into the opening 180O, as shown in FIG. Fig.10 shown in.

[0083] like Fig.11 , the buffer oxide layer 190 and the underlying dielectric material (e.g., isolation layer 134 and ILD layer 152) in the contact pad region 106 are patterned to form openings 180O1 to expose the conductive wires 154M of the interconnect structure 150. The buffer oxide layer 190 and the underlying dielectric layer 180 in the BLC region 104 are also patterned to form openings 190O to expose the light blocking structure 174. The patterning of the materials in the two regions (black level correction region 104, contact pad region 106) can be performed simultaneously.

[0084] Subsequently, a conductive layer 192 is formed on the buffer oxide layer 190 in the pixel array region 102, the alignment mark region 108, in the opening 190O in the BLC region 104, and in the openings 180O, 180O1 in the contact pad region 106, as shown in FIG. Fig.12 As shown in Fig.13 , the conductive layer 192 is patterned to form a contact pad structure 194. In some embodiments, portions of the conductive layer 192 disposed in the pixel array region 102 and the alignment mark region 108 are removed, and the remaining conductive layer 192 or the contact pad structure 194 is disposed in the BLC region 104 and the contact pad region 106. As described above, the light blocking structure 174 contacts the rear surface 110B of the substrate 110, and such electrical coupling provides a ground that can release unwanted charges in the BLC region 104. Fig.13 , the portion of the contact pad structure 194 disposed in the BLC region 104 contacts the light blocking structure 174. In some embodiments, the portion of the contact pad structure 194 disposed in the BLC region 104 fills a recess formed in the top surface of the light blocking structure 174. The portion of the contact pad structure 194 disposed in the BLC region 104 contacts the buffer oxide layer 190 and the dielectric layer 180. The portion of the contact pad structure 194 located in the contact pad region 106 is electrically coupled to the exposed conductive wire 154M and is electrically isolated from the sidewall of the substrate 110 by the buffer oxide layer 190. The portion of the contact pad structure 194 located in the contact pad region 106 is used to form an electrical connection, such as a wire bond (not shown), to electrically couple to a circuit and a light-sensitive pixel. The portion of the contact pad structure 194 located in the contact pad region 106 can be coupled to the light-sensitive pixel via the interconnect structure 150.

[0085] Subsequent processes may be performed to form the image sensor device 100. For example, a color filter layer (not shown) may be formed above the dielectric layer 180 in the pixel array region 102. In some embodiments, the color filter layer includes a plurality of color filters aligned with individual active light-sensitive pixels. The color filters may be used to allow light of certain wavelengths to pass through while reflecting other wavelengths, thereby allowing the image sensor device 100 to determine the color of the light received by the active light-sensitive pixels. For example, the color filters may be red, green, and blue filters as used in a Bayer pattern. Other combinations such as cyan, yellow, and magenta may also be used. The number of different colors of the color filters may also vary. The color filters may include a polymer or resin such as polymethyl-methacrylate (PMMA), polyglycidyl-methacrylate (PGMA), or the like including a coloring pigment.

[0086] The portion of the contact pad structure 194 disposed in the BLC region 104 provides a location for applying a negative voltage, such as from about 0 volts (V) to -0.5 V to ground. Fig.14 As shown in FIG. 1 , during operation of image sensor device 100 with a reduced power supply, such as from 3.0 V to 2.5 V, probe 196 is inserted into image sensor device 100 and contacts a portion of contact pad structure 194 disposed in BLC region 104, and a negative voltage applied to ground by probe 196 can increase FWC by increasing the energy barrier when transfer gate (TG) is turned off. Fig.15A and Fig. 15B The figure shows the effect of applying a -0.5v voltage to ground through a reduced power supply. Fig.15A and Fig. 15B As shown in , when -0.5v voltage is applied to ground, the potential is increased, which means that FWC is increased.

[0087] Replay Fig.14 In some embodiments, the light-blocking structure 174 includes a portion 174A extending through the dielectric layer 160 and in contact with the substrate 110. In some embodiments, the light-blocking structure 174 includes a plurality of portions 174A in contact with the substrate 110. Fig.16A and Fig. 16B As shown in FIG. 1 , portions 174A of the light blocking structures 174 may be arranged in a matrix, and these portions 174A are shown in dashed lines because they are located below the contact pad structures 194. The remaining portions of the light blocking structures 174 are omitted for clarity. In some embodiments, each portion 174A has a diameter ranging from about 1 micron to about 10 microns. Fig.16AAs shown in FIG. 1 , the distance D1 between adjacent portions 174A in the X direction ranges from about 0.5 micrometers to about 20 micrometers, and the distance D2 between adjacent portions 174A in the Y direction ranges from about 1 micrometer to about 10 micrometers. In some embodiments, as Fig.16A , the portion of the contact pad structure 194 located in the BLC region 104 may have an elliptical or circular shape and may surround the plurality of portions 174A. In some embodiments, the portion of the contact pad structure 194 located in the BLC region 104 may have a rectangular shape and may surround the plurality of portions 174A. The portions 174A may have any suitable shape and be arranged in any suitable pattern. The portion of the contact pad structure 194 located in the BLC region 104 may have any suitable shape.

[0088] Fig.17 and Fig.18 A method for forming image sensor device 100 is shown at various intermediate manufacturing stages according to an alternative embodiment. Fig.17 As shown in FIG. 1 , instead of the plurality of openings 160T1 , one or more larger openings 160T3 are formed in the dielectric layer 160 . Fig.18 As shown in FIG. 1 , light blocking structure 174 is formed in and above dielectric layer 160 in BLC region 104. Light blocking structure 174 includes one or more portions 174B that are substantially larger than portion 174A. Other portions of image sensor device 100 may be similar to those of FIG. Fig.13 The image sensor device 100 shown in FIG. 1 is substantially the same as that shown in FIG. Fig.17 As shown in FIG. 1 , portion 174B contacts substrate 110 . Light-blocking structure 174 includes a recess in the top surface, and the portion of contact pad structure 194 located in BLC region 104 fills the recess in the top surface of light-blocking structure 174 .

[0089] Fig.19A and Fig.19B The contact pad structure 194 is shown disposed at Fig.18 FIG. 1 is a top view of a portion of the image sensor device 100 above the light blocking structure 174. Fig.19A and Fig.19B As shown in FIG. 1 , a portion 174B of the light blocking structure 174 is shown in dashed lines because the portion 174B is located below the contact pad structure 194. For clarity, the remaining portion of the light blocking structure 174 is omitted. Fig.19A As shown in FIG. 1 , in some embodiments, portion 174B has an elliptical or circular shape, and the portion of contact pad structure 194 located in BLC region 104 has a shape similar to portion 174B. The size of the portion of contact pad structure 194 may be substantially larger than the size of portion 174B. Fig.19B, in some embodiments, portion 174B has a rectangular shape, and the portion of contact pad structure 194 located in BLC region 104 has a shape similar to portion 174B. The size of the portion of contact pad structure 194 may be substantially larger than the size of portion 174B. The shapes of the portion of contact pad structure 194 located in BLC region 104 and portion 174B of light blocking structure 174 may be substantially the same, such as Fig.19A and Fig.19B In some embodiments, the shapes of the portion of the contact pad structure 194 located in the BLC region 104 and the portion 174B of the light-blocking structure 174 are substantially different.

[0090] Fig. 20A and Fig. 20B FIG. 1 is a top view of a portion of an image sensor device 100 according to some embodiments. Fig. 20A and Fig. 20B As shown in FIG. 1 , the image sensor device 100 includes a pixel array region 102, the pixel array region 102 is surrounded by a BLC region 104, and the BLC region 104 is surrounded by a contact pad region 106. Fig. 20A , portions 174A of the light blocking structures 174 are located in the BLC region 104. The remaining portions of the light blocking structures 174 are omitted for clarity. A plurality of contact pad structures 194 are disposed over portions 174A of the light blocking structures 174. Each contact pad structure 194 is disposed in both the BLC region 104 and the contact pad region 106. In some embodiments, each contact pad structure 194 is a continuous layer extending from the contact pad region 106 into the BLC region 104. The shape of the contact pad structures 194 may vary, such as Fig. 20A and Fig. 20B In some embodiments, the shape of the portion of the contact pad structure 194 in the contact pad region 106 is the same as the shape of the portion of the contact pad structure 194 in the BLC region 104, such as Fig. 20A and Fig. 20B In some embodiments, the shape of the portion of the contact pad structure 194 in the contact pad region 106 is different from the shape of the portion of the contact pad structure 194 in the BLC region 104. In some embodiments, a plurality of contact pad structures 194 having different shapes are formed in the BLC region 104 and the contact pad region 106, such as Fig. 20A and Fig. 20B In some embodiments, a plurality of contact pad structures 194 having the same shape are formed in the BLC region 104 and the contact pad region 106 .

[0091] like Fig. 20B, in some embodiments, the light blocking structure 174 includes both portions 174A and 174B. For example, in the area of ​​the BLC region 104 where the contact pad structure 194 is located, the portion 174B is formed so as to increase the contact area to the substrate 110. In other areas of the BLC region 104 where the contact pad structure 194 is not formed, the portion 174A is formed.

[0092] The present disclosure provides an image sensor device 100 and a method of forming the image sensor device 100. In some embodiments, the image sensor device 100 includes a contact pad structure 194 extending from the contact pad region 106 to the BLC region 104. The portion of the contact pad structure 194 in the BLC region 104 is electrically connected to the substrate 110. Some embodiments can achieve advantages. For example, during operation, a probe 196 is inserted into the image sensor device 100 and contacts the portion of the contact pad structure 194 disposed in the BLC region 104, and a negative voltage applied to ground by the probe 196 can increase the FWC by increasing the energy barrier when the transfer gate (TG) is turned off.

[0093] One embodiment is an image sensor device. The device includes: a substrate; a contact pad structure extending from a contact pad region to a black level correction region; a dielectric layer disposed above the substrate in the black level correction region; and a light blocking structure disposed on and through the dielectric layer in the black level correction region. A first portion of the contact pad structure is disposed in a first portion of the black level correction region that contacts the light blocking structure, and the light blocking structure contacts the substrate.

[0094] In some embodiments, the light blocking structure includes a portion extending through the dielectric layer. In some embodiments, the size of the first portion of the contact pad structure is substantially larger than the size of the portion of the light blocking structure. In some embodiments, the second portion of the contact pad structure disposed in the contact pad area is electrically isolated from the substrate. In some embodiments, the image sensor device further includes a buffer oxide layer disposed between the sidewall of the substrate and the second portion of the contact pad structure. In some embodiments, a plurality of grooves are formed on the top surface of the light blocking structure, and the first portion of the contact pad structure fills the grooves. In some embodiments, a recess is formed on the top surface of the light blocking structure, and the first portion of the contact pad structure fills the recess. In some embodiments, multiple portions of the dielectric layer form multiple isolation structures in the substrate in the pixel array area.

[0095] Another embodiment is a method of forming an image sensor device. The method includes: forming one or more grooves in a pixel array region of a substrate; depositing a first dielectric layer over the substrate and in the one or more grooves; forming one or more openings in the first dielectric layer; depositing a light blocking layer over the first dielectric layer and in the one or more openings; and patterning the light blocking layer to form a light blocking structure in a black level correction region. The light blocking structure contacts the substrate. The method further includes: forming a first opening in the first dielectric layer and in the substrate in a contact pad region; depositing a conductive layer over the substrate and in the first opening; and patterning the conductive layer to form a contact pad structure. The contact pad structure extends from the contact pad region to the black level correction region.

[0096] In some embodiments, the method further includes: before the step of forming one or more grooves in the pixel array area of ​​the substrate, forming an interconnect structure on the substrate and flipping the substrate. In some embodiments, the step of patterning the light blocking layer removes multiple portions of the first dielectric layer. In some embodiments, the method further includes: depositing a second dielectric layer over the first dielectric layer after the step of patterning the light blocking layer. In some embodiments, the first opening is formed in the second dielectric layer. In some embodiments, the method further includes: forming a buffer oxide layer over the substrate and in the first opening before the step of depositing the conductive layer. In some embodiments, the method further includes: forming a second opening in the buffer oxide layer and the second dielectric layer to expose the light blocking structure in the black level correction area; and forming a third opening in the buffer oxide layer in the contact pad area, wherein the conductive layer is deposited in the second opening and the third opening.

[0097] Another embodiment is a method of forming an image sensor device. The method includes: depositing a first dielectric layer over a substrate, and the first dielectric layer is deposited in a pixel array region, a black level correction region, a contact pad region, and an alignment mark region. The method further includes: forming a plurality of openings in the first dielectric layer in the black level correction region and the alignment mark region; depositing a light blocking layer over the first dielectric layer and in the openings; removing a plurality of portions of the light blocking layer in the pixel array region and the contact pad region to form a light blocking grid in the pixel array region and a plurality of light blocking structures in the black level correction region and the alignment mark region; and depositing a conductive layer in the pixel array region, the black level correction region, the contact pad region, and the alignment mark region. The conductive layer contacts the light blocking structure in the black level correction region. The method further includes removing a plurality of portions of the conductive layer in the pixel array region and the alignment mark region to form a contact pad structure, the contact pad structure extending from the contact pad region to the black level correction region.

[0098] In some embodiments, the method further includes: depositing a second dielectric layer on the light blocking grid, the light blocking structure, and the first dielectric layer before the step of depositing the conductive layer, and the second dielectric layer is in contact with the light blocking grid, the light blocking structure, and the first dielectric layer. In some embodiments, the method further includes: removing a portion of the second dielectric layer, a portion of the first dielectric layer, and a portion of the substrate in the contact pad area to expose the isolation layer. In some embodiments, the method further includes: depositing a buffer oxide layer in the pixel array area, the black level correction area, the contact pad area, and the alignment mark area, wherein the buffer oxide layer is in contact with the isolation layer. In some embodiments, the method further includes: removing a portion of the buffer oxide layer and a portion of the second dielectric layer in the black level correction area to expose the light blocking structure in the black level correction area.

[0099] Another embodiment provides an image sensor device, comprising a substrate, a conductive layer, a dielectric layer, and a metal layer. The conductive layer extends from a contact pad region to a black level correction region. The dielectric layer is disposed above the substrate in the black level correction region. The metal layer is disposed on the dielectric layer in the black level correction region and passes through the dielectric layer, wherein a portion of the conductive layer disposed in the black level correction region contacts the metal layer, and the metal layer contacts the substrate.

[0100] Another embodiment provides an image sensor device, comprising a substrate, a contact pad structure, a dielectric layer, a buffer oxide layer, and a light blocking structure. The contact pad structure extends from a contact pad region to a black level correction region. The dielectric layer is disposed above the substrate in the black level correction region. The buffer oxide layer is disposed above the dielectric layer. The light blocking structure is disposed on the dielectric layer in the black level correction region and passes through the dielectric layer, wherein a portion of the contact pad structure is disposed in the black level correction region and contacts the light blocking structure, the dielectric layer, and the buffer oxide layer.

[0101] The foregoing summarizes the features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art will appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for implementing the same purposes and / or achieving the same advantages of the embodiments introduced herein. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and such equivalent constructions may be variously modified, substituted, and replaced herein without departing from the spirit and scope of the present disclosure.

Claims

1. An image sensor device, characterized in that: Include: a substrate; a contact pad structure extending from a contact pad region to a black level correction region; A dielectric layer disposed above the substrate in the black level correction area; and A light blocking structure is disposed on the dielectric layer in the black level correction area and passes through the dielectric layer, wherein a first portion of the contact pad structure is disposed in the black level correction area and contacts the light blocking structure, and the light blocking structure contacts the substrate.

2. The image sensor device according to claim 1, wherein: The light blocking structure includes a portion extending through the dielectric layer.

3. The image sensor device according to claim 2, wherein: A size of the first portion of the contact pad structure is substantially larger than a size of the portion of the light blocking structure.

4. The image sensor device according to claim 2, wherein: A second portion of the contact pad structure disposed in the contact pad region is electrically isolated from the substrate.

5. The image sensor device according to claim 4, wherein: The invention further includes a buffer oxide layer disposed between a sidewall of the substrate and the second portion of the contact pad structure.

6. The image sensor device according to any one of claims 1 to 5, characterized in that: A plurality of grooves are formed on a top surface of the light blocking structure, and the first portion of the contact pad structure fills the plurality of grooves.

7. The image sensor device according to any one of claims 1 to 5, characterized in that: A recess is formed on a top surface of the light blocking structure, and the first portion of the contact pad structure fills the recess.

8. The image sensor device according to any one of claims 1 to 5, characterized in that: Parts of the dielectric layer form a plurality of isolation structures in the substrate in a pixel array region.

9. An image sensor device, characterized in that: Include: a substrate; a conductive layer extending from a contact pad region to a black level correction region; A dielectric layer disposed above the substrate in the black level correction area; and A metal layer is disposed on the dielectric layer in the black level correction area and passes through the dielectric layer, wherein a portion of the conductive layer disposed in the black level correction area contacts the metal layer, and the metal layer contacts the substrate.

10. An image sensor device, characterized in that: Include: a substrate; a contact pad structure extending from a contact pad region to a black level correction region; a dielectric layer disposed above the substrate in the black level correction area; a buffer oxide layer disposed above the dielectric layer; and A light blocking structure is disposed on the dielectric layer in the black level correction area and passes through the dielectric layer, wherein a portion of the contact pad structure is disposed in the black level correction area and contacts the light blocking structure, the dielectric layer and the buffer oxide layer.

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