Digital channel delay determination device and test equipment
By designing a digital channel delay determination device, the processor, sending module, receiving module and connector determine and align the delay time of different signal paths, the problem of signal path delay misalignment in semiconductor automation tests is solved, and the accuracy of the clock edge flip of the test machine is improved and the test efficiency is improved.
Patent Information
- Application Number
- CN202420672635.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-04-02
- Publication Date
- 2025-04-15
- Estimated Expiration
- 2034-04-02
AI Technical Summary
In semiconductor automation testing, there is a problem of delay time misalignment in different signal paths of digital output channels, which affects the accuracy of clock edge flips when the tester pattern runs.
A digital channel delay determination device is designed, including a processor, a transmitting module, a receiving module and a connector, through these components, the delay time of different signal paths is determined, and the alignment of the signal paths is achieved through time difference compensation.
The delay time alignment of multiple signal paths is achieved, ensuring the accuracy of clock edge flips when the tester pattern runs, and improving testing efficiency and accuracy.
Smart Images
Figure CN222762234U_ABST
Abstract
Description
Technical Field
[0001] The present application belongs to the field of chip testing technology, and specifically relates to a digital channel delay determination device and testing equipment. Background Art
[0002] Semiconductor automated testing refers to the use of automatic test equipment (ATE) to test various parameters of the device under test (DUT) to eliminate defective products and control the factory quality of semiconductor devices.
[0003] The digital output channels of semiconductor automated test equipment usually have multiple configurable AC parameters, where the action bit per cycle represents the number of clock edge flips of the output waveform in one cycle, which improves the flexibility of the tester's output waveform. To achieve this function, it is necessary to ensure that there are multiple signal paths for controlling pattern (test vector) generation in the tester's TimingGenerator module and to synthesize the final pattern output signal using combinational logic at the end. This means that for the same output waveform, there are multiple unequal delay times from signal trigger to output to the terminal. In order to ensure the accuracy of clock edge flips when the tester pattern is running, the delay times of these different paths need to be aligned with each other. Summary of the invention
[0004] The purpose of the present application is to provide a digital channel delay determination device and a test device to determine the delay time of different paths; and then align the delay time of these different paths to ensure the accuracy of clock edge flipping when the test machine pattern is running.
[0005] According to a first aspect of an embodiment of the present application, a digital channel delay determination device is provided, which may include: a processor, a sending module, a receiving module and a connector; the processor is connected to the input end of the sending module through a digital channel, the output end of the sending module is connected to the first pin of the connector, the first pin of the connector is also connected to the input end of the receiving module, and the output end of the receiving module is connected to the processor; the digital channel includes at least two signal paths.
[0006] In some optional embodiments of the present application, the processor includes a driving unit, a logic unit and a time measurement unit; the driving unit is connected to the input end of the logic unit through a digital channel, the output end of the logic unit is connected to the input end of the sending module, and the output end of the receiving module is connected to the time measurement unit.
[0007] In some optional embodiments of the present application, the digital channel includes a first signal path and a second signal path; one end of the first signal path and the second signal path is connected to the driving unit, and the other end of the first signal path and the second signal path is connected to the input end of the logic unit.
[0008] In some optional embodiments of the present application, the sending module is connected to the receiving module, and a switch is provided between the connection point between the sending module and the receiving module and the connector, and the switch is used to connect and disconnect the connection point and the connector.
[0009] In some optional embodiments of the present application, the digital channel delay determination device further includes: an external module; the connector includes a first pin and a second pin; and the external module is connected to the second pin.
[0010] In some optional embodiments of the present application, the external module includes: an external cable and / or a board.
[0011] In some optional embodiments of the present application, the digital channel delay determination device further includes: a storage module; the storage module is connected to the time measurement unit and is used to store time measurement data.
[0012] In some optional embodiments of the present application, the processor includes a delay unit; the delay unit is arranged in the digital channel, and is used to delay the signal in the digital channel.
[0013] In some optional embodiments of the present application, there are multiple delay units; the multiple delay units are all arranged in the digital channel, and are used to delay the signal in the digital channel with multiple delay values.
[0014] According to a second aspect of an embodiment of the present application, a testing device is provided, which may include: a digital channel delay determination device as shown in any one of the embodiments of the first aspect.
[0015] The above technical solution of the present application has the following beneficial technical effects:
[0016] The device of the embodiment of the present application adopts an architecture of a processor, a sending module, a receiving module and a connector. During testing, the time difference of different signal paths in a digital channel can be determined, and the signal path can be compensated according to the time difference to achieve alignment of multiple signal paths, thereby ensuring the accuracy of clock edge flipping when the test machine pattern is running. BRIEF DESCRIPTION OF THE DRAWINGS
[0017] Figure 1 is a structural diagram of a digital channel delay determination device in an exemplary embodiment of the present application;
[0018] Figure 2 is a structural schematic diagram of a digital channel delay determination device in another exemplary embodiment of the present application;
[0019] Figure 3 is a structural schematic diagram of a digital channel delay determination device in another exemplary embodiment of the present application;
[0020] Figure 4 It is a structural diagram of a digital channel delay determination device in yet another exemplary embodiment of the present application. DETAILED DESCRIPTION
[0021] In order to make the purpose, technical solutions and advantages of the present application clearer, the present application is further described in detail below in conjunction with specific implementations and with reference to the accompanying drawings. It should be understood that these descriptions are only exemplary and are not intended to limit the scope of the present application. In addition, in the following description, the description of known structures and technologies is omitted to avoid unnecessary confusion of the concepts of the present application.
[0022] The accompanying drawings show schematic diagrams of layer structures according to embodiments of the present application. These figures are not drawn to scale, and some details are magnified and some details may be omitted for the purpose of clarity. The shapes of various regions and layers shown in the figures and the relative sizes and positional relationships therebetween are only exemplary, and may deviate in practice due to manufacturing tolerances or technical limitations, and those skilled in the art may additionally design regions / layers with different shapes, sizes, and relative positions according to actual needs.
[0023] Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without creative work are within the scope of protection of the present application.
[0024] In the description of the present application, it should be noted that the terms "first", "second" and "third" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance.
[0025] In addition, the technical features involved in the different embodiments of the present application described below can be combined with each other as long as they do not conflict with each other.
[0026] The digital channel delay determination device and the test equipment provided in the embodiments of the present application are described in detail below with reference to the accompanying drawings through specific embodiments and their application scenarios.
[0027] like Figure 1As shown, in a first aspect of an embodiment of the present application, a digital channel delay determination device is provided, which may include: a processor, a sending module, a receiving module and a connector; the processor is connected to the input end of the sending module through a digital channel, the output end of the sending module is connected to the first pin of the connector, the first pin of the connector is also connected to the input end of the receiving module, and the output end of the receiving module is connected to the processor; the digital channel includes at least two signal paths.
[0028] In order to ensure the accuracy of the clock edge flipping when the tester pattern is running, the delay time of different signal paths in the digital channel needs to be aligned with each other. The device of this embodiment adopts the architecture of the processor, the sending module, the receiving module and the connector, and can determine the time difference of different signal paths in the digital channel during the test, and then compensate the signal path delay according to the time difference, so as to achieve the delay time alignment of multiple signal paths and ensure the accuracy of the clock edge flipping when the tester pattern is running.
[0029] It should be noted that in this embodiment, both the sending module and the receiving module are connected to the first pin of the connector. A specific implementation method may be that the sending module is first connected to the receiving module and then connected to the first pin of the connector; or the sending module and the receiving module are respectively connected to the first pin of the connector. In short, the signal sent by the sending module can be returned to the receiving module through the open-circuit connector.
[0030] In some embodiments, the processor includes a driving unit, a logic unit and a time measurement unit; the driving unit is connected to the input end of the logic unit through a digital channel, the output end of the logic unit is connected to the input end of the sending module, and the output end of the receiving module is connected to the time measurement unit.
[0031] In this embodiment, the driving unit can select a signal path in the digital channel to transmit the pulse signal through the logic unit and the sending module, so that the pulse signal is transmitted to the end of the connector and reflected to the receiving module, and at the same time the pulse signal is sent, the time measurement unit of the processor starts measuring, and stops measuring when the receiving module receives the pulse signal. At this time, the time measurement unit can measure the transmission time of the pulse signal in the signal path. The signal path transmission time can be obtained based on the cycle count from the pulse signal sent by the driving unit to the receiving module. Then, by replacing other signal paths and repeating the operation, the transmission time of each signal path can be obtained. Finally, the transmission time is subtracted to obtain the difference in delay between the signal paths.
[0032] In addition, when using the full-channel parallel calibration method, the calibration process of this embodiment only needs to calibrate the time of one digital channel, that is, the signal path of each digital channel is measured once respectively. Even considering the influence of system jitter, when a single signal path triggers the pulse signal hundreds of times, the overall test time is still very short, which can be less than 5 minutes. This architecture has high calibration efficiency, and each digital channel can be calibrated using the resources of this channel to achieve parallel calibration. For tens of thousands of digital channels in the test machine, the test efficiency of the device of this embodiment is significantly improved compared with the method of measuring with an oscilloscope.
[0033] like Figure 2 As shown, in some embodiments, the digital channel includes a first signal path and a second signal path; one end of the first signal path and the second signal path is connected to the driving unit, and the other end of the first signal path and the second signal path is connected to the input end of the logic unit.
[0034] This embodiment takes two signal paths as an example. The driving unit can first select the first wave signal path to trigger the pulse signal through the logic unit and the sending module for output. The pulse signal is transmitted to the end of the connector through the path and reflected to the receiving module, so that the time measurement unit of the processor receives the pulse signal. At this time, the time measurement unit can measure the transmission time of the pulse signal in this signal path as T. A1 , and then change the second signal path and repeat the operation to obtain the transmission time of the second signal path as T A2 , and finally the transmission time is subtracted, that is, T A2 -T A1 , so that the time delay between the first signal path and the second signal path can be obtained.
[0035] In some embodiments, the sending module is connected to the receiving module, and the connection point between the sending module and the receiving module is connected to the connector. The driving unit sends a pulse signal to the sending module. Since the sending module is connected to the receiving module, and the connection point between the sending module and the receiving module is connected to the connector, the pulse signal output by the sending module is divided to the connector and the receiving module, and part of the pulse signal directly passes through the receiving module to the time measurement unit. Therefore, the time measurement unit measures the time T of the pulse signal from the driving unit to the receiving module through the logic unit and the sending module. B1 The other part of the pulse signal is reflected to the receiving module through the open end of the connector. The time measurement unit measures the time T from the driving unit to the logic unit, the sending module, the connector and then to the receiving module. B2 , so that the time T of the pulse signal from the output end of the sending module to the connector can be calculated B3 =(T B2 -T B1 ) / 2.
[0036] A switch may be provided between the connection point between the sending module and the receiving module and the connector, and the switch is used to control the on-off between the sending module and the connector. A person skilled in the art can understand that the switch disconnects the connection point from the connector, that is, the connection line between the connection point and the connector is disconnected, and the end of the connection line has the same function as the open end of the connector, which is to reflect the pulse signal back to the receiving module.
[0037] like Figure 3 As shown, in some embodiments, the digital channel delay determination device further includes: an external module; the connector includes a first pin and a second pin; and the external module is connected to the second pin.
[0038] If the number of connections outside the connector increases, changes in the system's external connections can be quickly calculated by comparison.
[0039] In this embodiment, the sending module is connected to the receiving module, the connection point between the sending module and the receiving module is connected to the connector, and the time measurement unit measures the time T of the driving unit passing through the logic unit, the sending module, the connector and then the receiving module. B2 The time measurement unit measures the time T of the pulse signal from the drive unit through the logic unit, the sending module, the connector to the external module, and then reflected by the external module to the receiving module. B4 , so the delay from the connector to the external module is T B5 =(T B4 -T B2 ) / 2. By combining the above two test data (T B4、 T B2 ) can be compared before and after to obtain the length from the connector to the external module, and then the delay can be compensated in the tester to improve the timing test accuracy of the tester.
[0040] Of course, those skilled in the art can know that, for the sending module and the receiving module respectively connected to the first pin of the connector, the connector is connected to the external module, and the time delay between the connector and the external module can also be measured by the time measurement unit. The calculation principle is similar. The time measurement unit measures the time for the pulse signal from the driving unit through the logic unit, the sending module, the connector to the external module, and then reflected from the external module to the receiving module, and the time measurement unit measures the time for the pulse signal from the driving unit through the logic unit, the sending module, the connector to the receiving module. No further description is given here. In some embodiments, the external module includes: an external cable and / or a board.
[0041] This embodiment provides that the external module can be an external cable, a board plugged into a connector, or a board connected to an external cable in actual situations. In these cases, the delay can be measured by the device architecture of this embodiment.
[0042] In some embodiments, the digital channel delay determination device further includes: a storage module; the storage module is connected to the time measurement unit and is used to store time measurement data.
[0043] When measuring the delay, the structure of this embodiment can store the test data of two times in the storage module for before-and-after comparison, so that the changes in the external connection of the system can be clearly compared, and then the cable length data or the board routing length can be obtained and compensated to the tester, thereby improving the timing test accuracy of the tester.
[0044] like Figure 4 As shown, in some embodiments, the processor includes a delay unit; the delay unit is arranged in the digital channel and is used to delay the signal in the digital channel.
[0045] In this embodiment, the delay unit is distributed in the path inside the digital channel to compensate the calibration data. In the delay value test process of the delay unit, we first use the processor to measure the signal return time in the channel in the initial state of the system and record it as the initial value T C1 After adding the delay unit, record the signal return time T obtained at this time C2 , then the delay value of the delay unit Tap=T C2 -T C1 .
[0046] In some embodiments, there are multiple delay units; the multiple delay units are all arranged in the digital channel, and are used to delay the signal in the digital channel with multiple delay values.
[0047] In this embodiment, if the linearity of the multiple delay units is good, the resolution k of the delay unit can be calculated first. For example, when the number of delay units is n, the return time of the signal after passing through n delay units is T CN , then k=(T CN -T C1 ) / n, and then the delay of any number of delay units can be calculated according to the resolution. If the linearity is poor, it can be calibrated in segments, dividing the parts with similar linearity into segments, calculating the resolution of each segment, and finally fitting multiple segments of calibration data for compensation. In addition, the delay value can be calculated for each delay unit to ensure that the delay value of each delay unit is more accurate.
[0048] In summary, the device architecture in the above embodiment can be used in multiple calibration scenarios such as intra-channel path alignment, external output path delay measurement, and delay unit calibration.
[0049] In a second aspect of the embodiments of the present application, a test device is provided, which may include: a digital channel delay determination device as shown in any one of the embodiments of the first aspect.
[0050] For the convenience and simplicity of description, the specific structure of the test equipment described above can refer to the corresponding introduction in the aforementioned digital channel delay determination device embodiment. The technical problems solved and the technical effects achieved by the digital channel delay determination device can also be achieved by the test equipment, and will not be repeated here.
[0051] In addition, the test equipment is simple in design, economical to use, has a wide range of applications, does not require external instruments for testing, and fully utilizes the internal resources of the test equipment.
[0052] The embodiments of the present application are described above in conjunction with the accompanying drawings, but the present application is not limited to the above-mentioned specific implementation methods. The above-mentioned specific implementation methods are merely illustrative and not restrictive. Under the guidance of the present application, ordinary technicians in this field can also make many forms without departing from the purpose of the present application and the scope of protection of the claims, all of which are within the protection of the present application.
Claims
1. A digital channel delay determination device, characterized in that: include: Processor, sending module, receiving module and connector; The processor is connected to the input end of the sending module through a digital channel, the output end of the sending module is connected to the first pin of the connector, the first pin of the connector is also connected to the input end of the receiving module, and the output end of the receiving module is connected to the processor; The digital channel includes at least two signal paths.
2. The digital channel delay determination device according to claim 1, characterized in that: The processor includes a driving unit, a logic unit and a time measurement unit; The driving unit is connected to the input end of the logic unit through the digital channel, the output end of the logic unit is connected to the input end of the sending module, and the output end of the receiving module is connected to the time measurement unit.
3. The digital channel delay determination device according to claim 2, characterized in that: The digital channel includes a first signal path and a second signal path; One end of the first signal path and the second signal path is connected to the driving unit, and the other end of the first signal path and the second signal path is connected to the input end of the logic unit.
4. The digital channel delay determination device according to claim 1, characterized in that: The sending module is connected to the receiving module. A switch is provided between a connection point between the sending module and the receiving module and the connector. The switch is used to switch on and off the connection between the connection point and the connector.
5. The digital channel delay determination device according to claim 2, characterized in that: Also includes: External modules; The connector includes a first pin and a second pin; The external module is connected to the second pin.
6. The digital channel delay determination device according to claim 5, characterized in that: The external module includes: external cables and / or boards.
7. The digital channel delay determination device according to claim 5, characterized in that: Also includes: Storage module; The storage module is connected to the time measurement unit and is used to store time measurement data.
8. The digital channel delay determination device according to claim 1, characterized in that: The processor includes a delay unit; The delay unit is arranged in the digital channel, and is used for delaying the signal in the digital channel.
9. The digital channel delay determination device according to claim 8, characterized in that: There are multiple delay units; The multiple delay units are all arranged in the digital channel, and are used to delay the signal in the digital channel with multiple delay values.
10. A testing device, characterized in that: include: The digital channel delay determination device as described in any one of claims 1 to 9.