Semiconductor packaging structure and electronic equipment

Abstract

The utility model relates to a semiconductor packaging structure and electronic equipment. The utility model discloses a semiconductor packaging structure, and the structure comprises a substrate which is provided with a first surface and a second surface, the first metal coating comprises a first sub-part and a second sub-part which are arranged on the first surface at an interval; the semiconductor device is arranged on one side, far away from the substrate, of the first sub part; one side, close to the substrate, of the semiconductor device is provided with a first electrode, and the first electrode is electrically connected with the first metal coating; a first bonding pad is arranged on one side, far away from the substrate, of the semiconductor device, a plurality of first leads are correspondingly connected to the first bonding pad, and the plurality of first leads are electrically connected with the second sub-part. Therefore, the first metal coating is arranged on the substrate, and the layout on the substrate can be designed, so that the area of the second sub-part (bonding area) can be larger according to requirements, the number of the first leads (bonding wires) is increased, and the current capacity of a product is improved.

Description

Technical Field

[0001] The present application relates to the technical field of semiconductor device packaging, and in particular to a semiconductor packaging structure and electronic equipment. Background Art

[0002] Power electronic devices are the core components of energy conversion and are indispensable to the current power, electronics, motor and energy industries. Among them, power semiconductor devices are the core devices of power electronic devices. With the further improvement of the miniaturization and integration of integrated circuits, the high voltage and high current requirements of power device packaging structures are getting higher and higher. However, the current capacity of traditional power device packaging structures is low, which is not conducive to further improving the performance of power electronic devices. Summary of the invention

[0003] Based on this, it is necessary to provide a semiconductor packaging structure and an electronic device to address at least one of the above problems.

[0004] In order to achieve the above objectives, in a first aspect, an embodiment of the present application provides a semiconductor packaging structure, including:

[0005] A substrate having a first surface and a second surface arranged opposite to each other;

[0006] a first metal plating layer, comprising a first sub-portion and a second sub-portion arranged at intervals on the first surface; and

[0007] A semiconductor device is arranged on a side of the first sub-section away from the substrate; a first electrode is arranged on a side of the semiconductor device close to the substrate, and the first electrode is electrically connected to the first metal plating layer; a first soldering pad is arranged on a side of the semiconductor device away from the substrate, and a plurality of first leads are correspondingly connected to the first soldering pad, and the plurality of first leads are electrically connected to the second sub-section.

[0008] In one of the embodiments, the semiconductor packaging structure further includes a first conductive connection layer, the first conductive connection layer is disposed on the first sub-portion, the semiconductor device is disposed on the first conductive connection layer, and the first electrode is connected to the first conductive connection layer.

[0009] In one embodiment, the semiconductor package structure further includes:

[0010] A second conductive connection layer is provided on the first sub-section; the first sub-section has a first region and a second region, the first conductive connection layer is located in the first region, and the second conductive connection layer is located in the second region;

[0011] A first pin connected to a side of the second conductive connection layer away from the substrate;

[0012] A third conductive connection layer is provided on the second sub-portion;

[0013] The second pin is connected to a side of the third conductive connection layer away from the substrate.

[0014] In one embodiment, the first pin and the second pin have the same structure; the first pin comprises:

[0015] A connecting portion, disposed on the second conductive connecting layer;

[0016] An extension portion is provided on a side of the connecting portion away from the substrate, one end of the extension portion is connected to the connecting portion, and the other end of the extension portion extends in a direction away from the substrate;

[0017] A pin portion, one end of which is connected to an end of the extension portion away from the substrate, and the other end of which extends in a direction away from the center of the substrate.

[0018] In one of the embodiments, the minimum distance between a surface of the pin portion close to the substrate and a surface of the substrate away from the semiconductor device is greater than or equal to 7 mm.

[0019] In one embodiment, the first metal coating further includes a third sub-portion disposed on the first surface, and the third sub-portion and the second sub-portion are respectively disposed on two opposite sides of the first sub-portion;

[0020] A second pad is provided on a side of the semiconductor device away from the substrate, and a plurality of second leads are correspondingly connected to the second pad, and the plurality of second leads are electrically connected to the third sub-section.

[0021] In one embodiment, the semiconductor package structure further includes:

[0022] a fourth conductive connection layer, disposed on the third sub-portion;

[0023] The third pin is connected to a side of the fourth conductive connection layer away from the substrate; the third pin has the same structure as the first pin.

[0024] In one embodiment, the semiconductor package structure further includes a second metal coating layer, and the second metal coating layer is disposed on the second surface.

[0025] In a second aspect, an embodiment of the present application provides an electronic device, comprising the semiconductor packaging structure described in any embodiment of the first aspect.

[0026] In one of the embodiments, the electronic device further includes a heat sink, and the heat sink is disposed on a side of the second metal coating layer of the semiconductor package structure away from the substrate.

[0027] The semiconductor packaging structure and electronic device provided by the embodiment of the present application are provided by providing a first metal coating on the substrate, wherein a semiconductor device is provided on the first sub-section, the second sub-section is used to be electrically connected to the first lead, and multiple first leads are electrically connected to the first pad and the second sub-section. In this way, by providing the first metal coating on the substrate, since the layout on the substrate can be designed, the area of ​​the second sub-section (bonding area) can be made larger according to demand, so that the number of first leads (bonding wires) is increased, the current capacity of the product is improved, and the problem that the current capacity of the traditional packaging structure cannot be improved due to the relatively fixed bonding area and small area is improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the conventional technology, the drawings required for use in the embodiments or the conventional technology descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0029] Figure 1 A schematic structural diagram of a semiconductor packaging structure provided in one embodiment of the present application.

[0030] Figure 2 for Figure 1 A side view of the semiconductor package structure is shown.

[0031] Figure 3A for Figure 1 The schematic plan view of the first metal plating layer and the second metal plating layer of the semiconductor package structure after fabrication is shown.

[0032] Figure 3B for Figure 1 The schematic side view of the first metal plating layer and the second metal plating layer of the semiconductor package structure after being manufactured is shown.

[0033] Figure 4A for Figure 1 The schematic plan view of the conductive connection layer of the semiconductor package structure after fabrication is shown.

[0034] Figure 4B for Figure 1 The schematic side view of the conductive connection layer of the semiconductor package structure after fabrication is shown.

[0035] Figure 5A for Figure 1 The semiconductor device and lead frame of the semiconductor package structure shown are plan views after fabrication.

[0036] Figure 5B for Figure 1 The semiconductor device and lead frame of the semiconductor package structure shown are side views after fabrication.

[0037] Fig. 6A for Figure 1 The schematic plan view of the leads of the semiconductor package structure after fabrication is shown.

[0038] Figure 6B for Figure 1 The schematic side view of the leads of the semiconductor package structure after fabrication is shown.

[0039] Fig. 7A for Figure 1 The schematic plan view of the semiconductor package structure after packaging is shown.

[0040] Figure 7B for Figure 1 The semiconductor package structure shown is a side view schematic diagram after packaging.

[0041] Fig. 8A for Figure 1 A plan view of the lead frame of the semiconductor package structure shown in FIG. 1 after electroplating.

[0042] Figure 8B for Figure 1 A side view of the lead frame of the semiconductor package structure shown after electroplating.

[0043] Fig.9A for Figure 1 The schematic plan view of the lead frame of the semiconductor package structure after cutting is shown.

[0044] Fig. 9B for Figure 1 The schematic side view of the lead frame of the semiconductor package structure after cutting is shown.

[0045] Fig.10 A schematic diagram of a partial structure of an electronic device provided in one embodiment of the present application.

[0046] Reference numerals:

[0047] 100. Electronic device; 10. Semiconductor packaging structure; 11. Substrate; 12. First metal coating; 121. First sub-unit; 122. Second sub-unit; 123. Third sub-unit; 13. Semiconductor device; 141. First conductive connection layer; 142. Second conductive connection layer; 143. Third conductive connection layer; 144. Fourth conductive connection layer; 151. First pin; 1511. Connecting portion; 1512. Extending portion; 1513. Pin portion; 152. Second pin; 153. Third pin; 16. Second metal coating; 171. First lead; 172. Second lead; 18. Package; 20. Heat sink; 30. Circuit board; 40. Pad. DETAILED DESCRIPTION

[0048] In order to make the above-mentioned purposes, features and advantages of the present application more obvious and easy to understand, the specific implementation methods of the present application are described in detail below in conjunction with the accompanying drawings. In the following description, many specific details are set forth to facilitate a full understanding of the present application. However, the present application can be implemented in many other ways different from those described herein, and those skilled in the art can make similar improvements without violating the connotation of the present application, so the present application is not limited by the specific embodiments disclosed below.

[0049] In the description of the present application, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present application.

[0050] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In the description of this application, the meaning of "plurality" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined.

[0051] In this application, unless otherwise clearly specified and limited, the terms "installed", "connected", "connected", "fixed" and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements, unless otherwise clearly defined. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0052] In the present application, unless otherwise clearly specified and limited, a first feature being “above” or “below” a second feature may mean that the first and second features are in direct contact, or the first and second features are in indirect contact through an intermediate medium. Moreover, a first feature being “above”, “above”, and “above” a second feature may mean that the first feature is directly above or obliquely above the second feature, or simply means that the first feature is higher in level than the second feature. A first feature being “below”, “below”, and “below” a second feature may mean that the first feature is directly below or obliquely below the second feature, or simply means that the first feature is lower in level than the second feature.

[0053] It should be noted that when an element is referred to as being "fixed to" or "disposed on" another element, it may be directly on the other element or there may be a central element. When an element is considered to be "connected to" another element, it may be directly connected to the other element or there may be a central element at the same time. The terms "vertical", "horizontal", "upper", "lower", "left", "right" and similar expressions used herein are for illustrative purposes only and are not intended to be the only implementation method.

[0054] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include / comprise" or "have" and the like specify the presence of stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not exclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. At the same time, in this specification, the term "and / or" includes any and all combinations of the relevant listed items.

[0055] First, refer to Figure 1-9B As shown, an embodiment of the present application provides a semiconductor package structure 10 , which includes a substrate 11 , a first metal plating layer 12 and a semiconductor device 13 .

[0056] The substrate 11 has a first surface and a second surface that are arranged opposite to each other. The first metal coating 12 is arranged on the first surface, and the first metal coating 12 includes a first sub-section 121 and a second sub-section 122 that are arranged at intervals on the first surface. The semiconductor device 13 is arranged on a side of the first sub-section 121 away from the substrate 11. A first electrode (not shown in the figure) is provided on a side of the semiconductor device 13 close to the substrate 11, and the first electrode is electrically connected to the first metal coating 12. A first pad (not shown in the figure) is provided on a side of the semiconductor device 13 away from the substrate 11, and a plurality of first leads 171 are correspondingly connected to the first pad, and the plurality of first leads 171 are electrically connected to the second sub-section 122.

[0057] It is understandable that the substrate 11 can be made of an insulating material, so that the interior of the semiconductor package structure 10 can be insulated from the second surface of the substrate 11. Exemplarily, the substrate 11 can be a ceramic substrate 11, and the material of the ceramic substrate 11 can be aluminum oxide, aluminum nitride, etc. The first metal coating 12 can be a copper coating or other metal coating. The semiconductor device 13 can be a metal-oxide-semiconductor field-effect transistor (Metal-Oxide-Semiconductor Field-EffectTransistor, MOSFET) device, an insulated gate bipolar transistor (Insulated Gate Bipolar Transistor, IGBT) device, etc.

[0058] It should be noted that a plurality of first pads may be provided on the semiconductor device 13 , and the embodiment of the present application does not limit the number of the first pads. Further, the first pad may be electrically connected to the second electrode of the semiconductor device 13 .

[0059] The semiconductor package structure 10 provided in the embodiment of the present application is provided with a first metal plating layer 12 on a substrate 11, wherein a semiconductor device 13 is provided on a first sub-section 121, and a second sub-section 122 is used to be electrically connected to a first lead 171, and a plurality of first leads 171 are electrically connected to a first pad and a second sub-section 122. In this way, by providing the first metal plating layer 12 on the substrate 11, since the area of ​​the substrate 11 is relatively large, the layout on the substrate 11 can be designed, and therefore, the area of ​​the second sub-section 122 (bonding area) can be made larger according to demand, so that the number of first leads 171 (bonding wires) is increased, and the current capacity of the product is improved, which improves the problem that the current capacity of the traditional package structure cannot be improved due to the relatively fixed bonding area and small area.

[0060] In one embodiment, the semiconductor package structure 10 further includes a first conductive connection layer 141, the first conductive connection layer 141 is disposed on the first sub-portion 121, the semiconductor device 13 is disposed on the first conductive connection layer 141, and the first electrode is connected to the first conductive connection layer 141. By providing the first conductive connection layer 141, not only can the semiconductor device 13 be structurally connected to the first metal plating layer 12, but also the first electrode of the semiconductor device 13 can be electrically connected to the first metal plating layer 12.

[0061] It is understandable that the first conductive connection layer 141 can be a solder sheet, solder paste, nano silver, etc.

[0062] Compared with the conventional technology of connecting multiple semiconductor devices 13 to the conductive frame one by one using welding wires, by providing the first conductive connection layer 141, multiple semiconductor devices 13 can be connected simultaneously in one process, which is beneficial to improving production efficiency.

[0063] In one embodiment, the semiconductor package structure 10 further includes a second conductive connection layer 142 , a first lead 151 , a third conductive connection layer 143 and a second lead 152 .

[0064] The second conductive connection layer 142 is disposed on the first sub-section 121. The first sub-section 121 has a first region (not shown) and a second region (not shown), the first conductive connection layer 141 is located in the first region, and the second conductive connection layer 142 is located in the second region. The first pin 151 is connected to a side of the second conductive connection layer 142 away from the substrate 11. The third conductive connection layer 143 is disposed on the second sub-section 122. The second pin 152 is connected to a side of the third conductive connection layer 143 away from the substrate 11.

[0065] In this way, not only can the pin be connected to the first metal plating layer 12 in structure, but the two can also be electrically connected.

[0066] It is understandable that the second conductive connection layer 142 and the third conductive connection layer 143 may be solder sheets, solder paste, nanosilver, etc. The second conductive connection layer 142, the third conductive connection layer 143 and the first conductive connection layer 141 may be manufactured in the same process.

[0067] Here, it should be noted that a plurality of first regions may be provided on the first sub-portion 121 , and each first region is provided with a first sub-portion 121 , so that a plurality of semiconductor devices 13 may be provided on the first metal plating layer 12 .

[0068] In one embodiment, referring to Figure 5A and Figure 5BAs shown, the first pin 151 and the second pin 152 have the same structure. Specifically, the first pin 151 includes a connecting portion 1511, an extending portion 1512 and a pin portion 1513. Take the arrangement of the first pin 151 as an example: the connecting portion 1511 is arranged on the second conductive connection layer 142, the extending portion 1512 is arranged on the side of the connecting portion 1511 away from the substrate 11, and one end of the extending portion 1512 is connected to the connecting portion 1511, and the other end of the extending portion 1512 extends in a direction away from the substrate 11. One end of the pin portion 1513 is connected to one end of the extending portion 1512 away from the substrate 11, and the other end of the pin portion 1513 extends in a direction away from the center of the substrate 11, that is, the other end of the pin portion 1513 extends toward the periphery of the substrate 11.

[0069] It is understandable that the second surface of the substrate 11 needs to be connected to the heat sink 20. The above configuration can keep the first pin 151 away from the heat sink 20, thereby meeting the high voltage creepage distance requirement and making the semiconductor packaging structure 10 suitable for applications greater than 1200V.

[0070] In one embodiment, the angle between the extension direction of the connecting portion 1511 and the extension direction of the extending portion 1512 is greater than 90°, and the angle between the extension direction of the extending portion 1512 and the extension direction of the pin portion 1513 is greater than 90°. In this way, the structure of the first pin 151 can be made more reasonable, and it is easy to manufacture and assemble.

[0071] In one embodiment, the minimum distance between the surface of the pin portion 1513 close to the substrate 11 and the surface of the substrate 11 away from the semiconductor device 13 is greater than or equal to 7 mm. In this way, the pin can be kept away from the heat sink 20, thereby meeting the creepage distance requirement of high voltage, and the semiconductor package structure 10 can be applied to occasions greater than 1200V.

[0072] In one embodiment, referring to Figure 5B As shown, the second surface of the substrate 11 is provided with a second metal plating layer 16, and the minimum distance L between the surface of the pin portion 1513 close to the substrate 11 and the surface of the second metal plating layer 16 away from the semiconductor device 13 is greater than or equal to 7 mm. In this way, the pin can be kept away from the heat sink 20, thereby meeting the creepage distance requirement of high voltage, and the semiconductor package structure 10 can be applied to occasions greater than 1200V.

[0073] In one embodiment, the first metal plating layer 12 further includes a third sub-section 123 disposed on the first surface, and the third sub-section 123 and the second sub-section 122 are respectively disposed on opposite sides of the first sub-section 121. A second pad (not shown) is disposed on the side of the semiconductor device 13 away from the substrate 11, and a plurality of second leads 172 are correspondingly connected to the second pad, and the plurality of second leads 172 are electrically connected to the third sub-section 123. The above arrangement can further improve the current capacity of the product.

[0074] It should be noted that in Figure 1 In the figure, only one second lead 172 is shown, and other second leads 172 are not shown. In addition, a plurality of second pads may be provided on the semiconductor device 13, and the number of the second pads is not limited in the embodiment of the present application. Further, the second pad may be electrically connected to the third electrode of the semiconductor device 13.

[0075] It is understandable that the first sub-section 121 , the second sub-section 122 and the third sub-section 123 may be arranged in other arrangements, which is not limited in the embodiment of the present application.

[0076] In one embodiment, the semiconductor package structure 10 further includes a fourth conductive connection layer 144 and a third pin 153. The fourth conductive connection layer 144 is disposed on the third sub-portion 123. The third pin 153 is connected to a side of the fourth conductive connection layer 144 away from the substrate 11. The third pin 153 has the same structure as the first pin 151.

[0077] It is understandable that the first conductive connection layer 141 may be a solder sheet, solder paste, nanosilver, etc. The first conductive connection layer 141, the second conductive connection layer 142, the third conductive connection layer 143 and the fourth conductive connection layer 144 may be manufactured in the same process.

[0078] In one embodiment, the semiconductor package structure 10 further includes a second metal coating 16, and the second metal coating 16 is disposed on the second surface. It is understandable that the second surface of the substrate 11 usually needs to be connected to the heat sink 20. The above arrangement is conducive to improving the heat dissipation capacity of the semiconductor package structure 10 on the one hand; on the other hand, the heat sink 20 can be welded to the semiconductor package structure 10, which can not only reduce the thermal resistance of the product, improve the heat dissipation capacity, but also improve the assembly efficiency.

[0079] In one embodiment, a heat conducting member is disposed on the second surface of the substrate 11. For example, the heat conducting member may be a thermal conductive silicone grease. In this way, not only the thermal resistance of the product can be reduced, the heat dissipation capacity can be improved, but also the cost of the process and materials can be reduced.

[0080] Please refer to Figure 3A-Figure 9B As shown, the embodiment of the present application provides Figure 1A method for manufacturing the semiconductor package structure 10 shown:

[0081] Reference Figure 3A and Figure 3B As shown, in the first step, a first metal coating 12 is provided on the first surface of the substrate 11, and a second metal coating 16 is provided on the second surface of the substrate 11. In this step, the placement position, bonding point position and pin position of the semiconductor device 13 can be designed. It can be understood that the structure formed by the substrate 11, the first metal coating 12 and the second metal coating 16 can be a directly bonded copper ceramic substrate 11 (DBC), an active metal welding ceramic substrate 11 (AMB), a directly electroplated copper ceramic substrate 11 (DPC), etc.

[0082] Reference Figure 4A and Figure 4B As shown, in the second step, a first conductive connection layer 141, a second conductive connection layer 142, a third conductive connection layer 143 and a fourth conductive connection layer 144 are arranged on the first metal plating layer 12. Exemplarily, solder paste can be brushed, conductive glue can be applied, nano silver can be applied or solder sheets can be installed. It should be noted that in the traditional packaging structure of TO-type discrete devices, the semiconductor device 13 is connected to the metal frame, and because the surface of the metal frame is uneven, the brushing glue and solder paste reflow method cannot be used, and multiple welding will lead to reduced welding accuracy. After the embodiment of the present application converts the traditional metal frame into a double-sided metal-plated ceramic substrate 11, the brushing glue and solder paste reflow method can be used. Only one welding is required when assembling the semiconductor device 13, which improves the assembly accuracy and can meet high reliability requirements.

[0083] Reference Figure 5A and Figure 5B As shown, in the third step, the semiconductor device 13 and the lead frame are assembled and reflowed to connect the semiconductor device 13, the lead frame and the first metal plating layer 12. It should be noted that in the packaging structure of traditional TO-type discrete devices, multiple semiconductor devices 13 usually need to be welded multiple times, while in the packaging structure provided by the present application, multiple semiconductor devices 13 can be welded simultaneously in one process, which is conducive to improving production efficiency.

[0084] Reference Fig. 6A and Figure 6B As shown, in the fourth step, the first pad is electrically connected to the second sub-section 122 using the first lead 171 , and the second pad is electrically connected to the third sub-section 123 using the second lead 172 .

[0085] Reference Fig. 7A and Figure 7B As shown, in the fifth step, the packaging is performed using a packaging member 18. Specifically, epoxy resin is used for plastic packaging and then cured.

[0086] Reference Fig. 8A and Figure 8B As shown, in the sixth step, the lead frame is electroplated to prevent the pins from oxidizing and facilitate subsequent welding.

[0087] Reference Fig.9A and Fig. 9B As shown, in the seventh step, the lead frame is cut to separate the first lead 151, the second lead 152 and the third lead 153. After completion, testing, packaging and other processes can be carried out.

[0088] Second, refer to Fig.10 As shown, an embodiment of the present application provides an electronic device 100, comprising a semiconductor packaging structure 10 according to any embodiment of the first aspect.

[0089] In one embodiment, the electronic device 100 further includes a heat sink 20, which is disposed on a side of the second metal coating layer 16 of the semiconductor package structure 10 away from the substrate 11. It is understood that a welding layer or thermal conductive silicone grease may be disposed between the heat sink 20 and the semiconductor package structure 10.

[0090] In one embodiment, the electronic device 100 further includes a circuit board 30 , the semiconductor package structure 10 is disposed on the circuit board 30 , and pins of the semiconductor package structure 10 are electrically connected to the circuit board 30 .

[0091] In one embodiment, a pad 40 is disposed on the circuit board 30, and at least a portion of the structure of the semiconductor package structure 10 is disposed on the pad 40. In this way, the assembly stability of the semiconductor package structure 10 and the circuit board 30 can be improved.

[0092] The electronic device 100 provided in the embodiment of the present application is provided with a first metal plating layer 12 on a substrate 11, wherein a semiconductor device 13 is provided on a first sub-section 121, and a second sub-section 122 is used to be electrically connected to a first lead 171, and a plurality of first leads 171 are electrically connected to a first pad and a second sub-section 122. In this way, by providing the first metal plating layer 12 on the substrate 11, since the layout on the substrate 11 can be designed, the area of ​​the second sub-section 122 (bonding area) can be made larger according to demand, so that the number of first leads 171 (bonding wires) is increased, the current capacity of the product is improved, and the problem that the current capacity of the traditional packaging structure cannot be improved due to the relatively fixed bonding area and small area is improved.

[0093] In the description of this specification, the description with reference to the terms "some embodiments", "other embodiments", "ideal embodiments", etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic descriptions of the above terms do not necessarily refer to the same embodiment or example.

[0094] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features of the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0095] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be construed as limiting the scope of the patent application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent application shall be subject to the attached claims.

Claims

1. A semiconductor packaging structure, characterized in that: include: A substrate having a first surface and a second surface arranged opposite to each other; A first metal plating layer includes a first sub-portion and a second sub-portion arranged at intervals on the first surface; as well as A semiconductor device is arranged on a side of the first sub-section away from the substrate; a first electrode is arranged on a side of the semiconductor device close to the substrate, and the first electrode is electrically connected to the first metal plating layer; a first soldering pad is arranged on a side of the semiconductor device away from the substrate, and a plurality of first leads are correspondingly connected to the first soldering pad, and the plurality of first leads are electrically connected to the second sub-section.

2. The semiconductor package structure according to claim 1, wherein: The semiconductor packaging structure further includes a first conductive connection layer, wherein the first conductive connection layer is disposed on the first sub-portion, the semiconductor device is disposed on the first conductive connection layer, and the first electrode is connected to the first conductive connection layer.

3. The semiconductor package structure according to claim 2, characterized in that: The semiconductor packaging structure further includes: A second conductive connection layer is provided on the first sub-section; the first sub-section has a first region and a second region, the first conductive connection layer is located in the first region, and the second conductive connection layer is located in the second region; A first pin connected to a side of the second conductive connection layer away from the substrate; A third conductive connection layer is provided on the second sub-portion; The second pin is connected to a side of the third conductive connection layer away from the substrate.

4. The semiconductor package structure according to claim 3, characterized in that: The first pin and the second pin have the same structure; the first pin comprises: A connecting portion, disposed on the second conductive connecting layer; An extension portion is provided on a side of the connecting portion away from the substrate, one end of the extension portion is connected to the connecting portion, and the other end of the extension portion extends in a direction away from the substrate; A pin portion, one end of which is connected to an end of the extension portion away from the substrate, and the other end of which extends in a direction away from the center of the substrate.

5. The semiconductor package structure according to claim 4, characterized in that: The minimum distance between a surface of the lead portion close to the substrate and a surface of the substrate away from the semiconductor device is greater than or equal to 7 mm.

6. The semiconductor package structure according to claim 3, characterized in that: The first metal plating layer further includes a third sub-portion disposed on the first surface, and the third sub-portion and the second sub-portion are respectively disposed on two opposite sides of the first sub-portion; A second pad is provided on a side of the semiconductor device away from the substrate, and a plurality of second leads are correspondingly connected to the second pad, and the plurality of second leads are electrically connected to the third sub-section.

7. The semiconductor package structure according to claim 6, characterized in that: The semiconductor packaging structure further includes: a fourth conductive connection layer, disposed on the third sub-portion; The third pin is connected to a side of the fourth conductive connection layer away from the substrate; the third pin has the same structure as the first pin.

8. The semiconductor packaging structure according to any one of claims 1 to 7, characterized in that: The semiconductor package structure further includes a second metal plating layer, and the second metal plating layer is disposed on the second surface.

9. An electronic device, characterized in that: The invention comprises a semiconductor packaging structure as claimed in any one of claims 1 to 8.

10. The electronic device according to claim 9, characterized in that: The electronic device further comprises a heat sink, which is arranged on a side of the second metal plating layer of the semiconductor package structure away from the substrate.

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