Chip protection ring structure
By designing a multi-layer metal interconnection unit buffer structure including diamond-shaped metal blocks and arc-edged metal blocks in the chip protection ring structure, the problem of easy breakage in the cutting process in the prior art is solved, and more effective stress buffering and protection effects are achieved.
Patent Information
- Application Number
- CN202421576225.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-07-04
- Publication Date
- 2025-04-18
- Estimated Expiration
- 2034-07-04
AI Technical Summary
The existing chip protection ring structure is susceptible to stress during the cutting process, resulting in fragility at corners, easy to break or damage, and thus weaken the protective effect.
A chip protection ring structure is designed, including a seal ring and a buffer structure located at the corner of the seal ring. The buffer structure consists of stacked multi-layer metal interconnection units, each layer including metal interconnection lines and dielectric layers. The metal interconnection lines include diamond-shaped metal blocks and arc-edged metal blocks. These structures guide the transmission of cutting cracks, causing damage stress to be blocked on the arc-shaped edges of arc-edged metal blocks, thereby reducing the degree of damage.
Through the design of diamond-shaped metal blocks and arc-edged metal blocks, the damage stress is weakened and slowed down, the direct impact of stress on the sealing ring is reduced, and the probability of metal interconnection units is reduced, thereby improving the protection effect of the chip protection ring structure.
Smart Images
Figure CN222775307U_ABST
Abstract
Description
Technical Field
[0001] The utility model belongs to the technical field of semiconductor manufacturing and relates to a chip protection ring structure. Background Art
[0002] With the development of semiconductor technology, a seal ring structure is usually set in the chip. The seal ring is composed of metal layers stacked from bottom to top. It is set between the chip device area and the cutting path. It is a sealing ring set between the chip device area. It can prevent the cutting cracks from damaging the chip device area when the wafer is cut. At the same time, it can play a role in moisture-proof and electromagnetic damage.
[0003] Most existing seal rings are octagonal in shape, but when cutting, the top corners of the octagonal seal ring are most susceptible to cutting stress, making the corners of the seal ring more fragile and easy to break or damage. In order to guide the cracks to avoid entering the corners of the seal ring as much as possible, a seal ring with a buffer structure is provided in the existing structure to obtain a better buffering effect. The buffer structure is usually made together with the device area.
[0004] However, since the metal at the top is thicker and has greater stress, this stress can easily cause deformation of the metal layer in the entire wafer, and even cause the fracture of part of the film layer, especially near the interface between the metal and the dielectric layer. For the corners, if the stress applied by the top metal has given the film layer the possibility of fracture, when cutting, the film layer at the fracture-prone location will be more likely to break and transmit the fracture when subjected to the stress or cracks transmitted by the cutting, thereby weakening the protective effect of the seal ring.
[0005] Therefore, it is necessary to provide a chip protection ring structure. Utility Model Content
[0006] In view of the above-mentioned shortcomings of the prior art, the purpose of the present invention is to provide a chip protection ring structure to solve the problem that the chip protection ring structure in the prior art is prone to weakening the protection effect of the protection ring.
[0007] In order to achieve the above-mentioned purpose and other related purposes, the utility model provides a chip protection ring structure, the chip protection ring structure comprising:
[0008] A sealing ring, wherein the sealing ring comprises an inclined edge, wherein an extending direction of the inclined edge is defined as a first direction, a direction perpendicular to the inclined edge is defined as a second direction, and a direction perpendicular to a plane formed by the first direction and the second direction from bottom to top is defined as a third direction;
[0009] A buffer structure, the buffer structure is located at a corner of the sealing ring, and includes M>1 layers of stacked metal interconnection units along the third direction, each layer of the metal interconnection units includes a metal interconnection line and a dielectric layer, the metal interconnection lines in each layer are electrically connected and spaced from the sealing ring, and the metal interconnection lines located in the lower layer extend into a portion of the dielectric layer in the upper layer adjacent thereto;
[0010] Among them, each layer of the metal interconnection lines includes diamond-shaped metal blocks and arc-edge metal blocks. In the first direction, the diamond-shaped metal blocks and the arc-edge metal blocks are arranged at intervals. In the second direction, N≥1 rows of diamond-shaped metal blocks are arranged between two adjacent rows of the arc-edge metal blocks, and on the plane formed by the first direction and the second direction, the diamond-shaped metal blocks form a first gap and a second gap. The angle between the first gap and the second gap toward the adjacent sealing ring is an obtuse angle, and the first gap and the second gap both intersect with the arc-edge metal block.
[0011] Optionally, a diagonal line corresponding to an obtuse angle in the rhombus-shaped metal block is perpendicular to the inclined edge.
[0012] Optionally, at least one side of the arc-edge metal block facing the diamond-shaped metal block is arc-shaped, the arc surface of the arc-edge metal block faces away from the sealing ring, and the first gap and the second gap both intersect with the arc surface of the arc-edge metal block.
[0013] Optionally, the shape of the arc-edge metal block includes a semi-ellipse or an ellipse.
[0014] Optionally, along the third direction, projections of adjacent metal interconnection lines are arranged to overlap with each other.
[0015] Optionally, the metal interconnection line at the lower layer extends into the dielectric layer at the same depth as that of the adjacent upper layer.
[0016] Optionally, the metal interconnection line at the lower layer extends into the dielectric layer at an adjacent upper layer at different depths, wherein the change in depth includes a gradual decrease along a third direction.
[0017] Optionally, in each layer of the metal interconnection unit, the lower surface of the metal interconnection line is at least partially flush with the lower surface of the corresponding dielectric layer.
[0018] Optionally, in each layer of the metal interconnection unit, the dielectric layer includes a stacked etch stop layer and a dielectric layer; in each layer of the metal interconnection unit, the metal interconnection line includes an electrically connected metal interconnection through hole and a metal interconnection layer.
[0019] Optionally, the sealing ring includes a single ring or a double ring; the sealing ring includes an open ring or a closed ring.
[0020] As described above, the chip protection ring structure of the utility model includes a sealing ring and a buffer structure located at the corner of the sealing ring, the buffer structure includes M layers of stacked metal interconnection units, each layer of metal interconnection units includes metal interconnection lines and dielectric layers, the metal interconnection lines in each layer are electrically connected and spaced apart from the sealing ring, and the metal interconnection lines located in the lower layer extend into part of the dielectric layer of the upper layer adjacent to it; each layer of metal interconnection lines includes diamond-shaped metal blocks and arc-edge metal blocks, in the first direction, the diamond-shaped metal blocks and the arc-edge metal blocks are spaced apart from each other, in the second direction, N rows of diamond-shaped metal blocks are arranged between two adjacent rows of arc-edge metal blocks, and on the plane formed by the first direction and the second direction, a first gap and a second gap are formed between the diamond-shaped metal blocks, the angle between the first gap and the second gap toward the adjacent sealing ring is an obtuse angle, and the first gap and the second gap both intersect with the arc-edge metal block.
[0021] The chip protection ring structure of the present application can weaken and slow down the damage stress through the diamond metal block and the arc-edge metal block, reduce the direct impact of the damage stress on the sealing ring, and allow the metal interconnection line to extend into part of the upper dielectric layer adjacent to it, so that there is a height difference between the metal interconnection line and the dielectric layer in the same layer, thereby reducing the splitting probability of the metal interconnection units in each layer, so that the chip protection ring structure can play a good protective role. BRIEF DESCRIPTION OF THE DRAWINGS
[0022] Figure 1 Shown is a schematic structural diagram of a chip protection ring structure in an embodiment of the present utility model.
[0023] Figure 2 Display as Figure 1 Schematic diagram of the cross-sectional structure along AA.
[0024] Component number description
[0025] 100 Sealing ring
[0026] 101 Slanted Edge
[0027] 200 Buffer structure
[0028] 210 Metal Interconnect Unit
[0029] 211 Metal Interconnect
[0030] 2111 Diamond Metal Block
[0031] 2112 Arc Edge Metal Block
[0032] 2113 Metal Interconnect Vias
[0033] 212 dielectric layer
[0034] 2121 Etch stop layer
[0035] 2122 Dielectric layer
[0036] 310 First Gap
[0037] 320 Second Gap DETAILED DESCRIPTION
[0038] The following is an explanation of the implementation of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific implementations, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.
[0039] It should be noted that the illustrations provided in this embodiment are only used to schematically illustrate the basic concept of the present invention. Therefore, the drawings only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.
[0040] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.
[0041] See also Figure 1 and Figure 2 ,in, Figure 2 Indicated as Figure 1 Schematic diagram of the cross-sectional structure along the middle line AA. This embodiment provides a chip protection ring structure, the chip protection ring structure includes a sealing ring 100 and a buffer structure 200, the sealing ring 100 includes an inclined edge 101, and the extending direction of the inclined edge 101 is defined as a first direction X, the direction perpendicular to the inclined edge 101 is defined as a second direction Y, and the direction perpendicular to the plane formed by the first direction X and the second direction Y from bottom to top is defined as a third direction Z.
[0042] The buffer structure 200 is located at the corner of the sealing ring 100, and includes M>1 layers of stacked metal interconnect units 210 along the third direction Z. Each layer of the metal interconnect units 210 includes a metal interconnect line 211 and a dielectric layer 212. The metal interconnect lines 211 in each layer are electrically connected and spaced apart from the sealing ring 100, and the metal interconnect lines 211 located in the lower layer extend into part of the dielectric layer 212 in the upper layer adjacent thereto.
[0043] Wherein, each layer of the metal interconnection line 211 includes a diamond-shaped metal block 2111 and an arc-edge metal block 2112. In the first direction X, the diamond-shaped metal block 2111 and the arc-edge metal block 2112 are arranged at intervals. In the second direction Y, N≥1 rows of the diamond-shaped metal blocks 2111 are arranged between two adjacent rows of the arc-edge metal blocks 2112. In addition, on the plane formed by the first direction X and the second direction Y, the diamond-shaped metal blocks 2111 form a first gap 310 and a second gap 320. The first gap 310 and the second gap 320 are spaced apart from each other. The angle θ of the gap 320 toward the adjacent sealing ring 100 is an obtuse angle, and the first gap 310 and the second gap 320 both intersect with the arc-edge metal block 2112, wherein the setting of the first gap 310 and the second gap 320 can guide the transmission of the cutting cracks during the cutting process, so that the arc-edge metal block 2112 intersects with the transmitted cracks, so that the cutting cracks collide with the arc-shaped edge of the arc-edge metal block 2112, so that the cutting force is buffered by the arc-edge metal block 2112, thereby greatly reducing the degree of damage.
[0044] Specifically, the rhombus described in this application does not include a square with right angles. Figure 1 , the buffer structure 200 is located outside the corner of the sealing ring 100. In this embodiment, in the first direction X, the diamond metal block 2111 and the arc-edge metal block 2112 are arranged at intervals, and a plurality of the diamond metal blocks 2111 are distributed in an array along the first direction X and the second direction Y. The arc-edge metal blocks 2112 and the diamond metal blocks 2111 are arranged alternately, wherein in the second direction Y, one row of the diamond metal blocks 2111 is arranged between two adjacent rows of the arc-edge metal blocks 2112, that is, N is 1, but the value of N is not limited to 1, and may also be 2, 3, 4, etc., which is not limited here.
[0045] In the array formed by the diamond metal blocks 2111, the first gap 310 and the second gap 320 are formed between the diamond metal blocks 2111, and the angle θ between the first gap 310 and the second gap 320 toward the adjacent sealing ring 100 is an obtuse angle, wherein the value of the angle θ may include, for example, 120°, 135°, 150°, etc., and no excessive limitation is made here.
[0046] In this embodiment, since the array formed by the rhombus-shaped metal blocks 2111 is further provided with a plurality of arc-edge metal blocks 2112 arranged at intervals and having arc-shaped surfaces and intersecting both the first gap 310 and the second gap 320, and preferably at least one side of the arc-edge metal block 2112 facing the rhombus-shaped metal block 2111 is arc-shaped, and the arc surface of the arc-edge metal block 2112 faces away from the sealing ring 100, the damage stress extending along the first gap 310 and the second gap 320 is not generated when encountering the first gap 310 and the second gap 320. After the arc-edge metal block 2112 is formed, the damage stress can be further weakened and slowed down by the blocking of the arc-shaped edge of the arc-edge metal block 2112, thereby further reducing the impact of the damage stress on the sealing ring 100; and because the arc surface of the arc-edge metal block 2112 is facing away from the sealing ring 100, the stress from the outside encounters the arc-edge metal block 2112, and after the force is decomposed, the arc surface can bear the damage stress, which makes it easier to slow down the stress impact and reduce the damage, thereby making the combined force away from the sealing ring 100.
[0047] As an example, the shape of the arc-edge metal block 2112 may include a semi-ellipse or an ellipse. In the present embodiment, the shape of the arc-edge metal block 2112 is an ellipse, but is not limited thereto. As required, the shape of the arc-edge metal block 2112 may also be set to be a semi-ellipse, or a combination of a semi-ellipse and an ellipse. No excessive restrictions are made here.
[0048] The selection of specific size, distribution, morphology, etc. of the diamond-shaped metal block 2111, the arc-edge metal block 2112, the first gap 310 and the second gap 320 is not overly limited here.
[0049] As an example, the diagonal corresponding to the obtuse angle in the diamond-shaped metal block 2111 is preferably perpendicular to the inclined edge 101, so that the diagonal corresponding to the obtuse angle in the diamond-shaped metal block 2111 is arranged along the second direction Y, thereby further reducing the direct impact of external force on the sealing ring 100.
[0050] See also Figure 2 Along the third direction Z, the buffer structure 200 includes 6 layers of stacked metal interconnect units 210, that is, the value of M is 6, but the value of M is not limited to 6, and can also be 2, 3, 4, 5, etc., which is not limited here.
[0051] Among them, each layer of the metal interconnection unit 210 includes the metal interconnection line 211 and the dielectric layer 212, the metal interconnection line 211 in each layer is electrically connected and spaced from the sealing ring 100, and the metal interconnection line 211 located in the lower layer extends into part of the dielectric layer 212 of the upper layer adjacent to it, that is, in each layer of the metal interconnection unit 210, the metal interconnection line 211 and the dielectric layer 212 have a height difference, so that in each layer of the metal interconnection unit 210, the metal interconnection line 211 and the dielectric layer 212 are not located on the same horizontal plane, but there is a height difference between the metal interconnection line 211 and the dielectric layer 212, such as Figure 2 The depth H1 in the sealing ring 100 can effectively avoid the probability of rupture due to stress or cracks near the interface between the metal and the dielectric layer, thereby enhancing the protection of the sealing ring 100.
[0052] As an example, in each layer of the metal interconnection unit 210, the dielectric layer 212 may include a stacked etch stop layer 2121 and a dielectric layer 2122; in each layer of the metal interconnection unit 210, the metal interconnection line 211 may include an electrically connected metal interconnection through hole 2113 and a metal interconnection layer, wherein the metal interconnection layer is Figure 1 The diamond-shaped metal block 2111 and the arc-edge metal block 2112.
[0053] The selection of specific types, materials, and structures of the metal interconnection lines 211 and the dielectric layer 212 in the metal interconnection unit 210 is not excessively limited herein.
[0054] As an example, the depth of the metal interconnection line 211 in the lower layer extending into the dielectric layer 212 in the upper layer adjacent thereto may be the same, such as Figure 2 The diagram shows that the depth H1 of the metal interconnection line 211 in the lower layer of the metal interconnection unit 210 in each layer extending into the dielectric layer 212 in the upper layer adjacent thereto is the same. Of course, in another embodiment, the depth of the metal interconnection line 211 in the lower layer extending into the dielectric layer 212 in the upper layer adjacent thereto may be different as required. The change of the depth may include gradually decreasing along the third direction, but is not limited thereto. The depth in a certain layer of the metal interconnection unit 210, such as the middle layer, the bottom layer, the top layer, etc., may also be maximized according to specific needs. That is, it may be set according to different products. In certain specific products, the part that is more susceptible to splitting due to the stress of the top metal layer may be located in a certain layer. At this time, the depth of the layer and the nearby layers may be set to be deeper than that of other places, so as to reduce the probability of splitting in the layer in a targeted manner, so that the chip protection ring structure plays a good protective role. No excessive restrictions are made here.
[0055] As an example, preferably, in each layer of the metal interconnection unit 210 , the lower surface of the metal interconnection line 211 is at least partially flush with the lower surface of the corresponding dielectric layer 212 .
[0056] Specifically, Figure 2 The figure illustrates the situation where the lower surface of the metal interconnect line 211 is flush with the bottom of the etch stop layer 2121 in its corresponding layer, that is, the etch stop layer 2121 serves as an etch stop layer and is eventually etched away to achieve the connection between the metal interconnect line 211 and the metal of the lower layer. The lower surface of the metal interconnect line 211 is flush with the bottom of the etch stop layer 2121 in its corresponding layer, which can further reduce the probability of rupture due to stress or cracks near the interface, and can enhance the protection of the sealing ring 100.
[0057] As an example, along the third direction Z, the projections of the adjacent metal interconnection lines 211 are preferably arranged to overlap with each other.
[0058] For details, see Figure 1 The diamond-shaped metal block 2111 and the arc-edge metal block 2112 located in the upper layer have an overlapping area with the diamond-shaped metal block 2111 and the arc-edge metal block 2112 located in the lower layer in their projections along the third direction Z, and the metal blocks in the upper and lower layers are electrically connected through the metal interconnection through-holes 2113, thereby further improving the buffer structure 200's ability to block damage stress.
[0059] The material of the diamond-shaped metal block 2111, the arc-edge metal block 2112 and the metal interconnection through hole 2113 can be selected as needed, such as copper metal, etc., which is not limited here. The specific morphology and connection position of the diamond-shaped metal block 2111, the arc-edge metal block 2112 and the metal interconnection through hole 2113 can be set as needed, which is not limited here.
[0060] As an example, the sealing ring 100 may include an open loop or a closed loop, that is, the sealing ring 100 may be an open-loop sealing ring with an opening, or may be a closed-loop sealing ring, which is not excessively limited here and can be set as needed.
[0061] In summary, the chip protection ring structure of the utility model includes a sealing ring and a buffer structure located at the corner of the sealing ring, the buffer structure includes M layers of stacked metal interconnection units, each layer of metal interconnection units includes metal interconnection lines and dielectric layers, the metal interconnection lines in each layer are electrically connected and spaced apart from the sealing ring, and the metal interconnection lines located in the lower layer extend into part of the dielectric layer of the upper layer adjacent to it; each layer of metal interconnection lines includes diamond-shaped metal blocks and arc-edge metal blocks, in the first direction, the diamond-shaped metal blocks and the arc-edge metal blocks are spaced apart from each other, in the second direction, N rows of diamond-shaped metal blocks are arranged between two adjacent rows of arc-edge metal blocks, and on the plane formed by the first direction and the second direction, a first gap and a second gap are formed between the diamond-shaped metal blocks, the angle between the first gap and the second gap toward the adjacent sealing ring is an obtuse angle, and the first gap and the second gap both intersect with the arc-edge metal block.
[0062] The chip protection ring structure of the present application can weaken and slow down the damage stress through the diamond-shaped metal block and the arc-edge metal block, reduce the direct impact of the damage stress on the sealing ring, and make the metal interconnection line extend into the part of the upper dielectric layer adjacent to it, so that there is a height difference between the metal interconnection line and the dielectric layer in the same layer, thereby reducing the splitting probability of the metal interconnection units in each layer, so that the chip protection ring structure plays a good protective role. Therefore, the utility model effectively overcomes various shortcomings in the prior art and has a high industrial utilization value.
[0063] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the technology may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed in the present invention shall still be covered by the claims of the present invention.
Claims
1. A chip protection ring structure, characterized in that: The chip protection ring structure comprises: A sealing ring, wherein the sealing ring comprises an inclined edge, wherein an extending direction of the inclined edge is defined as a first direction, a direction perpendicular to the inclined edge is defined as a second direction, and a direction perpendicular to a plane formed by the first direction and the second direction from bottom to top is defined as a third direction; A buffer structure, the buffer structure is located at a corner of the sealing ring, and includes M>1 layers of stacked metal interconnection units along the third direction, each layer of the metal interconnection units includes a metal interconnection line and a dielectric layer, the metal interconnection lines in each layer are electrically connected and spaced from the sealing ring, and the metal interconnection lines located in the lower layer extend into a portion of the dielectric layer in the upper layer adjacent thereto; Among them, each layer of the metal interconnection lines includes diamond-shaped metal blocks and arc-edge metal blocks. In the first direction, the diamond-shaped metal blocks and the arc-edge metal blocks are arranged at intervals. In the second direction, N≥1 rows of diamond-shaped metal blocks are arranged between two adjacent rows of the arc-edge metal blocks, and on the plane formed by the first direction and the second direction, the diamond-shaped metal blocks form a first gap and a second gap. The angle between the first gap and the second gap toward the adjacent sealing ring is an obtuse angle, and the first gap and the second gap both intersect with the arc-edge metal block.
2. The chip protection ring structure according to claim 1, characterized in that: The diagonal line corresponding to the obtuse angle in the rhombus metal block is perpendicular to the inclined side.
3. The chip protection ring structure according to claim 1, characterized in that: At least one side of the arc-edge metal block facing the diamond-shaped metal block is arc-shaped, the arc surface of the arc-edge metal block faces away from the sealing ring, and the first gap and the second gap both intersect with the arc surface of the arc-edge metal block.
4. The chip protection ring structure according to claim 3, characterized in that: The shape of the arc-edge metal block includes a semi-ellipse or an ellipse.
5. The chip protection ring structure according to claim 1, characterized in that: Along the third direction, projections of adjacent metal interconnection lines are overlapped with each other.
6. The chip protection ring structure according to claim 1, characterized in that: The metal interconnection line at the lower layer extends into the dielectric layer at the same depth as that of the upper layer adjacent thereto.
7. The chip protection ring structure according to claim 1, characterized in that: The metal interconnection line at the lower layer extends into the dielectric layer at a different depth from the upper layer adjacent thereto, wherein the change in the depth includes a gradual decrease along the third direction.
8. The chip protection ring structure according to claim 1, characterized in that: In each layer of the metal interconnection unit, the lower surface of the metal interconnection line is at least partially flush with the lower surface of the corresponding dielectric layer.
9. The chip protection ring structure according to claim 1, characterized in that: In each layer of the metal interconnection unit, the dielectric layer includes a stacked etch stop layer and a dielectric layer; in each layer of the metal interconnection unit, the metal interconnection line includes an electrically connected metal interconnection through hole and a metal interconnection layer.
10. The chip protection ring structure according to claim 1, characterized in that: The sealing ring includes a single ring or a double ring; the sealing ring includes an open ring or a closed ring.