Network-on-chip structure, processor and electronic equipment

Abstract

The utility model provides a network-on-chip structure, a processor and electronic equipment. The network-on-chip structure comprises a plurality of bare core structures and at least one boundary router, the bare core structure comprises a plurality of internal routers arranged in an array; each bare core structure is associated with at least one corresponding boundary router, and the boundary router associated with each bare core structure is connected with all the internal routers on one side edge of the bare core structure; the number of the boundary routers associated with each bare core structure is the same; for any bare core group, the boundary router associated with one bare core structure in the bare core group and the boundary router associated with the other bare core structure in the bare core group are in one-to-one correspondence and are connected with each other, so that in the process of data transmission across the bare core structures, when data is transmitted between the two bare core structures based on an X-Y routing strategy, the data transmission efficiency is improved. And the transmission direction is changed only once at most, so that the deadlock problem of data transmission of a cross-bare core structure is avoided.

Description

Technical Field

[0001] The utility model relates to the technical field of computers, and in particular to an on-chip network structure, a processor and an electronic device. Background Art

[0002] At present, the on-chip network includes multiple bare core structures, each of which is composed of multiple nodes arranged in an array. The nodes are processor cores, caches or other IP cores. Each node is associated with a router, and the nodes communicate through the router. When transmitting data between multiple bare core structures, an XY routing strategy can be used to reduce the probability of deadlock. The XY routing strategy means that data can only be transmitted between routers arranged in an array in the bare core structure in a horizontal and vertical transmission direction. When data is transmitted between any two routers in the bare core structure, a change in the transmission direction will occur at most once. When there is a knotted ring between the paths of multiple messages, the transmission of the message is blocked, and deadlock will occur. However, the XY routing strategy in the related art can only solve the deadlock problem during internal transmission of the bare core structure. For transmission between multiple bare core structures, there is still a high probability of deadlock. Utility Model Content

[0003] In view of the above problems, embodiments of the present utility model are proposed to provide a network-on-chip structure, a processor, and an electronic device that overcome the above problems or at least partially solve the above problems.

[0004] In a first aspect, an embodiment of the utility model discloses a network-on-chip structure, the network-on-chip structure comprising:

[0005] A plurality of bare core structures and at least one border router; the bare core structure comprises a plurality of internal routers arranged in an array; any two bare core structures constitute a bare core group; each of the bare core structures is associated with at least one corresponding border router, and each border router associated with the bare core structure is respectively connected to all internal routers on one side of the bare core structure; the number of border routers associated with each bare core structure is the same;

[0006] For any bare core group, a border router associated with one bare core structure corresponds to a border router associated with another bare core structure in the bare core group one by one and they are connected to each other.

[0007] In a second aspect, an embodiment of the utility model discloses a network-on-chip structure, the network-on-chip structure comprising:

[0008] A plurality of bare core structures and at least one border router; the bare core structure comprises a plurality of internal routers arranged in an array; any two bare core structures constitute a bare core group; each of the bare core structures is associated with two corresponding border routers, and the two border routers associated with each of the bare core structures are respectively connected to all the internal routers on one side of the bare core structure;

[0009] For any bare core group, two edge routers associated with one bare core structure correspond one-to-one with two edge routers associated with another bare core structure in the bare core group and are connected to each other.

[0010] In a third aspect, an embodiment of the utility model discloses a processor, wherein the processor includes an on-chip network structure.

[0011] In a fourth aspect, an embodiment of the utility model further discloses an electronic device, comprising a processor.

[0012] In an embodiment of the utility model, each bare core structure is associated with at least one corresponding border router, and each border router associated with the bare core structure is respectively connected to all internal routers on one side of the bare core structure; the number of border routers associated with each bare core structure is the same; for any bare core group, a border router associated with one bare core structure corresponds to a border router associated with another bare core structure in the bare core group one by one and is connected to each other. Under such a structural design, the border router and the internal router are separated from each other, so that the internal router only performs data transmission within the bare core structure, and the data transmission across the bare core structure is realized by the border router, and the border router does not participate in the internal transmission process of the bare core structure. In the process of data transmission across the bare core structure, when data is transmitted between the two bare core structures based on the XY routing strategy, there is at most only one change in the transmission direction, so that the data transmission across the bare core structure will not cause a deadlock problem. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 It is a schematic diagram of a network-on-chip structure provided by an embodiment of the utility model;

[0014] Figure 2 is a schematic diagram of another network-on-chip structure provided by an embodiment of the utility model;

[0015] Figure 3 It is a schematic diagram comparing transmission directions of on-chip networks provided by a related technology;

[0016] Figure 4 is a schematic diagram of another network-on-chip structure provided by an embodiment of the utility model;

[0017] Figure 5is a schematic diagram of another network-on-chip structure provided by an embodiment of the utility model;

[0018] Figure 6 is a schematic diagram of another network-on-chip structure provided by an embodiment of the utility model;

[0019] Figure 7 It is a partial structural diagram of a network-on-chip structure provided by an embodiment of the utility model;

[0020] Figure 8 is a schematic diagram of a processor provided by an embodiment of the utility model;

[0021] Fig. 9 It is a schematic diagram of an electronic device provided by an embodiment of the utility model. DETAILED DESCRIPTION

[0022] The exemplary embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. Although the exemplary embodiments of the present invention are shown in the accompanying drawings, it should be understood that the present invention can be implemented in various forms and should not be limited by the embodiments described herein. On the contrary, these embodiments are provided to enable a more thorough understanding of the present invention and to fully convey the scope of the present invention to those skilled in the art.

[0023] refer to Figure 1 , which shows a schematic diagram of an on-chip network structure provided by an embodiment of the utility model, including: multiple bare core structures 10 and at least one border router 12; the bare core structure 10 includes a processor core (or other IP), and multiple internal routers 11 arranged in an array; each processor core is associated with a router; any two bare core structures 10 constitute a bare core group; each bare core structure 10 is associated with at least one corresponding border router 12, and the border router 12 associated with each bare core structure 10 is respectively connected to all the internal routers 11 on one side of the bare core structure 10; the number of border routers 12 associated with each bare core structure 10 is the same; for any bare core group, the border router 12 associated with one bare core structure 10 corresponds to the border router 12 associated with another bare core structure 10 in the bare core group and is connected to each other.

[0024] In practical applications, although the multiple processor cores in a multi-core processor chip each execute their own code, data needs to be shared and synchronized between the processor cores. Therefore, the hardware structure of the multi-core processor must support efficient inter-core communication, and the performance of the on-chip communication structure will directly affect the performance of the processor.

[0025] Therefore, the Network on Chip (NoC) aims to solve the communication problem within the multi-core processor. The NoC is an integrated circuit on a communication subsystem based on a router network. The NoC is a packet switching network based on routers between systems on chip. The NoC technology draws on the interconnection network structure of parallel computers, integrating a large number of computing resources and an on-chip communication network connecting these resources on a single chip. Each processor core has an independent router and its private cache, and is connected together through an on-chip communication network. The processor cores use a message communication mechanism, and use routers and packet switching technology to replace the on-chip bus of related technologies to complete the communication task, thereby solving various bottleneck problems caused by bus interconnection in related technologies.

[0026] After determining the topology of the on-chip network, the routing algorithm can be used to determine the path that the message takes through the network to reach the destination. The goal of the routing algorithm is to evenly distribute traffic in the paths provided by the network topology, avoid hot spots, minimize contention, and improve network latency and throughput. While achieving these performance goals, design constraints must be observed to avoid critical paths that are too long and too large in area.

[0027] Among them, the bare core structure is also called a chiplet, which refers to a pre-manufactured chip (Die) with specific functions and can be combined and integrated. The bare core structure can divide the processor into multiple independent Dies, and then manufacture large chips through advanced packaging technology. This technology can reduce the manufacturing cost of large-scale chips, improve the reuse of a single Die, and reduce development costs. And when selecting or designing a routing algorithm, not only its impact on latency, power consumption, throughput and reliability must be considered, but also the network must be guaranteed to be deadlock-free.

[0028] Specifically, Figure 1 The figure shows a network-on-chip structure including two bare core structures 10, each bare core structure 10 includes an internal router 11 of 4×4 specification, and an XY routing strategy can be used to solve the deadlock problem for data transmission between the internal routers 11 included in each bare core structure 10. That is, the XY routing strategy avoids the occurrence of deadlock by limiting the transmission of data to be carried out along the longitudinal and lateral transmission directions.

[0029] For example, refer to Figure 2 , in a bare core structure 10, an XY routing strategy is implemented. Assuming that data is transmitted from router A to router B, there are two transmission paths: transmission path m1, first horizontal transmission and then vertical transmission; transmission path m2, first vertical transmission and then horizontal transmission. Regardless of the transmission path, the transmission direction will change (turn) at most once, thus avoiding the deadlock problem.

[0030] However, the XY routing strategy can only solve the deadlock problem during transmission within the bare core structure 10, and cannot avoid the deadlock problem for transmission between multiple bare core structures 10. The deadlock problem refers to the blocking of message transmission when there are knotted loops between the paths of multiple messages.

[0031] For example, refer to Figure 3 , data is transmitted between two bare core structures 10, and the XY routing strategy is executed. Assuming that data is exchanged between router C in one bare core structure 10 and router D in another bare core structure 10, the transmission path includes n1 and n2, which makes the data transmission produce a circular dependency, resulting in a deadlock problem, thereby blocking the data transmission.

[0032] In order to solve the above problems, in the embodiment of the present utility model, based on Figure 1 design, any two bare core structures 10 in all bare core structures 10 in the on-chip network can form a bare core group ( Figure 1 1 shows a bare core group), each bare core structure 10 may be associated with at least one border router 12, and the border router 12 is used for data transmission between bare core structures 10, that is, the internal router 11 in the bare core structure 10 can only perform data transmission within the bare core structure 10, while the border router 12 can perform data transmission across the bare core structure 10. In addition, the border router 12 associated with each bare core structure 10 is respectively connected to all the internal routers 11 on one side of the bare core structure 10, and the number of border routers 12 associated with each bare core structure 10 is the same. For any bare core group, the border router 12 associated with one bare core structure 10 corresponds to the border router 12 associated with another bare core structure 10 in the bare core group and is connected to each other.

[0033] Since the core idea of ​​the XY routing strategy is: in the process of transmitting data in the topology structure, at most one change in the transmission direction is allowed to occur to avoid deadlock, the embodiment of the utility model Figure 1The design is to separate the border router 12 from the internal router 11, so that the internal router 11 only performs data transmission inside the bare core structure 10, and the data transmission across the bare core structure 10 is realized by the border router 12, and the border router 12 does not participate in the internal transmission process of the bare core structure 10. Since the separately set border router 12 is connected to all the internal routers 11 on the side of the opposite side, when a bare core structure 10 communicates with all the internal routers 11 on the side opposite to the associated border router 12 and the border router 12 associated with the bare core structure 10, the transmission direction does not turn. By setting the border router 12 connected to the bare core structure 10 and independent of the bare core structure 10, the independent border router 12 does not intervene in the data transmission process inside the bare core structure 10 during the data transmission across the bare core structure 10. When data is transmitted between two bare core structures 10 based on the XY routing strategy, there is only one change in the transmission direction at most, so that the data transmission across the bare core structure will not cause deadlock problems.

[0034] For example, refer to Figure 4 For the communication between two bare core structures 10, assuming that the router E in one bare core structure 10 sends data to the router F in another bare core structure 10, the transmission path includes h1, assuming that the router G in one bare core structure 10 sends data to the router H in another bare core structure 10, the transmission path includes h2. It can be seen that no matter which transmission path, there is no change in the transmission direction (from longitudinal to transverse or from transverse to longitudinal, all the internal routers 11 on the side opposite to the associated border router 12 in the bare core structure 10, when communicating with the border router 12 associated with the bare core structure 10, the transmission direction does not turn), so that the data transmission conforms to the core idea of ​​the XY routing strategy, thereby avoiding the occurrence of deadlock problems. In addition, the embodiment of the utility model allows the internal part of one of the two bare core structures 10 that communicate with each other to change the transmission direction at most once during data transmission, thereby increasing the flexibility of routing selection during transmission.

[0035] It should be noted that the number of routers included in each bare core structure may also be n×m, and n and m may be different, which is not limited in the embodiment of the present utility model.

[0036] In summary, in the solution of the utility model, each bare core structure is associated with at least one corresponding border router, and each border router associated with the bare core structure is respectively connected to all internal routers on one side of the bare core structure; the number of border routers associated with each bare core structure is the same; for any bare core group, a border router associated with one bare core structure corresponds to a border router associated with another bare core structure in the bare core group one by one and is connected to each other. Under such a structural design, the border router and the internal router are separated from each other, so that the internal router only performs data transmission within the bare core structure, and the data transmission across the bare core structure is realized by the border router, and the border router does not participate in the internal transmission process of the bare core structure. In the process of data transmission across the bare core structure, when data is transmitted between the two bare core structures based on the XY routing strategy, there is at most only one change in the transmission direction, so that the data transmission across the bare core structure will not cause deadlock problems.

[0037] Optional, see Figure 1 , when each bare core structure 10 includes n×n internal routers 11; the number of edge routers 12 included in each bare core structure 10 is k, 1≤k<n.

[0038] In the embodiment of the utility model, the number k of border routers 12 associated with each bare core structure 10 is at least 1, and when each bare core structure 10 includes n×n internal routers 12, the number k of border routers 12 associated with each bare core structure 10 does not exceed n at most. Within this range, the number of border routers can be adjusted according to actual needs. Within this number range, associating more border routers can improve the data bandwidth during transmission across the bare core structure. Specifically, each time data is transmitted, one of the multiple border routers can be selected to perform the transmission.

[0039] Optional, see Figure 5 The utility model embodiment discloses an on-chip network structure, which includes: multiple bare core structures 10 and at least one border router 12; the bare core structure 10 includes multiple internal routers 11 arranged in an array; any two bare core structures 10 constitute a bare core group; each bare core structure 10 is associated with two corresponding border routers 12, and the two border routers 12 associated with each bare core structure 10 are respectively connected to all the internal routers 11 on one side of the bare core structure 10; for any bare core group, the two border routers 12 associated with one bare core structure 10 correspond to the two border routers 12 associated with another bare core structure 10 in the bare core group and are connected to each other.

[0040] Specifically, refer to Figure 5, which shows an on-chip network structure including two bare core structures 10, each bare core structure 10 includes a router 11 of 6×5 specifications, and each bare core structure 10 is associated with two border routers 12. Through a larger number of border routers 12, the data bandwidth during transmission across the bare core structures is improved.

[0041] Optional, see Figure 5 , when each bare core structure 10 includes n×m internal routers 11; the number of border routers 12 associated with each bare core structure 10 is k, if the total number of routers carried on the side of the bare core structure 10 connected to the border router 12 is n, then 1≤k<n; if the total number of routers carried on the side of the bare core structure 10 connected to the border router 12 is m, then 1≤k<m.

[0042] In the embodiment of the utility model, the border router 12 associated with the bare core structure 10 can be connected to all the internal routers 11 on any side of the bare core structure 10, such as Figure 1 The border router 12 is arranged on the left or right side of the bare core structure 10. Figure 5 The middle border router 12 is connected to all the internal routers 11 on the short side of the bare core structure 10. For the number k of border routers 12 associated with the bare core structure 10, if the total number of routers carried by the side of the bare core structure 10 connected by the border router 12 is n, then 1≤k<n; if the total number of routers carried by the side of the bare core structure 10 connected by the border router 12 is m, then 1≤k<m.

[0043] Regardless of the structure, it can be ensured that when data is transmitted between two bare core structures 10 based on the XY routing strategy, the change of the transmission direction will not exceed one time at most, so that the data transmission across the bare core structure will not cause deadlock problems.

[0044] Optional, see Figure 1 , the number of bare core structures 10 is an even number.

[0045] In the embodiment of the utility model, preferably, the number of bare core structures is an even number, so that the on-chip network structure can form a symmetrical structure that is easy to process and produce. Figure 1 , Figure 5 The number of bare core structures 10 is 2. Figure 6 , also shows a case where the number of bare core structures 10 is 4, each bare core structure 10 is of 4×4 specification, and each bare core structure 10 is associated with 1 border router 12.

[0046] Optional, see Figure 1 , Figure 5 and Figure 6The border router 12 associated with each bare core structure 10 is respectively connected to all internal routers 11 on the target side of the bare core structure 10. For any bare core group, the target side of one bare core structure 10 is arranged opposite to the target side of another bare core structure 10 in the bare core group; the target side is the side of the bare core structure 10 that is closest to the border router 12.

[0047] In the embodiment of the utility model, the target sides of any two bare core structures 10 are arranged relative to each other, and the target side is a side of the bare core structure 10 that is closest to the boundary router 12. In this way, the communication distance between the internal router 11 on the target side and the boundary router 12 can be shortened, and the processing difficulty when connecting the internal router on the target side and the boundary router is reduced.

[0048] Optional, see Figure 1 The bare core structure 10 includes routers 11 arranged in an array to form a grid structure. The routers 11 are located at the corner points of the grid in the grid structure, so that the data forwarded by the routers 11 are transmitted horizontally or vertically in the grid structure.

[0049] Specifically, refer to Figure 7 , which shows a partial structural diagram of an on-chip network structure, which shows a grid structure 50 formed by four routers 11 in the on-chip network structure. The grid structure 50 has four corner points 51, and a corresponding router 11 is arranged at each corner point.

[0050] In an embodiment of the utility model, the array-arranged routers 11 included in the bare core structure 10 can be formed into a grid structure, and each router 11 can be placed at a corner point of the grid in the grid structure, so that the horizontal transmission direction and the vertical transmission direction are realized in the bare core structure 10, that is, the transmission direction between the routers in the bare core structure is only horizontal and vertical, which provides a structural basis for the implementation of the XY routing strategy.

[0051] In addition, for the on-chip network structure of the embodiment of the utility model, only a single virtual channel is used, that is, the physical channel reflected by the connection between the routers in the on-chip network structure is the virtual channel. The virtual channel is a virtual channel divided from the physical channel by time-division multiplexing. It has an independent buffer and does not interfere with each other, but shares a physical link. From the perspective of the data packet, there are multiple virtual channels between the two routers, but the actual physical links are the same. One of the purposes of the utility model is to solve the deadlock problem by designing the position of the border router under the premise of using only a single virtual channel. A single virtual channel can reduce power consumption, reduce area, and reduce design complexity. By constraining the number, position, and connection relationship of the border routers, the purpose of deadlock-free under a single channel is achieved.

[0052] Reference Figure 8 , which shows a schematic diagram of a processor provided by an embodiment of the utility model, and the processor includes the on-chip network structure provided by the above embodiment.

[0053] Reference Fig. 9 , which shows a schematic diagram of an electronic device provided by an embodiment of the utility model, the electronic device may include Figure 8 processor.

[0054] In summary, in the solution of the utility model, each bare core structure is associated with at least one corresponding border router, and each border router associated with the bare core structure is respectively connected to all internal routers on one side of the bare core structure; the number of border routers associated with each bare core structure is the same; for any bare core group, a border router associated with one bare core structure corresponds to a border router associated with another bare core structure in the bare core group one by one and is connected to each other. Under such a structural design, the border router and the internal router are separated from each other, so that the internal router only performs data transmission within the bare core structure, and the data transmission across the bare core structure is realized by the border router, and the border router does not participate in the internal transmission process of the bare core structure. In the process of data transmission across the bare core structure, when data is transmitted between the two bare core structures based on the XY routing strategy, there is at most only one change in the transmission direction, so that the data transmission across the bare core structure will not cause deadlock problems.

[0055] Those skilled in the art will readily come up with other embodiments of the present invention after considering the specification and practicing the utility model disclosed herein. The present invention is intended to cover any variation, use or adaptation of the present invention, which follows the general principles of the present invention and includes common knowledge or customary technical means in the art that are not disclosed in the present disclosure. The specification and examples are to be regarded as exemplary only, and the true scope and spirit of the present invention are indicated by the following claims.

[0056] It should be understood that the present invention is not limited to the precise structure described above and shown in the drawings, and various modifications and changes can be made without departing from the scope thereof. The scope of the present invention is limited only by the appended claims.

Claims

1. A network-on-chip structure, characterized in that: The network-on-chip structure comprises: A plurality of bare core structures and at least one border router; the bare core structure comprises a plurality of internal routers arranged in an array; any two bare core structures constitute a bare core group; each of the bare core structures is associated with at least one corresponding border router, and each border router associated with the bare core structure is respectively connected to all internal routers on one side of the bare core structure; the number of border routers associated with each bare core structure is the same; For any bare core group, a border router associated with one bare core structure corresponds to a border router associated with another bare core structure in the bare core group one by one and they are connected to each other.

2. The network-on-chip structure according to claim 1, characterized in that: In the case where each of the bare core structures includes n×n internal routers, the number of edge routers included in each of the bare core structures is k, 1≤k<n.

3. The network-on-chip structure according to claim 1, characterized in that: In the case where each of the bare core structures includes n×m internal routers; the number of border routers associated with each of the bare core structures is k, and if the total number of routers carried by the side of the bare core structure connected by the border router is n, then 1≤k<n; If the total number of routers carried on the side of the bare core structure to which the border router is connected is m, then 1≤k<m.

4. The network-on-chip structure according to claim 1, characterized in that: The array-arranged internal routers included in the bare core structure form a grid structure, and the internal routers are located at the corner points of the grid in the grid structure, so that data forwarded by the internal routers are transmitted horizontally or vertically in the grid structure.

5. The network-on-chip structure according to claim 1, characterized in that: The number of the bare core structures is an even number.

6. The network-on-chip structure according to claim 1, characterized in that: Each of the border routers associated with the bare core structure is respectively connected to all internal routers on the target side of the bare core structure. For any bare core group, the target side of one bare core structure is arranged opposite to the target side of another bare core structure in the bare core group; the target side is a side of the bare core structure that is closest to the border router.

7. A network-on-chip structure, characterized in that: The network-on-chip structure comprises: A plurality of bare core structures and at least one border router; the bare core structure comprises a plurality of internal routers arranged in an array; any two bare core structures constitute a bare core group; each of the bare core structures is associated with two corresponding border routers, and the two border routers associated with each of the bare core structures are respectively connected to all the internal routers on one side of the bare core structure; For any bare core group, two edge routers associated with one bare core structure correspond one-to-one with two edge routers associated with another bare core structure in the bare core group and are connected to each other.

8. A processor, characterized in that: The processor comprises: the network-on-chip structure according to any one of claims 1 to 6, or the network-on-chip structure according to claim 7.

9. An electronic device, characterized in that: The processor according to claim 8 is included.

Images