Integrated chip and integrated circuit

Abstract

The utility model provides an integrated chip and an integrated circuit. The integrated chip includes: a first electrode made of metal; the second electrode is arranged on the first electrode; a ferroelectric layer between the first electrode and the second electrode; and an interface layer separating the ferroelectric layer from the first electrode, the interface layer comprising a semiconductor material and configured to separate the first electrode from the ferroelectric layer.

Description

Technical Field

[0001] The utility model relates to an integrated chip and an integrated circuit. Background Art

[0002] Many of today's electronic devices include non-volatile memory. Non-volatile memory is electronic memory that can store data in the absence of power. Promising candidates for the next generation of non-volatile memory include ferroelectric random-access memory (FeRAM). FeRAM has a relatively simple structure and is compatible with complementary metal-oxide-semiconductor (CMOS) logic manufacturing processes. Utility Model Content

[0003] The utility model provides an integrated chip, comprising: a first electrode, comprising metal; a second electrode, arranged on the first electrode; a ferroelectric layer, located between the first electrode and the second electrode; and an interface layer, separating the ferroelectric layer from the second electrode, wherein the interface layer comprises semiconductor material and is configured to separate the second electrode from the ferroelectric layer.

[0004] The utility model provides an integrated circuit, comprising: a first electrode, located on a substrate; a ferroelectric layer, arranged on the first electrode; a second electrode, arranged on the ferroelectric layer; and an interface layer, arranged on the first electrode and separating the first electrode from the ferroelectric layer, wherein no dielectric material exists directly between the first electrode and the second electrode. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Aspects of the present invention are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the various features are not drawn to scale. In fact, the size of the various features may be arbitrarily increased or decreased for clarity of discussion.

[0006] Figure 1 Cross-sectional views of some embodiments of memory cells including an interfacial layer as a semiconductor are shown.

[0007] Figure 2A and Figure 2B Show Figure 1 Cross-sectional views of some alternative embodiments of storage cells are shown.

[0008] Figure 3A and Figure 3B Show Figure 1 and Figure 2AVarious current / voltage (I / V) graphs of some embodiments of memory cells are shown.

[0009] Figure 4 Show Figure 1 A cross-sectional view of some embodiments of a memory cell is shown, wherein the memory cell is integrated with the interconnect structure of an integrated circuit (IC) chip.

[0010] Figure 5 Show Figure 4 Cross-sectional views of some alternative embodiments of memory cells are shown in which the top electrode width is reduced relative to the rest of the memory cell.

[0011] Figure 6 Show Figure 1 Cross-sectional views of some alternative embodiments of storage cells are shown, wherein components of the storage cell have a U-shaped profile.

[0012] Figure 7 Show Figure 6 Cross-sectional views of some alternative embodiments of storage cells are shown.

[0013] FIG. 8A to FIG. 8B Show Figure 1 Cross-sectional views of some alternative embodiments of memory cells are shown in which a top electrode surrounds a bottom electrode.

[0014] 9A to 9E Show Figure 2A Cross-sectional views of some alternative embodiments of memory cells are shown, where the interface layer is located at the bottom electrode.

[0015] Fig. 10A and Fig. 10B A cross-sectional view of some embodiments of an IC chip including a plurality of memory cells integrated into respective one-transistor-one-resistor (1T1R) cells and as shown in FIG. Figures 4 to 8B Generally configured in.

[0016] Fig.11 Show Fig. 10A and Fig. 10B Cross-sectional views of some alternative embodiments of IC chips are shown.

[0017] Fig.12 Show Fig. 10A and Fig. 10B A top view layout of some embodiments of an IC chip is shown.

[0018] Figures 13 to 23 A series of cross-sectional views illustrating some embodiments of methods for forming an IC chip including a plurality of memory cells integrated into individual 1T1R cells and including an interface layer composed of a semiconductor material.

[0019] Fig.24 Show Figures 13 to 23 Flowcharts of some embodiments of the illustrated method.

[0020] [Description of Figure Numbers]

[0021] 100, 200a, 200b, 400, 500, 600, 700, 800a, 900a, 900b, 900c, 900d, 900e, 1000a, 1000b, 1100, 1300, 1400, 1500, 1600, 1700, 1800, 1900, 2000, 2100, 2200, 2300: cross-sectional views;

[0022] 102: storage unit;

[0023] 104, 104l: interface layer;

[0024] 106: top electrode;

[0025] 108: ferroelectric layer;

[0026] 110: bottom electrode;

[0027] 112: bias circuit system;

[0028] 114: access transistor;

[0029] 116: control circuit system;

[0030] 202: first intermediate layer;

[0031] 204: Second intermediate layer;

[0032] 206: The third intermediate layer;

[0033] 300a, 300b: I / V diagram;

[0034] 302, 302', 304, 304', 306, 306', 308, 308', A-A', E, F: lines;

[0035] 402: Internal connection structure;

[0036] 404, 404a: wiring;

[0037] 404b: bottom electrode wiring;

[0038] 404t: top electrode wiring;

[0039] 406: through hole;

[0040] 406b: bottom electrode via (BEVA);

[0041] 406t: top electrode via (TEVA);

[0042] 408: BEVA barrier;

[0043] 410: BEVA body;

[0044] 412: Hard mask;

[0045] 414: Sidewall spacer structure;

[0046] 416: intermetal dielectric (IMD) layer;

[0047] 416b: second IMD layer;

[0048] 418: first etch stop layer;

[0049] 420: second etch stop layer;

[0050] 422: buffer layer;

[0051] 502: first shared side wall;

[0052] 504: second shared side wall;

[0053] 702: bottom electrode barrier;

[0054] 800b, 1200: top view of the layout;

[0055] 1002: 1T1R cell;

[0056] 1004: drain region;

[0057] 1005: Contact piece;

[0058] 1006: drain side conductive path;

[0059] 1008: substrate;

[0060] 1010: Trench isolation structure;

[0061] 1014: interlayer dielectric (ILD) layer;

[0062] 1016: surrounding areas;

[0063] 1018: Peripheral devices;

[0064] 1020: source / drain region;

[0065] 1022, 1032: gate electrodes;

[0066] 1024, 1030: gate dielectric layer;

[0067] 1026: source side conductive path;

[0068] 1028: source region;

[0069] 110l: bottom electrode layer;

[0070] 106l: top electrode layer;

[0071] 108l: ferroelectric layer;

[0072] 1202: storage array;

[0073] 2102: through hole opening;

[0074] 2202: Wiring opening;

[0075] 2400: Block diagram;

[0076] 2402, 2404, 2406, 2408: operation;

[0077] BL: bit line;

[0078] Tf, Ti: thickness;

[0079] SL: source line;

[0080] X, Y, Z: direction. DETAILED DESCRIPTION

[0081] The present disclosure provides many different embodiments or examples for implementing the different features of the present disclosure. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are only examples and are not intended to be limiting. For example, the following description of forming a first feature on or on a second feature may include an embodiment in which the first feature and the second feature are formed to be in direct contact, and may also include an embodiment in which an additional feature may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the present disclosure may reuse reference numbers and / or letters in various examples. This repetition is for the purpose of brevity and clarity, rather than representing the relationship between the various embodiments and / or configurations discussed.

[0082] In addition, for ease of description, spatially relative terms such as "beneath," "below," "lower," "above," "upper," and the like may be used herein to describe the relationship of one component or feature to another (other) component or feature as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0083] An integrated circuit (IC) chip may include an interconnect structure and a memory cell located in the interconnect structure. The memory cell includes a bottom electrode, a ferroelectric layer overlying the bottom electrode, a top electrode overlying the ferroelectric layer, and an interface layer (interface layer) directly contacting the ferroelectric layer between one of the top electrode or the bottom electrode and the ferroelectric layer. The interconnect structure includes a bottom electrode wire (bottom electrode wire) located below the memory cell and a top electrode wire (top electrode wire) overlying the memory cell. In addition, the interconnect structure includes a plurality of through holes extending from the bottom electrode wire and the top electrode wire to the bottom electrode and the top electrode, respectively. The interface layer is an insulator that increases the tunneling resistance ratio of the memory cell. That is, the interface layer causes the memory cell to have a larger resistance change between the first polarization and the second polarization of the ferroelectric layer.

[0084] The challenge of the memory cell is that the interface layer has a minimum thickness and a high band gap. Such a high band gap can be, for example, greater than about 3 electron volts (eV) or can be some other suitable value. Materials with a high band gap reduce the current flowing through the memory cell. As a result, the combination of the ferroelectric and interface layers can have a low tunneling current density during a read operation due to the combined thickness of the layers and the high band gap. Reducing the thickness of the ferroelectric layer and the interface layer may suppress the bulk properties (e.g., dielectric constant) of the layers, which may be undesirable. Low tunneling current density during a read operation can negatively affect the performance of the memory cell. For example, low tunneling current density during a read operation may result in an increase in sensing time.

[0085] Various embodiments of the present disclosure relate to a memory cell including an interfacial layer composed of a semiconductor material, more specifically, a semiconductor material having a band gap of less than 3 electron volts (eV) directly between a ferroelectric layer and one of a top electrode or a bottom electrode.

[0086] Because the interfacial layer is composed of a semiconductor material having a lower band gap than the insulating material, the tunneling current density of the memory cell can be increased relative to a memory cell having an interfacial layer composed of an insulating material. By increasing the tunneling current density of the ferroelectric layer and the interfacial layer, the performance of the ferroelectric layer and thus the memory cell can be enhanced. For example, the sensing time during a read operation can be reduced. In addition, the memory cell is compatible with pre-existing manufacturing processes, thereby enabling the use of the memory device cell for embedded memory applications.

[0087] Reference Figure 1 , a cross-sectional view 100 of some embodiments of a memory cell 102 is provided, wherein an interface layer 104 is configured to separate a top electrode 106 from a ferroelectric layer 108. In some embodiments, the interface layer 104 may additionally or alternatively be referred to as a barrier layer, an intermixing layer, a diffusion barrier layer, the like, or any combination thereof. The memory cell 102 may be or may include, for example, a metal-ferroelectric-semiconductor-metal (MFSM) cell, a ferroelectric tunnel junction (FTJ), the like, or any combination thereof.

[0088] The ferroelectric layer 108 overlies the bottom electrode 110, the interface layer 104 overlies the ferroelectric layer 108, and the top electrode 106 overlies the interface layer 104. In addition, the interface layer 104 is composed of a semiconductor material. For example, in some embodiments, the interface layer 104 is one of the following materials or includes one of the following materials: crystalline elemental silicon (Si) or amorphous elemental silicon (Si), crystalline elemental germanium (Ge) or amorphous elemental germanium (Ge), gallium arsenide (GaAs), silicon carbide (SiC), tin selenide (SnSe), cadmium telluride (CdTe), indium phosphide (InP), boron arsenide (BAs), similar materials or combinations thereof.

[0089] In some embodiments, the interfacial layer 104 is composed of a material with a band gap of less than 3 electron volts. For example, in some embodiments, the interfacial layer 104 is composed of germanium with a band gap of 0.8 electron volts. An interfacial layer 104 with a high band gap (e.g., greater than 3 electron volts) may negatively affect the performance of the memory cell 102. The interfacial layer 104 has a thickness T between the ferroelectric layer 108 and the top electrode 106. i , thereby reducing the current density of the memory cell 102 while providing other beneficial effects (e.g., increasing the resistance difference between the two ferroelectric states of the memory cell). If the interface layer 104 has a high band gap, the current density through the memory cell 102 can be further reduced. The reduction in current density will increase the sensing time of the memory cell 102 and slow down the operation of the integrated chip to an undesirable level. Therefore, using a material with a low band gap (e.g., a semiconductor material with a band gap of less than 3 electron volts) to form the interface layer 104 can increase the current density of the memory cell 102, thereby reducing the sensing time of the read operation. In some embodiments, the memory cell 102 is configured to function as a ferroelectric tunneling junction, and the ferroelectric tunneling junction is configured to support 100 amperes per square centimeter (A / cm 2 ) tunneling current density. In some embodiments, the bias circuitry 112 is configured to supply a bias voltage to the ferroelectric tunneling junction, thereby causing the tunneling current density to be greater than or equal to 100 amperes per square centimeter. In some embodiments, no dielectric material is directly present between the top electrode 106 and the bottom electrode 110. In other embodiments, due to the formation of a native oxide layer in the semiconductor layer or some other process, a dielectric material may be directly present between the top electrode 106 and the bottom electrode 110. However, the dielectric layer results in a reduction in current density and an increase in sensing time, and the thickness does not exceed 20 angstroms.

[0090] In some embodiments, the interface layer 104 has a thickness T of about 50 angstroms to 1200 angstroms, about 50 angstroms to 600 angstroms, about 600 angstroms to 1200 angstroms, or some other suitable value. i If the thickness T i If the thickness T is too small (eg, less than 50 angstroms), the bulk properties (eg, dielectric constant) of the interface layer 104 may be reduced or undesirably altered. i If it is too large (eg, greater than 1200 angstroms), the resistance of the interface layer 104 may be too high and may result in a low current density through the memory cell 102 .

[0091] In some embodiments, the thickness T of the ferroelectric layer 108 is f is about 50 angstroms to 400 angstroms, about 50 angstroms to 200 angstroms, about 200 angstroms to 400 angstroms, or some other suitable value.f If the thickness T is too small (e.g., less than 50 angstroms) or too large (e.g., greater than 400 angstroms), the ferroelectric layer 108 may have no remanent polarization or may have an unusable small remanent polarization. f If the thickness T of the interface layer 104 is too large (eg, greater than 400 angstroms), the resistance of the ferroelectric layer 108 may be too high and may result in low current flowing through the memory cell 102. In some embodiments, the thickness T of the interface layer 104 may be too large (eg, greater than 400 angstroms). i The thickness T of the ferroelectric layer 108 f The thickness ratio between them ranges from a ratio of 1:1 to a ratio of 3:1.

[0092] During operation of the memory cell 102, the remnant polarization of the ferroelectric layer 108 is used to represent a bit of data. For example, a positive remnant polarization may represent a binary "0" and a negative remnant polarization may represent a binary "1", or vice versa.

[0093] To set the remnant polarization to a positive polarity, a first write voltage is applied across the ferroelectric layer 108 from the top electrode 106 to the bottom electrode 110 by the bias circuit system 112. To set the remnant polarization to a negative polarity, a second write voltage is applied across the ferroelectric layer 108 from the top electrode 106 to the bottom electrode 110. The first write voltage has an opposite polarity to the second write voltage and has a magnitude that exceeds a coercive voltage (e.g., exceeds a voltage threshold at which the remnant polarization of the ferroelectric layer changes). In some embodiments, to read the polarity of the remnant polarization, a read voltage that is less than the coercive voltage is applied across the ferroelectric layer 108 by the bias circuit system 112. The current through the memory cell 102 is then read, and the current will vary based on the remnant polarization of the ferroelectric layer 108. For example, in Figure 1 In the configuration shown in , when the remnant polarization is set to negative polarity, the read voltage will draw a higher current. In some embodiments, there may be several orders of magnitude difference between the current through the memory cell 102 at positive and negative polarities. Therefore, the current can be used to discern the polarity of the remnant polarization.

[0094] In some embodiments, the memory cell 102 of the IC chip being read is controlled using an access transistor 114. The access transistor 114 is controlled by the bias circuitry 112. In some embodiments, the control circuitry 116 is configured to control the bias circuitry 112 and read the current through the ferroelectric tunneling junction.

[0095] Figure 2A Show Figure 1 A cross-sectional view 200a of an alternative embodiment of a memory cell is shown in which the interface layer 104 is located directly between the ferroelectric layer and the bottom electrode 110. During a read operation, using the same read voltage as in the example given above, the change in order of the interface layer 104 and the ferroelectric layer 108 will result in a higher current being conducted when the remnant polarization is set to a positive polarity.

[0096] In some embodiments, the ferroelectric layer 108 is or includes a binary oxide, a ternary oxide or a ternary nitride, a quaternary oxide, some other suitable ferroelectric material, or any combination thereof. The binary oxide may be or include, for example, hafnium oxide (e.g., hafnia or HfO2) and / or some other suitable binary oxide. The ternary oxide or ternary nitride may be or include, for example, hafnium silicate (e.g., HfSiO x ), hafnium zirconate (e.g., HfZrO x ), barium titanate (e.g., BaTiO3), lead titanate (e.g., PbTiO3), strontium titanate (e.g., SrTiO3), calcium manganite (e.g., CaMnO3), bismuth ferrite (e.g., BiFeO3), aluminum scandium nitride (e.g., AlScN), aluminum gallium nitride (e.g., AlGaN), aluminum yttrium nitride (e.g., AlYN), some other suitable ternary oxide and / or ternary nitride, or any combination thereof. The quaternary oxide may be or may include, for example, barium strontium titanate (e.g., BaSrTiO x ) and / or some other suitable quaternary oxide.

[0097] In some embodiments, the top electrode 106 and the bottom electrode 110 are or include one of copper (Cu), platinum (Pt), aluminum copper (AlCu), gold (Au), silver (Ag), titanium (Ti), tantalum (Ta), tungsten (W), another conductive material, a similar material, or any combination thereof. In some embodiments, the top electrode 106 includes the same material as the bottom electrode 110. In other embodiments, the top electrode 106 includes one or more materials different from the bottom electrode 110. In some embodiments, the bottom electrode 110 is a first electrode and the top electrode 106 is a second electrode. In some embodiments, the top electrode 106 and the bottom electrode 110 are composed of titanium, the ferroelectric layer 108 is composed of hafnium oxide, and the interface layer 104 is composed of elemental silicon.

[0098] Figure 2B Show Figure 2AA cross-sectional view 200b of an alternative embodiment of a memory cell is shown, wherein a first intermediate layer 202, a second intermediate layer 204, and a third intermediate layer 206 separate the layers of the memory cell. In some embodiments, the first intermediate layer 202, the second intermediate layer 204, and the third intermediate layer 206 are sandwiched between different layers of the memory cell 102. In still other embodiments, the first intermediate layer 202, the second intermediate layer 204, and the third intermediate layer 206 are or include a first material that is the same material as the layer in contact with the corresponding top surface and a second material that is the same material as the layer in contact with the corresponding bottom surface of the intermediate layer. For example, in some embodiments, the first intermediate layer 202 is or includes the same material (first material) as the top electrode 106 and the same material (second material) as the ferroelectric layer 108. In still other embodiments, the first material is distributed throughout the first intermediate layer 202 in a gradient from a first surface in contact with the top electrode 106 to a second surface in contact with the ferroelectric layer 108. For example, in an embodiment where the top electrode is made of titanium (Ti) and the ferroelectric layer is made of hafnium oxide (HfO2), the first intermediate layer may include approximately 99% Ti and 1% HfO2 at the first surface in mole percent. In addition, the first intermediate layer may include approximately 1% Ti and 99% HfO2 at the second surface in mole percent. In yet other embodiments, the ratio of HfO2 to Ti may increase monotonically from the first surface to the second surface, and the ratio of Ti to HfO2 may decrease monotonically from the second surface to the first surface. For example, "monotonically" may be linearly, exponentially, quadratically, or according to a Gaussian function, etc. In some embodiments, the second intermediate layer 204 and the third intermediate layer 206 may have similar material gradients between the material of the ferroelectric layer 108, the material of the interface layer 104, and the material of the bottom electrode 110. In some embodiments, the first intermediate layer 202, the second intermediate layer 204, and the third intermediate layer 206 have a thickness of less than 1 nanometer. In yet other embodiments, the thickness of the first intermediate layer 202, the thickness of the second intermediate layer 204, and the thickness of the third intermediate layer 206 are measured from a position where the molar percentage of the first material is approximately 99% to a position where the molar percentage of the second material is approximately 99%. In some embodiments, the first intermediate layer 202, the second intermediate layer 204, and the third intermediate layer 206 are formed during an annealing process performed on the memory cell 102 to increase the amount of the ferroelectric layer 108 in the orthorhombic phase.

[0099] Figure 3A and Figure 3B Show Figure 1 and Figure 2A Various I / V graphs 300a, 300b of some embodiments of memory cells are shown. Figure 3A The dielectric constant and remnant polarization of the Figure 1 302 and 304 represent memory cells where the semiconductor material has a lower dielectric constant, while lines 306 and 308 represent memory cells where the semiconductor material has a higher dielectric constant. Lines 302 and 306 each represent the read current of the ferroelectric layer 108 (see Figure 1 ) has a positive polarity at various voltages. Line 304 and line 308 each represent the current flowing through the memory cell 102 when the ferroelectric layer 108 (see Figure 1 ) has a negative polarity and flows through the memory cell 102 at various voltages.

[0100] Figure 3B The dielectric constant and remnant polarization of the Figure 2A . Lines 302' and 304' represent memory cells where the semiconductor material has a lower dielectric constant, while lines 306' and 308' represent memory cells where the semiconductor material has a higher dielectric constant. Lines 302' and 306' each represent the read current of the ferroelectric layer 108 (see Figure 2A ) has a negative polarity. Line 304' and line 308' each represent the current flowing through the memory cell 102 at various voltages when the ferroelectric layer 108 (see Figure 2A ) has a positive polarity and flows through the memory cell 102 at various voltages.

[0101] The dielectric constant of the interface layer 104 affects the difference in resistance between the positive polarity and the negative polarity. The dielectric constant of the interface layer 104 depends on the material used to form the interface layer 104 and the crystalline properties of the material. For example, in some cases, the interface layer 104 may be an amorphous interface layer (e.g., amorphous silicon), and in other cases, the interface layer 104 may be a crystalline interface layer (e.g., crystalline silicon) having a lower dielectric constant than the amorphous interface layer.

[0102] Reference Figure 4 ,supply Figure 1 A cross-sectional view 400 of some embodiments of the memory cell 102 is shown, wherein the memory cell 102 is integrated into an interconnect structure 402 of an IC chip.

[0103] The top electrode wiring 404t overlies the memory cell 102, and a top electrode via (TEVA) 406t extends downward from the top electrode wiring 404t to the top electrode 106. The bottom electrode wiring 404b is located below the memory cell 102, and a bottom electrode via (BEVA) 406b extends upward from the bottom electrode wiring 404b to the bottom electrode 110. The BEVA 406b includes a BEVA barrier 408 and a BEVA body 410. The BEVA barrier 408 cups the underside of the BEVA body 410 to separate the BEVA body 410 from the bottom electrode wiring 404b. In an alternative embodiment, the BEVA barrier 408 is omitted so that the BEVA body 410 directly contacts the bottom electrode wiring 404b. The BEVA barrier 408 may, for example, be configured to block or otherwise substantially reduce diffusion of material from the bottom electrode wire 404 b to the bottom electrode 110 .

[0104] In some embodiments, the top electrode wire 404t, TEVA 406t, and bottom electrode wire 404b are or include copper, aluminum, tungsten, a similar material, or any combination thereof. In some embodiments, the BEVA body 410 is or includes: (1) the same material as the top electrode wire 404t, TEVA 406t, bottom electrode wire 404b, or any combination thereof; (2) the same material as the BEVA barrier 408; (3) the same material as the bottom electrode 110; (4) some other suitable material; or (5) any combination thereof. In some embodiments, the BEVA barrier 408 is or includes titanium nitride, platinum, aluminum copper, gold, titanium, tantalum, tantalum nitride, tungsten, tungsten nitride, a similar material, or any combination thereof. In some embodiments, the thickness of the BEVA barrier 408 is about 50 angstroms to 200 angstroms or some other suitable value.

[0105] A hard mask 412 overlies the top electrode 106, and the TEVA 406t extends from the top electrode wire 404t through the hard mask 412 to the top electrode 106. In an alternative embodiment, the hard mask 412 is omitted. The hard mask 412 may be or may include, for example, titanium nitride, silicon oxide, silicon nitride, silicon carbonitride, silicon oxynitride, a metal oxide, some other suitable material, or any combination thereof. The metal oxide may be or may include, for example, titanium oxide, aluminum oxide, some other suitable metal oxide, or any combination thereof. In some embodiments, the thickness of the hard mask 412 is about 50 angstroms to 400 angstroms or some other suitable value.

[0106] If targeted Figure 1As illustrated, the interface layer 104 is configured to space the top electrode 106 from the ferroelectric layer 108. This in turn can enhance the performance of the ferroelectric layer 108.

[0107] The bottom electrode 110, the ferroelectric layer 108, the interface layer 104, the top electrode 106 and the hard mask 412 share a shared width and form a pair of shared sidewalls on opposite sides of the memory cell 102, respectively. That is, the ferroelectric layer has a first outer sidewall, the interface layer has a second outer sidewall, and the bottom electrode and the top electrode have a third outer sidewall and a fourth outer sidewall aligned with the first outer sidewall and the second outer sidewall. In addition, the shared sidewall has a planar profile, but alternatively may have a curved profile or other suitable profiles.

[0108] A sidewall spacer structure 414 is provided on the shared sidewall. The sidewall spacer structure 414 may be or may include, for example, titanium nitride, silicon oxide, silicon nitride, silicon carbonitride, silicon oxynitride, metal oxide, some other suitable material, or any combination thereof. The metal oxide may be or may include, for example, titanium oxide, aluminum oxide, some other suitable metal oxide, or any combination thereof. In some embodiments, the sidewall spacer structure 414 is the same material as the hard mask 412.

[0109] A plurality of intermetal dielectric (IMD) layers 416 surround the bottom electrode wiring 404b and the top electrode wiring 404t, respectively. In addition, the IMD layer 416 is separated by a first etch stop layer 418, a second etch stop layer 420, and a buffer layer 422. The first etch stop layer 418 surrounds the BEVA 406b and is between the bottom electrode wiring 404b and the memory cell 102 in a vertical direction. The second etch stop layer 420 and the buffer layer 422 cover the first etch stop layer 418 and the memory cell 102 and conform to the first etch stop layer 418 and the memory cell 102. In addition, the second etch stop layer 420 is located between the buffer layer 422 and the memory cell 102.

[0110] The IMD layer 416 may be or may include, for example, silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, silicon carbonitride, some other suitable dielectric, or any combination thereof. The first etch stop layer 418 and / or the second etch stop layer 420 may be or may include, for example, metal nitride, metal oxide, metal carbide, silicon nitride, silicon oxide, silicon carbide, silicon oxynitride, some other suitable dielectric, or any combination thereof. In some embodiments, the first etch stop layer 418 and the second etch stop layer 420 are the same material. In some embodiments, the thickness of the first etch stop layer 418 is about 150 angstroms to 350 angstroms or some other suitable value. In some embodiments, the thickness of the second etch stop layer 420 is about 50 angstroms to 300 angstroms or some other suitable value. The buffer layer 422 may be or may include, for example, tetraethylorthosilicate (TEOS) oxide and / or some other suitable dielectric. In some embodiments, the buffer layer 422 has a thickness of approximately 50 angstroms to 300 angstroms or some other suitable value.

[0111] Reference Figure 5 ,supply Figure 4 A cross-sectional view 500 of some alternative embodiments of the memory cell 102 is shown in which the top electrode width is reduced relative to the remainder of the memory cell 102 .

[0112] The bottom electrode 110, the ferroelectric layer 108, and the interface layer 104 share a first shared width and form a pair of first shared sidewalls 502 on opposite sides of the memory cell 102, respectively. That is, the outermost sidewalls of the interface layer 104 are aligned with the outermost sidewalls of the bottom electrode 110 and the bottommost sidewalls of the ferroelectric layer 108. In addition, the top electrode 106 and the hard mask 412 share a second shared width and form a pair of second shared sidewalls 504 on opposite sides of the memory cell 102, respectively. That is, the outermost sidewalls of the top electrode 106 are aligned with the outermost sidewalls of the hard mask 412. The second shared width is smaller than the first shared width, and the second shared sidewalls 504 are laterally located between the first shared sidewalls 502. In addition, the second shared sidewalls 504 are covered by the sidewall spacer structure 414 overlying the interface layer 104. The first shared sidewalls and the second shared sidewalls have a planar profile, but other suitable profiles are also possible.

[0113] Reference Figure 6 ,supply Figure 5A cross-sectional view 600 of some alternative embodiments of the memory cell 102 is shown, wherein the BEVA barrier 408 and the BEVA body 410 are omitted. Instead, the bottom electrode 110 directly contacts the bottom electrode wire 404b. The bottom electrode 110, the ferroelectric layer 108, the interface layer 104, the top electrode 106, and the hard mask 412 are recessed at the bottom electrode wire 404b, and the TEVA 406t is laterally offset relative to the center of the memory cell 102. In some embodiments, the bottom surface of the top electrode 106 extends below the top surface of the bottom electrode 110.

[0114] Reference Figure 7 ,supply Figure 4 A cross-sectional view 700 of some alternative embodiments of the memory cell 102 is shown, wherein the BEVA 406b (including the BEVA barrier 408 and the BEVA body 410), the sidewall spacer structure 414, the second etch stop layer 420, and the hard mask 412 are omitted. As such, the memory cell 102 extends from the bottom electrode wiring 404b. In addition, the bottom electrode barrier 702, the bottom electrode 110, the ferroelectric layer 108, and the interface layer 104 cover the bottom side of the top electrode 106. For example, the bottom electrode barrier 702, the bottom electrode 110, the ferroelectric layer 108, and the interface layer 104 can each have a U-shaped profile or similar profile. The bottom electrode barrier 702 is located between the bottom electrode 110 and the bottom electrode wiring 404b and can be, for example, Figure 4 BEVA barrier 408 is illustrated. In some embodiments, top electrode 106, interface layer 104, and ferroelectric layer 108 are located between the inner sidewalls of bottom electrode 110. In some embodiments, top electrode 106 is located directly between the outer sidewalls of ferroelectric layer 108, the outer sidewalls of interface layer 104, and the outer sidewalls of bottom electrode 110 and directly above the upper surface of ferroelectric layer 108, the upper surface of interface layer 104, and the upper surface of bottom electrode 110.

[0115] Reference Fig. 8A ,supply Figure 4 A cross-sectional view 800a of some alternative embodiments of the memory cell 102 is shown, wherein the BEVA 406b (including the BEVA barrier 408 and the BEVA body 410), the sidewall spacer structure 414, the second etch stop layer 420, and the hard mask 412 are omitted. Thus, the memory cell 102 extends from the bottom electrode wire 404b. In addition, the additional wire 404a is located below the TEVA 406t and flush with the bottom electrode wire 404b, and the top electrode 106, the interface layer 104, and the ferroelectric layer 108 form a sidewall spacer structure.

[0116] The sidewall spacer structure is on some portions of the outer sidewalls of the bottom electrode 110 and overlies the first etch stop layer 418. In addition, the sidewall spacer structure has a pair of spacer sections, and the bottom electrode 110 is arranged between the pair of spacer sections. The TEVA 406t extends to a portion of the top electrode 106 at one of the sections and further extends into the first etch stop layer 418. In at least some embodiments, the spacer sections are continuous with each other outside the cross-sectional view 800a. The interface layer 104 and the ferroelectric layer 108 have an L-shaped portion at each of the spacer sections. The L-shaped portion of the ferroelectric layer 108 wraps around the bottom corner of the corresponding L-shaped portion of the interface layer 104, and the L-shaped portion of the interface layer 104 wraps around the bottom corner of the corresponding portion of the top electrode 106. In some embodiments, the top electrode 106 extends in a closed path around the bottom electrode 110 , and wherein the bottom electrode 110 has an outer sidewall extending to a height flush with the highest point of the top electrode 106 .

[0117] Reference Figure 8B ,supply Fig. 8A A top view layout diagram 800b of some embodiments of the memory cell 102 is shown. In addition, the top view layout of the TEVA 406t is shown with a dotted line (phantom) overlying the memory cell 102. For example, the top view layout of the TEVA 406t can be taken along the line AA'. Fig. 8A Cross-sectional view 800a is shown. Top electrode 106 extends in a closed path around interface layer 104, interface layer 104 extends in a closed path around ferroelectric layer 108, and ferroelectric layer 108 extends in a closed path around bottom electrode 110. Memory cell 102 has a square top view layout or a rectangular top view layout, but may alternatively have a circular top view layout or some other suitable top view layout. TEVA 406t has a square top view layout or a rectangular top view layout, but may alternatively have other suitable top view layouts.

[0118] Reference 9A to 9E ,supply Figure 2A Some cross-sectional views 900a to 900e of some alternative embodiments of the memory cell 102 are shown, wherein the interface layer 104 is located at the bottom electrode 110, such as Figure 2A In cross-sectional views 900a to 900e, a Figure 2A Some alternative embodiments of the storage unit 102 are shown, wherein the storage unit 102 is respectively as follows Figure 4 , Figure 5 , Figure 6 , Figure 7 and Fig. 8A Generally configured in.

[0119] Reference Fig. 10A, a cross-sectional view 1000a of some embodiments of an IC chip including a memory cell 102 is provided, wherein a plurality of memory cells 102 are integrated into respective 1T1R cells 1002. The memory cells 102 are each Figure 1 The counterpart of the storage unit 102 is illustrated.

[0120] A plurality of 1T1R cells 1002 include respective drain regions 1004 and respective drain-side conductive paths 1006. The drain regions 1004 are doped regions of a substrate 1008 and each have a doping type opposite to an adjacent region of the substrate 1008. In addition, the drain regions 1004 are electrically isolated by trench isolation structures 1010 and partially define access transistors 114 (partially shown) for individually selecting the memory cells 102. The trench isolation structures 1010 extend to the top of the substrate 1008 and include silicon oxide and / or some other suitable dielectric material. The substrate 1008 may be, for example, a bulk silicon substrate or some other suitable semiconductor substrate.

[0121] The drain-side conductive path 1006 electrically couples the drain region 1004 to the memory cell 102 and is formed by the interconnect structure 402 in which the memory cell 102 is arranged. The interconnect structure 402 includes a plurality of wirings 404 and a plurality of vias 406 alternately stacked into a plurality of wiring levels and a plurality of via levels. The plurality of wirings 404 include a top electrode wiring 404t and a bottom electrode wiring 404b. In some embodiments, the top electrode wiring 404t corresponds to a bit line BL. The plurality of vias 406 include a TEVA 406t and a BEVA 406b. A level with a plurality of contacts 1005 extends between the plurality of wirings 404 and a substrate 1008 in an interlayer dielectric (ILD) layer 1014, and a level with vias 406 and a level with wirings 404 are located in an IMD layer 416 above the ILD layer 1014. The wiring 404 and the vias 406 except for the BEVA 406b may be or may include, for example, copper, aluminum, some other suitable metal, or any combination thereof. The BEVA 406b may be, for example, Figure 3A and Figure 3B The counterpart of BEVA 406b described.

[0122] A peripheral region 1016 on one side of the 1T1R cell 1002 accommodates a plurality of peripheral devices 1018 (only one of the peripheral devices 1018 is shown). The peripheral device 1018 may be, for example, a metal-oxide-semiconductor field-effect transistor (MOSFET), a fin field-effect transistor (finFET), a gate-all-around field-effect transistor (GAA FET), or some other suitable type of semiconductor device. Each of the peripheral devices 1018 includes a pair of source / drain regions 1020 located in the substrate 1008 and a gate electrode 1022 and a gate dielectric layer 1024 stacked between the source / drain regions 1020.

[0123] Reference Fig. 10B , along with the intercept Fig. 10A The axis orthogonal to the axis of the cross-sectional view 1000a provides Fig. 10A A cross-sectional view 1000b of some embodiments of an IC chip is shown. The 1T1R cell 1002 includes a respective memory cell 102, a respective drain-side conductive path 1006, a respective access transistor 114, and a respective source-side conductive path 1026. The memory cells 102 are each for Figure 1 The counterpart of the storage unit 102 is illustrated.

[0124] The access transistor 114 is located between the substrate 1008 and the interconnect structure 402, and is located on the substrate 1008 and is electrically isolated by the trench isolation structure 1010. The access transistor 114 includes a respective drain region 1004, a respective source region 1028, a respective gate dielectric layer 1030, and a respective gate electrode 1032. The gate electrode 1032 overlies the gate dielectric layer 1030 and forms a word line in some embodiments. The drain region 1004 and the source region 1028 are doped regions of the substrate 1008 and each has a doping type opposite to that of adjacent regions of the substrate 1008. In addition, the drain region 1004 and the source region 1028 are respectively bordered by the gate electrode 1032. The access transistor 114 can be, for example, a MOSFET, a finFET, a GAA FET, or some other suitable type of semiconductor device.

[0125] The drain-side conductive path 1006 electrically couples the drain region 1004 to the memory cell 102, and the source-side conductive path 1026 electrically couples the source region 1028 to a source line SL. The drain-side conductive path 1006 and the source-side conductive path 1026 are formed by the plurality of wirings 404 and the plurality of vias 406. In some embodiments, the source line SL and the bit line BL electrically couple the memory cell 102 to the bias circuit system 112 and the control circuit system 116. In yet other embodiments, the gate electrode 1032 is also coupled to the bias circuit system 112.

[0126] Despite using Figure 1 The memory cell embodiment shown in Fig. 10A and Fig. 10B ,However Figure 1 , FIG. 2A to FIG. 2B , Figure 4 , Figure 5 , Figure 6 , Figure 7 , Fig. 8A and 9A to 9E Any of the memory cell embodiments in the embodiment of FIG. 1 is also feasible in alternative embodiments. For example, Fig.11 As shown in the cross-sectional view 1100, Fig. 10A and Fig. 10B The storage unit 102 shown may alternatively be Fig. 8A Generally configured in.

[0127] Reference Fig.12 ,supply Fig. 10A and Fig. 10B The top view layout diagram 1200 of some embodiments of the IC chip is shown. For example, the top view can be taken along lines E and F respectively. Fig. 10A The cross-sectional view 1000a and Fig. 10B The IC chip includes a plurality of 1T1R cells 1002 arranged in a plurality of columns and a plurality of rows, thereby forming a memory array 1202. A plurality of peripheral devices 1018 surround the memory array 1202 at a peripheral region 1016 of the IC chip. The peripheral devices 1018 may, for example, implement read / write circuitry and / or other suitable circuitry for operating the 1T1R cells 1002.

[0128] Reference Figures 13 to 23 , a series of cross-sectional views 1300 to 2300 of some embodiments of a method for forming an IC chip including a plurality of memory cells 102, wherein the memory cells are integrated into respective 1T1R cells 1002 and include an interface layer 104 composed of a semiconductor material. The cross-sectional views 1300 to 2300 may correspond, for example, to Fig. 10A and Fig. 10B The IC chip shown.

[0129] like Fig.13 As shown in the cross-sectional view 1300 of FIG. 1 , an interconnect structure 402 electrically coupled to a plurality of access transistors 114 (only partially shown) and a peripheral device 1018 is partially formed over the plurality of access transistors 114 and the peripheral device 1018. The access transistors 114 are individual to and located at the plurality of 1T1R cells 1002 being formed, and the peripheral device 1018 is located at a peripheral region 1016 of the IC chip being formed. The access transistors 114 and the peripheral device 1018 are located on and partially formed by the substrate 1008 and are separated by a trench isolation structure 1010 in the substrate 1008. For example, the access transistors 114 and the peripheral device 1018 may be as described for Fig. 10A and Fig. 10B The general description.

[0130] The interconnect structure 402 includes a plurality of wirings 404 and a plurality of through holes 406 alternately stacked in a wiring level and a through hole level in a dielectric structure. The dielectric structure includes an ILD layer 1014 surrounding a plurality of contacts 1005 and a first IMD layer 416a located on the ILD layer 1014. The plurality of wirings 404 include a plurality of bottom electrode wirings 404b along the top surface of the interconnect structure 402. The bottom electrode wirings 404b are individual to the 1T1R cell 1002 being formed and are respectively located at the 1T1R cell 1002. In addition, the bottom electrode wirings 404b are respectively electrically coupled to the drain regions 1004 of the access transistors 114. The first IMD layer 416a may be formed, for example, by and / or using chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), some other suitable deposition process, or any combination thereof. The wiring 404, the via 406, and the contact 1005 may be formed, for example, by and / or using CVD, PVD, ALD, electroless plating, electroplating, some other suitable deposition process, or any combination thereof.

[0131] like Fig.14As shown in the cross-sectional view 1400 of FIG. 1 , a first etch stop layer 418 is deposited or otherwise formed on the interconnect structure 402. It should be noted that the lower portion of the interconnect structure 402 is omitted in this and subsequent figures for the sake of compactness. The first etch stop layer 418 is a dielectric and can be deposited, for example, by CVD, PVD, ALD, some other suitable deposition process, or any combination thereof.

[0132] Also by Fig.14 1400 shows that, in some embodiments, a plurality of BEVAs 406b are formed that extend through the first etch stop layer 418 to the bottom electrode wiring 404b, respectively. The BEVAs 406b include respective BEVA bodies 410 and respective BEVA barriers 408, each of which covers the bottom side of the BEVA bodies 410. The BEVA bodies 410 and / or the BEVA barriers 408 may be formed, for example, by and / or using CVD, PVD, ALD, some other suitable deposition process, or any combination thereof. In some embodiments, instead of forming the BEVAs 406b, a plurality of gaps are etched into the etch stop layer to expose the bottom electrode wiring 404b.

[0133] like Fig.15 As shown in the cross-sectional view 1500 of FIG. 1 , a bottom electrode layer 1101 is deposited on the BEVA 406b and the first etch stop layer 418. The bottom electrode layer 1101 may be deposited, for example, by CVD, PVD, ALD, some other suitable deposition process, or any combination thereof. In an embodiment without the BEVA 406b, the bottom electrode layer 1101 is deposited directly onto the bottom electrode line 404b.

[0134] Also by Fig.15 The cross-sectional view 1500 of 1500 shows that a ferroelectric layer 1081 is deposited on the bottom electrode layer 1101. The deposition may be performed, for example, by CVD, PVD, ALD, a similar process, or any combination thereof.

[0135] like Fig.16 As shown in the cross-sectional view 1600 of , an interface layer 1041 is deposited on the ferroelectric layer 1081, and a top electrode layer 1061 is deposited on the interface layer 1041. The interface layer 1041 can be deposited, for example, by CVD, PVD, ALD, some other suitable deposition process, or any combination thereof. Similarly, the top electrode layer 1061 can be deposited, for example, by CVD, PVD, ALD, some other suitable deposition process, or any combination thereof.

[0136] In some embodiments, the interface layer 1041 is or includes elemental silicon, elemental germanium, gallium arsenide, silicon carbide, tin selenide, cadmium telluride, indium phosphide, boron arsenide, some other suitable semiconductor, or any combination thereof. The interface layer 1041 may have a band gap of less than or equal to 3 electron volts. For example, the interface layer 1041 may be or include elemental germanium having a band gap of 0.8 electron volts.

[0137] In some embodiments, the interface layer 1041 has an amorphous structure to reduce the dielectric constant. Alternatively, in some embodiments, the interface layer 1041 has a crystalline structure to increase the dielectric constant. By changing the dielectric constant, the I / V reading of the memory cell 102 (see FIG. 3 ) during a read operation is also changed.

[0138] like Fig.17 As shown in the cross-sectional view 1700 of FIG. 17 , a hard mask 412 is formed for each 1T1R cell 1002 being formed. As described below, the hard mask 412 has a pattern of the memory cell 102 being formed. The process for forming the hard mask 412 may, for example, include depositing a hard mask layer on the top electrode layer 1061 and then patterning the hard mask layer into the hard mask 412. The deposition may be performed, for example, by CVD, PVD, ALD, some other suitable deposition process, or any combination thereof. The patterning may be performed, for example, by a lithography / etching process or some other suitable patterning process.

[0139] like Fig.18As shown in the cross-sectional view 1800 of , etching is performed into the top electrode layer 106l, the interface layer 104l, the ferroelectric layer 108l, and the bottom electrode layer 110l with the hard mask 412 in place. In some embodiments where the hard mask 412 is formed by a photolithography / etching process, the etching of the photolithography / etching process is the same as the etching performed into the top electrode layer 106l and other layers. The etching stops on the first etch stop layer 418, whereby the first etch stop layer 418 serves as an etch stop for the etching. In addition, the etching transfers the pattern of the hard mask 412 to the top electrode layer 106l, the interface layer 104l, the ferroelectric layer 108l, and the bottom electrode layer 110l, thereby forming the memory cell 102 overlying and located on the BEVA 406b, respectively. Respective segments of the top electrode layer 106l at the memory cell 102 are hereinafter referred to as top electrodes 106, and individual segments of the bottom electrode layer 110l at the memory cell 102 are hereinafter referred to as bottom electrodes 110. In some embodiments, patterning of the interface layer 104l and the ferroelectric layer 108l delineates respective segments of the interface layer 104 and segments of the ferroelectric layer 108 for the memory cell 102, wherein the bottom electrode 110, the top electrode 106, and the segments of the interface layer 104 and the ferroelectric layer 108 directly between the bottom electrode 110 and the top electrode 106 form the memory cell 102 of a plurality of memory cells.

[0140] In some embodiments, etching back is performed into the top electrode layer, the interface layer, and the ferroelectric layer to remove multiple horizontally extending segments of the top electrode layer, multiple horizontally extending segments of the interface layer, and multiple horizontally extending segments of the ferroelectric layer and to form a sidewall structure surrounding some portions of the multiple bottom electrodes, wherein the sidewall structure includes the top electrode and segments of the interface layer and segments of the ferroelectric layer.

[0141] like Fig.19 As shown in the cross-sectional view 1900 of , a sidewall spacer structure 414 is formed on the shared sidewall formed by the hard mask 412, the top electrode 106, the interface layer 104, the ferroelectric layer 108 and the bottom electrode 110. The process for forming the sidewall spacer structure 414 may, for example, include: 1) depositing a sidewall spacer layer on the memory cell 102; and 2) etching back the sidewall spacer layer. However, other suitable processes are also feasible. The sidewall spacer layer may be deposited, for example, by CVD, PVD, ALD, some other suitable deposition process, or any combination thereof.

[0142] like Figure 20 to Figure 23 As shown in the cross-sectional views 2000 to 2300 , the interconnect structure 402 is completed on and around the memory cell 102 .

[0143] like Fig. 20As shown in the cross-sectional view 2000 of , a second etch stop layer 420 is formed, which covers the memory cell 102 and is laterally offset relative to the peripheral area 1016. The process for forming the second etch stop layer 420 in this way may, for example, include: 1) depositing the second etch stop layer 420 covering the memory cell 102 and the peripheral area 1016; and 2) patterning the second etch stop layer 420 to remove the second etch stop layer 420 from the peripheral area 1016. However, other suitable processes are also feasible. The second etch stop layer 420 can be deposited, for example, by CVD, PVD, ALD, some other suitable deposition process, or any combination thereof. The patterning can be performed, for example, by a photolithography / etching process or some other suitable process.

[0144] like Fig.21 As shown in the cross-sectional view 2100 of FIG. 2 , a buffer layer 422 and a second IMD layer 416 b are deposited, and the buffer layer 422 and the second IMD layer 416 b cover the memory cell 102 and the peripheral region 1016 on the first etch stop layer 418 and the second etch stop layer 420. In an alternative embodiment, the buffer layer 422 is omitted. The buffer layer 422 and / or the second IMD layer 416 b can be deposited, for example, by CVD, PVD, ALD, some other suitable deposition process, or any combination thereof.

[0145] Also by Fig.21 The cross-sectional view 2100 of FIG. 2 shows that the second IMD layer 416 b, the buffer layer 422, and the first etch stop layer 418 and the second etch stop layer 420 are patterned to form a plurality of via openings 2102. Each via opening 2102 exposes the top electrode 106 at the memory cell 102 and the wiring 404 at the peripheral area 1016, respectively. The patterning can be performed, for example, by one or more photolithography / etching processes and / or some other suitable patterning processes. In some embodiments, the first etch stop layer 418 and the second etch stop layer 420 are used as etch stops when etching is performed in the photolithography / etching process.

[0146] like Fig. 22 As shown in the cross-sectional view 2200 of , the second IMD layer 416b is further patterned to form a plurality of wire openings 2202 overlapping the via openings 2102. The patterning may be performed, for example, by a photolithography / etching process and / or some other suitable patterning process.

[0147] like Fig.23 As shown in the cross-sectional view 2300, a pair of through hole openings 2102 (see for example Fig.21 ) and wiring opening 2202 (see e.g. Fig. 22) and a plurality of additional wirings 404 and a plurality of additional through-holes 406 filled therein. The plurality of additional wirings 404 respectively fill the wiring openings 2202 and include a plurality of top electrode wirings 404t, which are individual to the memory cells 102 and respectively overlie the memory cells 102. The plurality of additional through-holes 406 respectively fill the through-hole openings 2102 and include a plurality of TEVAs 406t, which are individual to the top electrodes 106 and respectively located at the top electrodes 106. In addition, the TEVAs 406t extend from the top electrode wirings 404t to the top electrodes 106, respectively.

[0148] The process for forming the additional wiring 404 and the additional via 406 may, for example, include: 1) depositing a metal layer that fills the via opening 2102 and the wiring opening 2202; and 2) performing planarization into the metal layer and the second IMD layer 416b until the top surface of the second IMD layer 416b is flush with the top surface of the metal layer. However, other suitable processes are also possible. The metal layer may be deposited, for example, by CVD, PVD, ALD, electroless plating, electroplating, some other suitable deposition process, or any combination thereof.

[0149] Although referring to a method Figures 13 to 23 , however, it should be understood that Figures 13 to 23 The structures shown in are not limited to the methods described, but can exist independently of the methods described. Figures 13 to 23 The steps are described as a series of actions, however, it should be understood that in other embodiments, the order of the actions may be changed. For example, instead of forming the interface layer 1041 between the ferroelectric layer 1081 and the top electrode layer 1061, the interface layer 1041 may be formed between the bottom electrode layer 1101 and the ferroelectric layer 1081.

[0150] although Figures 13 to 23 The ferroelectric layer 1081 is shown and described as a specific set of actions, however, some of the actions shown and / or described may be omitted in other embodiments. In addition, other embodiments may include actions that are not shown and / or described. For example, annealing may be performed after the ferroelectric layer 1081 is deposited, thereby causing the ferroelectric layer 1081 to have a higher ratio of orthorhombic phase (relative to other crystalline phases), thereby increasing the residual polarization (2Pr) of the memory cell 102 and improving data retention.

[0151] Reference Fig.24 ,supply Figures 13 to 23 Block diagram 2400 of some embodiments of the method is shown. Fig.24The block diagram 2400 shown is shown and described herein as a series of actions or events, but it should be understood that the order of the actions or events shown should not be interpreted as limiting. For example, in addition to the order shown and / or described herein, some actions may also be performed in a different order and / or simultaneously with other actions or events. In addition, it may not be necessary for all of the actions shown to implement one or more aspects or embodiments described herein, and one or more of the actions illustrated herein may be implemented in one or more separate actions and / or stages.

[0152] At 2402, a bottom electrode is formed over the substrate. See e.g. Fig.15 and Fig.18 .

[0153] At 2404, an interface layer, a ferroelectric layer, and a top electrode layer are deposited and stacked over the substrate. See, e.g. Figure 15 to Figure 16 .

[0154] At 2406, the top electrode layer is patterned to form a top electrode. See, e.g. Fig.18 .

[0155] At 2408, the interface layer and the ferroelectric layer are patterned to delineate respective segments of the interface layer and the ferroelectric layer for a memory cell, wherein a bottom electrode, a top electrode, and a segment of the interface layer and the ferroelectric layer directly between the bottom electrode and the top electrode form the memory cell, and wherein the interface layer is composed of a semiconductor material having a band gap of less than 3 electron volts. See, e.g. Fig.18 .

[0156] In some embodiments, the present disclosure provides an integrated chip, which includes: a first electrode made of metal; a second electrode disposed on the first electrode; a ferroelectric layer located between the first electrode and the second electrode; and an interface layer separating the ferroelectric layer from the first electrode, the interface layer comprising a semiconductor material and configured to separate the first electrode from the ferroelectric layer.

[0157] In one embodiment, the integrated chip further comprises a bias circuit system, wherein the first electrode, the second electrode, the ferroelectric layer and the interface layer are configured to function as a ferroelectric tunneling junction, and wherein the bias circuit system is configured to supply a tunneling current density greater than or equal to 100 amperes per square centimeter across the ferroelectric tunneling junction. In one embodiment, the integrated chip further comprises an intermediate layer, the intermediate layer having a first surface facing the interface layer and a second surface facing the ferroelectric layer and comprising a material of the ferroelectric layer and a material of the interface layer, and wherein the ratio of the material of the ferroelectric layer to the material of the interface layer increases monotonically from the first surface to the second surface. In one embodiment, in the integrated chip, the interface layer has a first thickness greater than or equal to 50 angstroms and less than or equal to 1200 angstroms, and wherein the ferroelectric layer has a second thickness greater than or equal to 50 angstroms and less than or equal to 400 angstroms. In one embodiment, in the integrated chip, the ratio of the first thickness to the second thickness is between a ratio of 1 to 1 and a ratio of 3 to 1. In one embodiment, in the integrated chip, the semiconductor material is amorphous silicon. In one embodiment, in the integrated chip, the interface layer has a band gap of less than 3 electron volts.

[0158] In some embodiments, the present disclosure provides an integrated circuit, which includes: a first electrode located on a substrate; a ferroelectric layer disposed on the first electrode; a second electrode disposed on the ferroelectric layer; and an interface layer disposed on the first electrode and separating the first electrode from the ferroelectric layer, wherein no dielectric material exists directly between the first electrode and the second electrode.

[0159] In one embodiment, in the integrated circuit, the ferroelectric layer has a first outer sidewall, the interface layer has a second outer sidewall, and one of the first electrode or the second electrode has a third outer sidewall aligned with the first outer sidewall and the second outer sidewall. In one embodiment, in the integrated circuit, the second electrode is directly between the outer sidewall of the ferroelectric layer, the outer sidewall of the interface layer, and the outer sidewall of the first electrode and directly above the upper surface of the ferroelectric layer, the upper surface of the interface layer, and the upper surface of the first electrode. In one embodiment, in the integrated circuit, the second electrode extends around the first electrode in a closed path, and the first electrode has an outer sidewall extending to a height flush with the highest point of the second electrode. In one embodiment, the integrated circuit further includes a bias circuit system, the bias circuit system is coupled to the first electrode and the second electrode and is configured to supply a tunneling current through the interface layer, the tunneling current having a tunneling current density equal to or greater than 100 amperes per square centimeter. In one embodiment, in the integrated circuit, the bottom surface of the second electrode extends below the top surface of the first electrode.

[0160] In some embodiments, the present disclosure provides a method comprising: forming a bottom electrode on a substrate; depositing an interface layer, a ferroelectric layer, and a top electrode layer stacked on the substrate; patterning the top electrode layer to form a top electrode; and patterning the interface layer and the ferroelectric layer to delineate segments of the interface layer and segments of the ferroelectric layer, respectively, for a memory cell, wherein the bottom electrode, the top electrode, and the segments of the interface layer and the segments of the ferroelectric layer directly between the bottom electrode and the top electrode form the memory cell, and wherein the interface layer is composed of a semiconductor material having a band gap of less than 3 electron volts.

[0161] In one embodiment, the method further comprises: forming a semiconductor device before forming the bottom electrode, the semiconductor device overlying the substrate and partially defined by the substrate; and forming an interconnect structure, the interconnect structure comprising a plurality of wirings and a plurality of vias alternately stacked into a plurality of wiring levels and a plurality of via levels, wherein the interconnect structure electrically couples the semiconductor device to the memory cell. In one embodiment, in the method, the patterning of the top electrode layer, the interface layer, and the ferroelectric layer comprises: performing etching back on the top electrode layer, the interface layer, and the ferroelectric layer to remove horizontally extending segments of the top electrode layer, horizontally extending segments of the interface layer, and horizontally extending segments of the ferroelectric layer and forming a sidewall structure surrounding some portions of the bottom electrode, wherein the sidewall structure comprises the top electrode, the segments of the interface layer, and the segments of the ferroelectric layer. In one embodiment, the method further includes annealing the integrated chip after depositing the top electrode layer, thereby forming an intermediate layer between the interface layer and the ferroelectric layer, the intermediate layer extending from a first surface facing the interface layer to a second surface facing the ferroelectric layer, the first surface having a molar percentage of 99% of the same material as the interface layer, and the second surface having a molar percentage of 99% of the same material as the ferroelectric layer. In one embodiment, the method further includes: depositing a bottom electrode layer before depositing the interface layer, the ferroelectric layer, and the top electrode layer; and patterning the bottom electrode layer to form the bottom electrode after patterning the interface layer, the ferroelectric layer, and the top electrode layer. In one embodiment, in the method, the patterning of the bottom electrode layer, the interface layer, and the ferroelectric layer further includes: forming a first mask on top of the top electrode layer; and etching the bottom electrode layer, the ferroelectric layer, and the interface layer with the first mask in position to perform the patterning of the bottom electrode layer, the ferroelectric layer, and the interface layer. In one embodiment, the method further comprises depositing a bottom electrode layer before depositing the interface layer, the ferroelectric layer, and the top electrode layer, wherein the interface layer, the ferroelectric layer, and the top electrode layer are deposited directly between inner sidewalls of the bottom electrode layer.

[0162] Finally, it should be noted that the above embodiments are only used to illustrate the technical solution of the utility model, rather than to limit it. Although the utility model has been described in detail with reference to the aforementioned embodiments, ordinary technicians in this field should understand that they can still modify the technical solutions recorded in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not make the essence of the corresponding technical solution deviate from the scope of the technical solution of the embodiments of the utility model.

Claims

1. An integrated chip, characterized in that: include: a first electrode comprising a metal; A second electrode, disposed on the first electrode; a ferroelectric layer, located between the first electrode and the second electrode; as well as An interface layer separates the ferroelectric layer from the second electrode, wherein the interface layer includes a semiconductor material and is configured to separate the second electrode from the ferroelectric layer.

2. The integrated chip according to claim 1, characterized in that: It further includes a bias circuit system, wherein the first electrode, the second electrode, the ferroelectric layer and the interface layer are configured to function as a ferroelectric tunneling junction, and wherein the bias circuit system is configured to supply a tunneling current density greater than or equal to 100 amperes per square centimeter across the ferroelectric tunneling junction.

3. The integrated chip according to claim 1, characterized in that: The interface layer has a first thickness greater than or equal to 50 angstroms and less than or equal to 1200 angstroms, and the ferroelectric layer has a second thickness greater than or equal to 50 angstroms and less than or equal to 400 angstroms.

4. The integrated chip according to claim 1, characterized in that: The interfacial layer has a band gap of less than 3 electron volts.

5. An integrated circuit, characterized in that: include: A first electrode, located on the substrate; A ferroelectric layer is disposed on the first electrode; A second electrode is disposed on the ferroelectric layer; as well as An interface layer is disposed on the first electrode and separates the first electrode from the ferroelectric layer, wherein no dielectric material exists directly between the first electrode and the second electrode.

6. The integrated circuit according to claim 5, characterized in that The ferroelectric layer has a first outer sidewall, the interface layer has a second outer sidewall, and one of the first electrode or the second electrode has a third outer sidewall aligned with the first outer sidewall and the second outer sidewall.

7. The integrated circuit according to claim 5, characterized in that The second electrode is directly located between the outer wall of the ferroelectric layer, the outer wall of the interface layer and the outer wall of the first electrode and directly located above the upper surface of the ferroelectric layer, the upper surface of the interface layer and the upper surface of the first electrode.

8. The integrated circuit according to claim 5, characterized in that The second electrode extends around the first electrode in a closed path, and the first electrode has an outer sidewall extending to a height flush with a highest point of the second electrode.

9. The integrated circuit according to claim 5, characterized in that: Further included is a bias circuit system coupled to the first electrode and the second electrode and configured to supply a tunneling current through the interface layer, the tunneling current having a tunneling current density equal to or greater than 100 amperes per square centimeter.

10. The integrated circuit according to claim 5, characterized in that Wherein a bottom surface of the second electrode extends below a top surface of the first electrode.

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