Super-nodule VDMOS device for improving depletion layer
By introducing wide and narrow metal conductive columns and etching deep grooves into the low-doped N-epitaxial layer of VDMOS devices for epitaxial growth of P-type semiconductors, forming a superjunction structure, solving the problem of longitudinal widening of the depletion layer between the metal gate and the metal drain in VDMOS devices, achieving more efficient current transmission and reducing production costs.
Patent Information
- Application Number
- CN202421534287.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-07-01
- Publication Date
- 2025-04-18
- Estimated Expiration
- 2034-07-01
AI Technical Summary
The depletion layer between the metal gate and the metal drain has a longitudinal widening problem, resulting in current and voltage overshoot.
By introducing a wide metal conductive column and a narrow metal conductive column in the low-doped N-epitaxial layer, the length of the narrow conductive column is greater than that of the wide conductive column, and the deep groove is etched in the second low-doped N-epitaxial layer for P-type semiconductor epitaxial growth, forming an equidistantly distributed narrow metal conductive column to form a superjunction structure.
This design can alleviate the longitudinal broadening of the depletion layer between the metal gate and the metal drain, reduce the on-resistance of the semiconductor device, improve working efficiency, and simplify production steps and reduce costs.
Smart Images
Figure CN222776519U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the technical field of VDMOS devices, and more specifically discloses a super-junction VDMOS device with an increased depletion layer. Background Art
[0002] VDMOS device, the full name is Vertical Double-diffused Metal-Oxide-Semiconductor, that is, vertical double diffused metal oxide semiconductor device. When the voltage applied to the gate is large enough, the insulating layer (oxide layer) between the gate and the channel will be broken down to form a conductive channel. At this time, the charge can flow from the source to the drain to achieve the conduction of the device. When the voltage on the gate decreases, the insulating layer is restored, the conductive channel is disconnected, and the device stops conducting. VDMOS devices are widely used in power management, electric vehicle control, industrial control and other fields.
[0003] With the continuous advancement of science and technology and the innovation of materials, the characteristics of VDMOS devices are constantly improving, and the performance of VDMOS devices can be further enhanced, providing important support for the development of modern electronic technology. Summary of the invention
[0004] The utility model provides a super-junction VDMOS device with an increased depletion layer, which can solve the problems raised in the above-mentioned background technology.
[0005] To solve the above technical problems, according to one aspect of the utility model, more specifically, a super-nodule VDMOS device with an increased depletion layer comprises a highly doped N+ substrate and a silicon dioxide oxide insulating layer, wherein a first low-doped N-epitaxial layer is epitaxially grown on the upper surface of the highly doped N+ substrate, first metal conductive pillars are formed on both sides of the interior of the first low-doped N-epitaxial layer by ion implantation, a second low-doped N-epitaxial layer is formed on the upper surface of the first low-doped N-epitaxial layer by ion implantation, and a deep groove is etched inside the second low-doped N-epitaxial layer, and a second metal conductive pillar is epitaxially grown inside the deep groove, a P-type body region is formed on both sides of the interior of the second low-doped N-epitaxial layer by ion implantation, and a highly doped N+ source region is implanted inside each of the P-type body regions, a highly doped P+ region is implanted on one side of the P-type body region close to the highly doped N+ source region, a depth difference is formed between the highly doped N+ source region and the P-type body region, and the depth of the highly doped N+ source region is less than the depth of the P-type body region;
[0006] A U-groove is etched inside the second low-doped N-epitaxial layer and near the two P-type body regions, the U-groove is concave in shape, a polysilicon region is injected into the inside of the U-groove near the bottom, a second metal gate is deposited above the inside of the U-groove, and the depth of the second metal gate is greater than the depth of the polysilicon region, a first metal gate is deposited on the upper surface of the second metal gate, the silicon dioxide oxide insulating layer is laid on the upper surface of the second low-doped N-epitaxial layer, a first long groove and a second long groove are provided on the upper surface of the silicon dioxide oxide insulating layer, and the first metal gate is embedded in the inside of the first long groove, and a metal source is embedded in the inside of the second long groove.
[0007] As a preferred technical solution in some embodiments, the metal source is deposited on the upper surface of the P-type body region and the highly doped N+ source region.
[0008] In some embodiments, as a preferred technical solution, a metal drain is deposited on the back side of the highly doped N+ substrate.
[0009] In some embodiments, as a preferred technical solution, there is a depletion layer between the highly doped N+ source region and the P-type body region.
[0010] In some embodiments, as a preferred technical solution, the second metal conductive column is a P-type semiconductor.
[0011] The beneficial effects of the super-junction VDMOS device with improved depletion layer in the utility model are as follows:
[0012] In the utility model, a wide metal conductive column is introduced into the lower low-doped N-epitaxial layer, and a narrow metal conductive column is introduced into the upper low-doped N-epitaxial layer. The length of the narrow metal conductive column is greater than the wide metal conductive column, which can alleviate the longitudinal widening of the depletion layer between the metal gate and the metal drain, and is beneficial to alleviate current and voltage overshoot.
[0013] In the utility model, deep grooves are etched in the upper low-doped N-epitaxial layer, and then P-type semiconductor epitaxial growth is performed in the deep grooves. Only one deep groove etching and one epitaxial growth are required, thereby simplifying the steps and reducing the production cost.
[0014] In the utility model, narrow metal conductive pillars distributed at equal distances form a super junction structure in a low-doped N-epitaxial layer, which can reduce the on-resistance of semiconductor devices and improve working efficiency. BRIEF DESCRIPTION OF THE DRAWINGS
[0015] The utility model is further described in detail below with reference to the accompanying drawings and specific implementation methods.
[0016] Figure 1 It is a schematic diagram of the structure of the super-nodule VDMOS device of the utility model.
[0017] In the figure: 1. first low-doped N-epitaxial layer; 2. highly-doped N+ substrate; 3. metal drain; 4. first metal conductive pillar; 5. second low-doped N-epitaxial layer; 6. second metal conductive pillar; 7. polysilicon region; 8. U-groove; 9. second metal gate; 10. first metal gate; 11. silicon dioxide oxide insulating layer; 12. highly-doped N+ source region; 13. metal source; 14. P-type body region; 15. deep trench; 16. first long trench; 17. second long trench; 18. P+ region. DETAILED DESCRIPTION
[0018] The present invention will be described in detail below with reference to the accompanying drawings and in combination with embodiments. It should be noted that the embodiments and features in the embodiments of the present application can be combined with each other without conflict.
[0019] According to the attached Figure 1 , a super-junction VDMOS device with an increased depletion layer is provided, comprising a highly doped N+ substrate 2 and a silicon dioxide oxide insulating layer 11, a first low-doped N-epitaxial layer 1 is epitaxially grown on the upper surface of the highly doped N+ substrate 2, first metal conductive pillars 4 are formed on both sides of the interior of the first low-doped N-epitaxial layer 1 by ion implantation, a second low-doped N-epitaxial layer 5 is formed on the upper surface of the first low-doped N-epitaxial layer 1 by ion implantation, a deep groove 15 is etched inside the second low-doped N-epitaxial layer 5, a second metal conductive pillar 6 is epitaxially grown inside the deep groove 15, a P-type body region 14 is formed on both sides of the interior of the second low-doped N-epitaxial layer 5 by ion implantation, a highly doped N+ source region 12 is implanted inside each P-type body region 14, a highly doped P+ region 18 is implanted on one side of the P-type body region 14 close to the highly doped N+ source region 12, a depth difference is formed between the highly doped N+ source region 12 and the P-type body region 14, and the depth of the highly doped N+ source region 12 is less than the depth of the P-type body region 14;
[0020] A U-groove 8 is etched inside the second low-doped N-epitaxial layer 5 and near the two P-type body regions 14. The U-groove 8 is concave in shape. The polysilicon region 7 is injected into the U-groove 8 near the bottom. A second metal gate 9 is deposited above the inside of the U-groove 8, and the depth of the second metal gate 9 is greater than the depth of the polysilicon region 7. A first metal gate 10 is deposited on the upper surface of the second metal gate 9. A silicon dioxide oxide insulating layer 11 is laid on the upper surface of the second low-doped N-epitaxial layer 5. A first long groove 16 and a second long groove 17 are provided on the upper surface of the silicon dioxide oxide insulating layer 11, and the first metal gate 10 is embedded in the first long groove 16, and a metal source 13 is embedded in the second long groove 17. A first metal conductive column 4 is introduced into the first low-doped N-epitaxial layer 1, and a second metal conductive column 6 is introduced into the second low-doped N-epitaxial layer 5. The length of the second metal conductive column 6 is greater than that of the first metal conductive column 4, which can alleviate the longitudinal widening of the depletion layer between the metal gate (the first metal gate 10 and the second metal gate 9) and the metal drain 3, and is beneficial to alleviate current and voltage overshoot.
[0021] There is an insulating layer between the second metal gate 9 and the U groove 8. When the voltage applied to the metal gate is large enough, the insulating layer between the gate and the U groove 8 will be broken down to form a conductive channel. This conductive channel allows charges to flow from the metal source 13 to the metal drain 3, thereby achieving device conduction.
[0022] Furthermore, in the present embodiment, the depth of the deep trench 15 is 40 microns; conventionally, multiple epitaxial growths are performed to grow the second low-doped N-epitaxial layer 5, and each epitaxial growth is accompanied by an injection of the second metal conductive column 6, and the steps are cumbersome. Now, by etching the deep trench 15 in the second low-doped N-epitaxial layer 5 and then performing epitaxial growth of a P-type semiconductor in the deep trench 15, only one deep trench etching and one epitaxial growth are required, thereby simplifying the steps and reducing the production cost.
[0023] Furthermore, the metal source 13 is deposited on the upper surface of the P-type body region 14 and the highly doped N+ source region 12 , and the metal source 13 is made of aluminum.
[0024] Furthermore, a metal drain 3 is deposited on the back side of the highly doped N+ substrate 2 .
[0025] Furthermore, there is a depletion layer between the highly doped N+ source region 12 and the P-type body region 14 .
[0026] Furthermore, the second metal conductive column 6 is a P-type semiconductor, and there are multiple second metal conductive columns 6 in the second low-doped N-epitaxial layer 5. Similarly, there are multiple first metal conductive columns 4 in the first low-doped N-epitaxial layer 1. The P-type conductive column and the N-epitaxial layer with deep grooves 15 form a super junction structure, which can reduce the on-resistance of the semiconductor device and improve working efficiency.
[0027] The electrical components that appear in this article are all electrical components that exist in reality.
[0028] Of course, the above description is not a limitation of the present invention, and the present invention is not limited to the above examples. Changes, modifications, additions or substitutions made by ordinary technicians in this technical field within the essential scope of the present invention also fall within the protection scope of the present invention.
Claims
1. A super-junction VDMOS device with an increased depletion layer, comprising a highly doped N+ substrate (2) and a silicon dioxide oxide insulating layer (11), characterized in that: A first low-doped N-epitaxial layer (1) is epitaxially grown on the upper surface of the high-doped N+ substrate (2); first metal conductive pillars (4) are formed on both sides of the interior of the first low-doped N-epitaxial layer (1) by ion implantation; a second low-doped N-epitaxial layer (5) is formed on the upper surface of the first low-doped N-epitaxial layer (1) by ion implantation; a deep groove (15) is etched inside the second low-doped N-epitaxial layer (5); a second metal conductive pillar (6) is epitaxially grown inside the deep groove (15); P-type body regions (14) are formed by ion implantation on both sides of the interior of the second low-doped N-epitaxial layer (5), and a highly-doped N+ source region (12) is implanted into the interior of each of the P-type body regions (14), and a highly-doped P+ region (18) is implanted into the interior of the P-type body region (14) on a side close to the highly-doped N+ source region (12), and a depth difference is formed between the highly-doped N+ source region (12) and the P-type body region (14), and the depth of the highly-doped N+ source region (12) is less than the depth of the P-type body region (14); A U-groove (8) is etched inside the second low-doped N-epitaxial layer (5) and near the two P-type body regions (14), the U-groove (8) being in a concave shape, a polysilicon region (7) is implanted inside the U-groove (8) near the bottom, a second metal gate (9) is deposited above the inside of the U-groove (8), and the depth of the second metal gate (9) is greater than the depth of the polysilicon region (7), a first metal gate (10) is deposited on the upper surface of the second metal gate (9), the silicon dioxide oxide insulating layer (11) is laid on the upper surface of the second low-doped N-epitaxial layer (5), a first long groove (16) and a second long groove (17) are provided on the upper surface of the silicon dioxide oxide insulating layer (11), the first metal gate (10) is embedded inside the first long groove (16), and a metal source electrode (13) is embedded inside the second long groove (17).
2. A super-junction VDMOS device with an increased depletion layer according to claim 1, characterized in that: The metal source electrode (13) is deposited on the upper surfaces of the P-type body region (14) and the highly doped N+ source region (12).
3. A super-junction VDMOS device with an increased depletion layer according to claim 1, characterized in that: A metal drain (3) is deposited on the back side of the highly doped N+ substrate (2).
4. A super-junction VDMOS device with an increased depletion layer according to claim 1, characterized in that: A depletion layer is provided between the highly doped N+ source region (12) and the P-type body region (14).
5. The super-junction VDMOS device with an increased depletion layer according to claim 1, characterized in that: The second metal conductive column (6) is a P-type semiconductor.