Interface circuit system for resolver signal of long-distance cable

Abstract

The utility model belongs to the technical field of power electronics, and particularly relates to an interface circuit system for a resolver signal of a long-distance cable, which comprises an excitation output control circuit and a signal input control circuit, and the excitation output control circuit comprises a wave crest sampling hold circuit, a comparison bias circuit and a gain phase shift circuit. The signal input control circuit comprises a feedback signal circuit and a filter circuit, a sampling feedback signal which is transmitted back to a frequency converter through a cable after induction is sent to the excitation output control circuit, a peak value of the sampling feedback signal is compared with a target peak value, a difference value is obtained, gain operation is carried out through an operational amplifier, excitation voltage fills voltage drop caused by cable internal resistance Rs for compensation, and the excitation output control circuit is used for outputting excitation voltage. Through adjustment of the adjustable excitation phase-shifting capacitor, resonant frequency points between the cables can avoid excitation working frequency, the problem of signal oscillation caused by excitation frequency voltage interlacing of cable internal resistance can be effectively solved, and finally the aim of keeping real signal feedback is achieved through a filter circuit for suppressing common mode and eliminating differential mode noise.

Description

Technical Field

[0001] The utility model belongs to the technical field of power electronics, in particular to an interface circuit system for resolver signals of long-distance cables. Background Art

[0002] As an angle position sensing element, resolver sensors are often installed on motors in industrial applications to feedback the rotor speed, and then calculate the position change or torque of the load through the inverter. The unique structural design of the resolver sensor itself has excellent shock resistance and corrosion resistance and can be used in harsh environments, especially in the mining or special robot industry; for example, when equipment such as excavation, lifting equipment or collection, transmission, machine tool processing, remote robot control, etc. needs to be used in a closed loop with a motor and inverter, resolver sensors are often the preferred sensors. The internal principle of the resolver sensor is as follows Figure 1 shown.

[0003] In actual applications, the motor and resolver sensor are installed together, and the inverter is connected to the motor and resolver sensor through cables to form a closed-loop control. According to electrical requirements, the length of the cable is generally limited to 20 meters. The output of the resolver sensor is a pair of sine-cosine interlaced analog signals, and the input of the sensor is a sine wave alternating voltage with a fixed frequency; when rotating, it senses two sets of coils, and the waveform correspondence is as follows: Figure 2 As shown, the working principle is similar to that of a transformer. The input and output relationship equation of the resolver sensor is as follows:

[0004] Input: E R1-R2 =E Sinωt

[0005] Output: E S1-S3 =K*E R1-R2 *CosΘ

[0006] E S2-S4 =K*E R1-R2 *SinΘ

[0007] Where K is the transformation ratio between output and input, which is generally 0.5 to 0.286.

[0008] Θ is the amplitude modulation, which is tan -1

E S2-S4 / E S1-S3

[0009] Ideally, the two pairs of analog output waveforms of the sensor are transmitted to the decoding chip AD2S1205, and then converted into digital signals and enter the control chip of the inverter. The physical quantity of load angular position, speed or torque is obtained through the internal algorithm. As the cable length increases, the impedance effect of the cable has a greater impact on the real signal of the resolver sensor. And because of the inductive reactance XL synthesized by the cable and the alternating frequency and the capacitive reactance X C The interaction produces resonance, which will amplify the problem of mutual reinforcement of differential mode noise and eliminate the advantage of mutual cancellation of common mode signals.

[0010] The internal resistance of the cable is composed of impedance Rs, inductive reactance X L and capacitive reactance X C Its equivalent circuit is as follows Figure 3 As shown:

[0011] The conductance equation between the two ends is:

[0012]

[0013] The condition for resonance to occur is that the imaginary part is zero. And generally the coil impedance affects R<<ωL,

[0014] but Resonant frequency

[0015] If the excitation operating frequency fw needs to avoid the resonant frequency fo, then change the inductance X in the cable L Or capacitive reactance Xc.

[0016] When the cable of the resolver sensor exceeds the requirement, the resolver signal will be distorted due to the internal resistance of the cable, especially the resolver sensor is an analog positive rotation alternating signal, one part is the fixed frequency of excitation, and the other part is the rotation frequency generated during rotation. When the frequency of the load rotation is higher and the cable distance is longer, the internal impedance, inductive reactance, and capacitive reactance will superimpose with the actual signal, which will not only reduce the voltage but also cause waveform oscillation. The waveform output to the inverter will be unregulated or even unrecognizable, and the data will be biased. Summary of the invention

[0017] In order to solve the technical problems in the prior art, the utility model provides an interface circuit system for resolver signals of long-distance cables, which can feed back data to a decoding chip without being affected by the internal resistance of the cable, and the feedback waveform is consistent with the ideal waveform, ensuring data accuracy.

[0018] The technical solution is as follows: an interface circuit system for a resolver signal of a long-distance cable, characterized in that it includes an excitation output control circuit and a signal input control circuit, the excitation output control circuit includes a peak sampling and holding circuit, a comparison bias circuit, and a gain phase shift circuit, the peak sampling and holding circuit includes a resistor R21 and a resistor R24, one end of which respectively inputs the sampling signals SIN_HI and SIN_LO, the other end of the resistor R21 is connected to one end of a resistor R23, one end of a capacitor C8, and a positive phase input end of an operational amplifier U1B, the The other end of the resistor R24 ​​is connected to one end of the capacitor C9, the other end of the resistor R23 and the SINLO interface of the inverter, the capacitor C8 and the capacitor C9 are both grounded, the inverting input end of the operational amplifier U1B is connected to one end of the resistor R20, the positive electrode of the diode D1, and one end of the resistor R16, the other end of the resistor R20 is connected, the negative electrode of the diode D1 is connected to one end of the resistor R18, the other end of the resistor R18 is connected to the positive electrode of the diode D2 and the output end of the operational amplifier U1B, and the other end of the resistor R16 is connected to one end of the capacitor C7 , one end of the resistor R22, the cathode of the diode D2 and outputs a peak holding voltage Vo.pp, Vo.pp is defined as SinHMax; the comparison bias circuit includes an operational amplifier U1A, the non-inverting input end of the operational amplifier U1A is connected to one end of the resistor R7, the other end of the resistor R7 is connected to one end of the resistor R10 and one end of the resistor R11 and inputs an ideal voltage Ref_V, the inverting input end of the operational amplifier U1A is connected to one end of the resistor R5, one end of the resistor R3, and one end of the capacitor C3, the other end of the resistor R5 inputs the peak holding voltage Si nHMax, the other end of the resistor R3 is connected to the other end of the capacitor C3 and connected to one end of the resistor R8 and the output end of the operational amplifier U1A, the output end of the operational amplifier U1A outputs a positive bias output value OFFSET_P, the other end of the resistor R8 is connected to one end of the resistor R12 and the inverting input end of the operational amplifier U2A, the positive input end of the operational amplifier U2A is grounded through the resistor R13, the other end of the resistor R12 is connected to the output end of the operational amplifier U2A, and the output end of the operational amplifier U2A outputs a negative bias output value OFFSET_N;The gain phase shift circuit includes an operational amplifier IC1A and an operational amplifier IC1B, wherein the non-phase input terminal of the operational amplifier IC1A is connected to one end of a resistor R6, one end of a resistor R9, and one end of a capacitor C4, and the other end of the resistor R6 inputs a positive bias output value OFFSET_P, the inverting input terminal of the operational amplifier IC1A is connected to one end of a resistor R4, one end of a resistor R2, and one end of a capacitor C1, and the other end of the resistor R4 inputs an alternating frequency EXC, the other end of the capacitor C1 is connected to the other end of the resistor R2 and connected to the output terminal of the operational amplifier IC1A, and the non-phase input terminal of the operational amplifier IC1B is connected to one end of a resistor R17, one end of a resistor R19, and one end of a capacitor C 6, the other end of the resistor R17 inputs the positive bias output value OFFSET_N, the inverting input end of the operational amplifier IC1B is connected to one end of the resistor R15, one end of the resistor R14, and one end of the capacitor C5, the other end of the resistor R15 inputs the alternating frequency / EXC, the output ends of the operational amplifier IC1A and the operational amplifier IC1B are connected to the two ends of the adjustable excitation phase shift capacitor Cin; the signal input control circuit includes a feedback signal circuit and a filter circuit, the feedback signal circuit includes a common mode inductor L1 and a common mode inductor L4, the 1st foot of the common mode inductor L1 is connected to one end of the varistor SA1 and connected to the SIN interface of the inverter, 2 The first pin is connected to the other end of the varistor SA1 and connected to the SINLO interface of the inverter, the 3rd pin is connected to one end of the resistor R5, and the 4th pin is connected to one end of the resistor R1. The other end of the resistor R1 is connected to the cathode of the Zener diode ZD1, one end of the capacitor C1, one end of the resistor R2, and one end of the resistor R3. The other end of the resistor R5 is connected to the cathode of the Zener diode ZD2, one end of the capacitor C4, one end of the resistor R4, and the other end of the resistor R3. The other end of the capacitor C1 and the other end of the capacitor C4 are both grounded. The other ends of the resistors R2 and R4 are respectively connected to single-phase LC filters. The 1st pin of the common-mode inductor L4 is connected to the varistor SA 2 and connected to the COS interface of the inverter, 2 pins are connected to the other end of the varistor SA2 and connected to the COSLO interface of the inverter, 3 pins are connected to one end of the resistor R10, 4 pins are connected to one end of the resistor R6, the other end of the resistor R6 is connected to the cathode of the Zener diode ZD3, one end of the capacitor C5, one end of the resistor R7, and one end of the resistor R8, the other end of the resistor R10 is connected to the cathode of the Zener diode ZD4, one end of the capacitor C6, one end of the resistor R9, and the other end of the resistor R8, the other end of the capacitor C5 and the other end of the capacitor C6 are both grounded, and the other ends of the resistor R7 and the resistor R9 are respectively connected to the single-phase LC filter. ;

[0019] Its further feature is that the single-phase LC filter is composed of an inductor and a capacitor connected in parallel and then a diode connected in series.

[0020] After the utility model is adopted, the excitation alternating output voltage {R1, R2} generated by the inverter itself is transmitted to the resolver sensor through the cable, and after induction, the sampling feedback signal of the inverter is transmitted back through the cable, and sent to the excitation output control circuit. The peak value is compared with the target peak value, and the difference is obtained and the gain operation is performed by the operational amplifier, so that the excitation voltage fills the voltage drop caused by the internal resistance Rs of the cable for compensation. In addition, the adjustment of the adjustable excitation phase-shifting capacitor can make the resonant frequency point between the cables avoid the working frequency of the excitation, and can effectively reduce the signal oscillation problem caused by the interlacing effect of the excitation frequency and voltage of the cable internal resistance. Finally, the filter circuit that suppresses common mode and eliminates differential mode noise is used to achieve the purpose of maintaining real signal feedback, that is, the data fed back to the decoding chip is not affected by the internal resistance of the cable, and the feedback waveform is consistent with the ideal waveform, ensuring the accuracy of the data. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 This is the internal schematic diagram of the resolver sensor;

[0022] Figure 2 This is the corresponding diagram of the excitation and output waveform of the resolver sensor;

[0023] Figure 3 is the cable equivalent circuit;

[0024] Figure 4 It is the principle diagram of the peak sampling and holding circuit in the excitation output control circuit of the utility model;

[0025] Figure 5 It is a schematic diagram of a comparison bias circuit and a gain phase shift circuit in the excitation output control circuit of the utility model;

[0026] Figure 6 This is a schematic diagram of a feedback signal circuit in a signal input control circuit of the utility model;

[0027] Figure 7 The schematic diagram of the single-phase LC filter circuit in the signal input control circuit of the utility model is shown in FIG. DETAILED DESCRIPTION

[0028] See Figures 4 to 7 As shown, an interface circuit system for resolver signals of long-distance cables includes an excitation output control circuit and a signal input control circuit; the excitation output control circuit automatically compensates the voltage amplitude of the excitation output {R1, R2} due to the insufficient voltage drop caused by the long cable internal resistance Rs through the circuit; and avoids the inductance X in the cable by adjusting the phase shift of the capacitor value. LThe resonance caused by the alternation of the excitation working frequency fw; the signal input control circuit is the two sets of inductive feedback signals {S1, S3} / {S2, S4} of the resolver sensor, the common-mode and differential-mode influence caused by returning to the interface through a long cable, and the noise spike voltage in the signal transmission process, providing a circuit solution to suppress and eliminate it.

[0029] The specific circuit is as follows:

[0030] The excitation output control circuit includes a peak sampling and holding circuit, a comparison bias circuit, and a gain phase shift circuit. The peak sampling and holding circuit includes a resistor R21 and a resistor R24, each of which inputs sampling signals SIN_HI and SIN_LO respectively at one end. The other end of the resistor R21 is connected to one end of the resistor R23, one end of the capacitor C8, and the positive phase input end of the operational amplifier U1B. The other end of the resistor R24 ​​is connected to one end of the capacitor C9, the other end of the resistor R23 and the SINLO interface of the inverter. The capacitors C8 and C9 are both grounded. The inverting input end of the operational amplifier U1B is connected to one end of the resistor R20, the positive electrode of the diode D1, and one end of the resistor R16. The other end of the resistor R20 is connected to the negative electrode of the diode D1, and the negative electrode of the diode D1 is connected to the resistor R 18, the other end of the resistor R18 is connected to the positive electrode of the diode D2 and the output end of the operational amplifier U1B, the other end of the resistor R16 is connected to one end of the capacitor C7, one end of the resistor R22, and the negative electrode of the diode D2 and outputs the peak holding voltage Vo.pp, Vo.pp is defined as SinHMax; the comparison bias circuit includes the operational amplifier U1A, the non-inverting input end of the operational amplifier U1A is connected to one end of the resistor R7, the other end of the resistor R7 is connected to one end of the resistor R10, one end of the resistor R11 and inputs the ideal voltage Ref_V, the inverting input end of the operational amplifier U1A is connected to one end of the resistor R5, one end of the resistor R3, and one end of the capacitor C3, the other end of the resistor R5 is input with the peak holding voltage SinHMax, the other end of the resistor R3 and The other end of the capacitor C3 is connected to one end of the resistor R8 and the output end of the operational amplifier U1A. The output end of the operational amplifier U1A outputs a positive bias output value OFFSET_P. The other end of the resistor R8 is connected to one end of the resistor R12 and the inverting input end of the operational amplifier U2A. The positive phase input end of the operational amplifier U2A is grounded through the resistor R13. The other end of the resistor R12 is connected to the output end of the operational amplifier U2A. The output end of the operational amplifier U2A outputs a negative bias output value OFFSET_N. The gain phase shift circuit includes an operational amplifier IC1A and an operational amplifier IC1B. The positive phase input end of the operational amplifier IC1A is connected to one end of the resistor R6, one end of the resistor R9, and one end of the capacitor C4. The other end of the resistor R6 inputs the positive bias output value OFFSET_P. The inverting input terminal of the operational amplifier IC1A is connected to one end of the resistor R4, one end of the resistor R2, and one end of the capacitor C1. The other end of the resistor R4 inputs the alternating frequency EXC. The other end of the capacitor C1 is connected to the other end of the resistor R2 and connected to the output terminal of the operational amplifier IC1A. The non-inverting input terminal of the operational amplifier IC1B is connected to one end of the resistor R17, one end of the resistor R19, and one end of the capacitor C6. The other end of the resistor R17 inputs the positive bias output value OFFSET_N. The inverting input terminal of the operational amplifier IC1B is connected to one end of the resistor R15, one end of the resistor R14, and one end of the capacitor C5. The other end of the resistor R15 inputs the alternating frequency / EXC. The output terminals of the operational amplifier IC1A and the operational amplifier IC1B are connected to the two ends of the adjustable excitation phase shift capacitor Cin.

[0031] The excitation alternating output voltage {R1, R2} generated by the inverter itself is transmitted to the resolver sensor through the cable, and then transmitted back to one of the two input signals of the inverter {S1, S3} through the cable after induction, namely the sampling signals SIN_HI and SIN_LO. After the voltage divider resistors R21, R23, R24 and capacitor C8 are used for the first-order filter, the output is sent to the peak sampling circuit composed of the op amp U1B and resistors R16, R18, R20 and diodes D1 and D2, and finally the peak holding voltage Vo.pp is completed by capacitor C7 and resistor R22, which is defined as SinHMax.

[0032] Next, SinHMax is compared with the ideal voltage Ref_V, and the subtraction and gain operations are performed through the op amp U1A and resistors R3, R5, R6, R10, and R11. The capacitor C3 is connected in parallel with R3 as a filter and voltage stabilization capacitor to obtain the positive bias output value OFFSET_P = m*(Ref_V-SinHMax). Where m is the fine-tuned gain value. The other path is reversely calculated through the op amp U2A and resistors R8, R12, and R13 to obtain the negative bias output value OFFSET_N = -OFFSET_P with the same potential but different direction as OFFSET_P.

[0033] The cable internal resistance Rs determines the offset value OFFSET, which can be automatically calculated through the above circuit.

[0034] The alternating frequencies EXC and / EXC directly output by the decoding chip AD2S1205 inside the inverter and the offset values ​​OFFSET_P and OFFSET_N are added respectively, and through the operational amplifiers IC1A and IC1B and the resistors R2, R4, R6, R9 and R14, R15, R17, R19, wherein a filter capacitor is connected in parallel with R2 and R14 respectively, the output REF_P and REF_N are stabilized, so that the output voltages have the function of automatic amplitude gain.

[0035] Finally, connect an excitation phase shift capacitor Cin between REF_P and REF_N, and measure the inductance R of the cable or look up the table. L , excitation fixed frequency f0, the inductive reactance X L =jωL=j2πf0L, combined with the resonant frequency formula Adjust the capacitance of the adjustable excitation phase shift capacitor Cin so that the resonant frequency f0 ≥ 10 * fw excitation fixed frequency, so that the maximum amplitude of the resonant frequency is not at the excitation fixed frequency. The strategy adopted by the excitation phase shift capacitor here is to use a sliding capacitor. The main purpose is to facilitate debugging in different cable lengths and specifications through on-site application technology.

[0036] The signal input control circuit includes a feedback signal circuit and a filter circuit. The feedback signal circuit includes a common-mode inductor L1 and a common-mode inductor L4. Pin 1 of the common-mode inductor L1 is connected to one end of the varistor SA1 and connected to the SIN interface of the inverter, pin 2 is connected to the other end of the varistor SA1 and connected to the SINLO interface of the inverter, pin 3 is connected to one end of the resistor R5, and pin 4 is connected to one end of the resistor R1. The other end of the resistor R1 is connected to the cathode of the Zener diode ZD1, one end of the capacitor C1, one end of the resistor R2, and one end of the resistor R3. The other end of the resistor R5 is connected to the cathode of the Zener diode ZD2, one end of the capacitor C4, one end of the resistor R4, and the other end of the resistor R3. The other end of the capacitor C1 and the other end of the capacitor C4 are both grounded, and the other ends of the resistors R2 and R4 are respectively connected to single Phase LC filter, pin 1 of the common mode inductor L4 is connected to one end of the varistor SA2 and connected to the COS interface of the inverter, pin 2 is connected to the other end of the varistor SA2 and connected to the COSLO interface of the inverter, pin 3 is connected to one end of the resistor R10, and pin 4 is connected to one end of the resistor R6. The other end of the resistor R6 is connected to the cathode of the Zener diode ZD3, one end of the capacitor C5, one end of the resistor R7, and one end of the resistor R8. The other end of the resistor R10 is connected to the cathode of the Zener diode ZD4, one end of the capacitor C6, one end of the resistor R9, and the other end of the resistor R8. The other end of the capacitor C5 and the other end of the capacitor C6 are both grounded. The other ends of the resistors R7 and R9 are respectively connected to the single-phase LC filter. The single-phase LC filter is composed of an inductor and a capacitor connected in parallel and then a diode connected in series. For details, see Figure 7 .

[0037] The {S1, S3} / {S2, S4} signals sensed by the resolver sensor are returned to the SIN / SINLO and COS / COSLO interfaces of the inverter via long cables. First, a varistor SA1 and SA2 are connected in parallel to each other to prevent surge voltage from damaging the equipment. Then, a filter composed of common-mode inductors L1, L4 and capacitors C1, C4, C5, and C6 is connected in series to suppress the common-mode superimposed signal effect; among them, resistor R1 and capacitor C1, resistor R5 and capacitor C4, resistor R6 and capacitor C5, and resistor R10 and capacitor C6 are first-order RC filters. Then, Zener diodes ZD1, ZD2 and ZD3, ZD4 are connected end to end. In addition to voltage limiting protection, they can also play the role of TVS and ESD. Next, voltage division is performed through resistors R2, R3, R4 and R7, R8, R9. Finally, a group of unidirectional LC filters are connected, which are composed of diodes D1~D4 and inductors L2, L3, L5, L6 and capacitors C2, C3, C7, C8 respectively, which can effectively eliminate EMC differential mode noise.

Claims

1. An interface circuit system for resolver signals in long-distance cables, characterized in that: It includes an excitation output control circuit and a signal input control circuit. The excitation output control circuit includes a peak sampling and holding circuit, a comparison bias circuit, and a gain phase shift circuit. The peak sampling and holding circuit includes a resistor R21 and a resistor R24, each of which inputs a sampling signal SIN_HI and SIN_LO at one end. The other end of the resistor R21 is connected to one end of a resistor R23, one end of a capacitor C8, and a positive input end of an operational amplifier U1B. The other end of the resistor R24 ​​is connected to one end of a capacitor C9, the other end of the resistor R23, and the positive input end of an operational amplifier U1B. The SINLO interface of the inverter is connected, the capacitor C8 and the capacitor C9 are both grounded, the inverting input end of the operational amplifier U1B is connected to one end of the resistor R20, the positive electrode of the diode D1, and one end of the resistor R16, the other end of the resistor R20 is connected, the negative electrode of the diode D1 is connected to one end of the resistor R18, the other end of the resistor R18 is connected to the positive electrode of the diode D2 and the output end of the operational amplifier U1B, and the other end of the resistor R16 is connected to one end of the capacitor C7, one end of the resistor R22, and the negative electrode of the diode D2 And output peak holding voltage Vo.pp, Vo.pp is defined as SinHMax; the comparison bias circuit includes an operational amplifier U1A, the non-inverting input terminal of the operational amplifier U1A is connected to one end of the resistor R7, the other end of the resistor R7 is connected to one end of the resistor R10 and one end of the resistor R11 and inputs the ideal voltage Ref_V, the inverting input terminal of the operational amplifier U1A is connected to one end of the resistor R5, one end of the resistor R3, and one end of the capacitor C3, the other end of the resistor R5 inputs the peak holding voltage SinHMax, the resistor The other end of R3 is connected to the other end of the capacitor C3 and connected to one end of the resistor R8 and the output end of the operational amplifier U1A, the output end of the operational amplifier U1A outputs a positive bias output value OFFSET_P, the other end of the resistor R8 is connected to one end of the resistor R12 and the inverting input end of the operational amplifier U2A, the positive input end of the operational amplifier U2A is grounded through the resistor R13, the other end of the resistor R12 is connected to the output end of the operational amplifier U2A, and the output end of the operational amplifier U2A outputs a negative bias output value OFFSET_N;The gain phase shift circuit includes an operational amplifier IC1A and an operational amplifier IC1B. The non-phase input terminal of the operational amplifier IC1A is connected to one end of a resistor R6, one end of a resistor R9, and one end of a capacitor C4. The other end of the resistor R6 inputs a positive bias output value OFFSET_P. The inverting input terminal of the operational amplifier IC1A is connected to one end of a resistor R4, one end of a resistor R2, and one end of a capacitor C1. The other end of the resistor R4 inputs an alternating frequency EXC. The other end of the capacitor C1 is connected to the other end of the resistor R2 and connected to the output terminal of the operational amplifier IC1A. The operational amplifier IC1B The positive input end of the operational amplifier IC1B is connected to one end of the resistor R17, one end of the resistor R19, and one end of the capacitor C6, and the other end of the resistor R17 inputs the positive bias output value OFFSET_N, the inverting input end of the operational amplifier IC1B is connected to one end of the resistor R15, one end of the resistor R14, and one end of the capacitor C5, and the other end of the resistor R15 inputs the alternating frequency / EXC, and the output ends of the operational amplifier IC1A and the operational amplifier IC1B are connected to the two ends of the adjustable excitation phase shift capacitor Cin; the signal input control circuit includes Feedback signal circuit and filter circuit, the feedback signal circuit includes common mode inductor L1 and common mode inductor L4, pin 1 of the common mode inductor L1 is connected to one end of the varistor SA1 and connected to the SIN interface of the inverter, pin 2 is connected to the other end of the varistor SA1 and connected to the SINLO interface of the inverter, pin 3 is connected to one end of the resistor R5, and pin 4 is connected to one end of the resistor R1, and the other end of the resistor R1 is connected to the cathode of the Zener diode ZD1, one end of the capacitor C1, one end of the resistor R2, and the resistor R3 One end, the other end of the resistor R5 is connected to the cathode of the Zener diode ZD2, one end of the capacitor C4, one end of the resistor R4, and the other end of the resistor R3. The other end of the capacitor C1 and the other end of the capacitor C4 are both grounded. The other ends of the resistor R2 and the resistor R4 are respectively connected to the single-phase LC filter. Pin 1 of the common-mode inductor L4 is connected to one end of the varistor SA2 and connected to the COS interface of the inverter, pin 2 is connected to the other end of the varistor SA2 and connected to the COSLO interface of the inverter, pin 3 is connected to one end of the resistor R10, and pin 4 is connected to one end of the resistor R6. The other end of the resistor R6 is connected to the cathode of the Zener diode ZD3, one end of the capacitor C5, one end of the resistor R7, and one end of the resistor R8. The other end of the resistor R10 is connected to the cathode of the Zener diode ZD4, one end of the capacitor C6, one end of the resistor R9, and the other end of the resistor R8. The other end of the capacitor C5 and the other end of the capacitor C6 are both grounded, and the other ends of the resistor R7 and the resistor R9 are respectively connected to the single-phase LC filter. ; 2. The interface circuit system for resolver signals used in long-distance cables according to claim 1, characterized in that: The single-phase LC filter is composed of an inductor and a capacitor connected in parallel and a diode connected in series.

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