Electronic device

Abstract

The utility model provides an electronic device. The electronic device comprises a power chip; the first heat radiator is provided with a continuous side surface and is configured to provide a heat radiation path for the power chip; the packaging adhesive coats the power chip and laterally covers one part of the continuous side surface of the first radiator; wherein the first radiator comprises a first radiating fin, a first circuit layer and a first insulating layer, the first insulating layer is arranged between the radiating fin and the circuit layer, and the first circuit layer is electrically connected with the first terminal of the power chip. According to the electronic device, due to the fact that an external heat dissipation device is omitted, a heat conduction interface can be reduced, the heat dissipation effect can be improved, the manufacturing process can be simplified, and cost can be reduced.

Description

Technical Field

[0001] The present application relates to the field of semiconductor packaging technology, and in particular to an electronic device. Background Art

[0002] Most existing power modules use DBC (Direct Bonded Copper) substrates, which function as conductive circuits, electrical insulation media, and heat conductors. However, the manufacturing process of DBC substrates is complex. They are formed by directly coating thick copper foil on a ceramic substrate by high-temperature sintering, and then engraving circuit patterns on the ceramic substrate by exposure and development. Therefore, the use of DBC substrates increases the cost of power modules.

[0003] In addition, the metal layer of the DBC substrate is relatively thin and has insufficient heat dissipation performance. In order to meet the heat dissipation requirements of the power module, the DBC substrate needs to be connected to an external heat dissipation device. This will require multiple bonding processes in the assembly process of the existing power module, resulting in a complex process and increased costs.

[0004] In addition, an additional thermal interface is generated between the metal layer of the DBC substrate and the external heat dissipation device, and there may be bubbles in the middle of the thermal interface that are not conducive to heat conduction. The existence of this thermal interface will affect the heat dissipation effect. Utility Model Content

[0005] The present application provides an electronic device for reducing costs and improving heat dissipation effects.

[0006] The electronic device proposed in the present application may include: a power chip; a first heat sink having a continuous side surface, configured to provide a heat dissipation path for the power chip; a packaging glue, covering the power chip and laterally covering a portion of the continuous side surface of the first heat sink; wherein the first heat sink includes a first heat sink, a first circuit layer, and a first insulating layer arranged between the heat sink and the circuit layer, and the first circuit layer is electrically connected to the first terminal of the power chip.

[0007] In some optional embodiments, the packaging adhesive covers side surfaces of the first insulating layer.

[0008] In some optional embodiments, the continuous side surface includes a side surface of the first heat sink, and a side surface of the first insulating layer protrudes outward from the side surface of the first heat sink.

[0009] In some optional embodiments, the power chip includes an insulated gate bipolar transistor (IGBT), and the first terminal includes a collector.

[0010] In some optional embodiments, the thickness of the first heat sink is greater than that of the first circuit layer.

[0011] In some optional embodiments, the electronic device further includes a gasket disposed between the power chip and the first circuit layer.

[0012] In some optional embodiments, the plurality of gaskets are respectively disposed between the plurality of power chips and the first circuit layer, and the thicknesses of the plurality of gaskets are not completely the same.

[0013] In some optional embodiments, the electronic device also includes a second heat sink arranged opposite to the first heat sink, the second heat sink includes a second heat sink, a second circuit layer, and a second insulating layer arranged between the second heat sink and the second circuit layer, and the power chip is located between the first circuit layer and the second circuit layer.

[0014] In some optional implementations, the second circuit layer and the first circuit layer have different circuit patterns.

[0015] In some optional embodiments, the second circuit layer is electrically connected to the second terminal of the power chip.

[0016] In some optional embodiments, the power chip includes an insulated gate bipolar transistor (IGBT), and the second terminal includes an emitter and a gate.

[0017] In some optional implementations, the electronic device further includes pins electrically connected to the second circuit layer, and the pins are exposed outside the packaging glue.

[0018] In some optional embodiments, the second circuit layer includes a first area electrically connected to the power chip and a second area electrically connected to the pin, and the first area and the second area are electrically connected by wire bonding.

[0019] In some optional embodiments, the first circuit layer includes a boss, and the power chip is disposed on the boss.

[0020] In some optional embodiments, the gasket is made of copper.

[0021] In some optional embodiments, the packaging adhesive laterally covers a portion of a side surface of the first heat sink.

[0022] As described above, in order to solve the technical problem that the DBC substrate in the existing power module requires an external heat dissipation device, which leads to complex process, increased cost, and increased thermal conductive interface and affects the heat dissipation effect, the present application proposes an electronic device, the heat sink of which is equivalent to an insulating metal substrate (IMS) with a built-in heat sink. The heat sink is an integrated structure formed by directly laminating an insulating layer that performs thermal conductivity and dielectric functions on the heat sink and arranging a circuit layer on the insulating layer (equivalent to replacing the metal substrate in the conventional IMS with a heat sink). Therefore, the electronic device does not require an external heat dissipation device and does not add an additional thermal conductive interface. Therefore, compared with the existing structure of the DBC substrate with an external heat dissipation device, the present application can reduce the thermal conductive interface and improve the heat dissipation effect. It also simplifies the process and reduces costs because an insulating metal substrate with a simpler process technology is used to replace the DBC substrate and the step of connecting an external heat dissipation device is eliminated. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Other features, objects and advantages of the present application will become more apparent by reading the detailed description of non-limiting embodiments made with reference to the following drawings:

[0024] Figure 1 This is a schematic diagram of the longitudinal cross-sectional structure of a current power module using a DBC substrate;

[0025] Figure 2 is a schematic diagram of a longitudinal cross-sectional structure of an embodiment 2a of an electronic device according to the present application;

[0026] Figure 3 is a schematic diagram of a power chip according to an embodiment of the present application;

[0027] Figure 4 is a schematic diagram of a longitudinal cross-sectional structure of an embodiment 4a of an electronic device according to the present application;

[0028] Figure 5 is a schematic diagram of a longitudinal cross-sectional structure of an embodiment 5a of an electronic device according to the present application;

[0029] Figure 6 is a schematic diagram of placing an electronic device in a mold for mold sealing according to an embodiment of the present application;

[0030] Figure 7 is a schematic diagram of placing an electronic device in a mold for mold sealing according to another embodiment of the present application;

[0031] Figure 8-11 It is a schematic diagram of manufacturing steps of an embodiment of the electronic device of the present application.

[0032] Description of reference numerals / symbols:

[0033] 10-DBC substrate; 101-ceramic base; 102-metal layer; 11-power chip; 12-heat dissipation device; 21-power chip; 211-first terminal; 212-second terminal; 22-first radiator; 220-continuous side; 221-first heat sink; 2211-heat dissipation fin; 222-first circuit layer; 2221-boss; 223-first insulating layer; 23-packaging glue; 24-solder; 25-gasket; 26-second radiator; 261-second heat sink; 262-second circuit layer; 263-second insulating layer; 27-pin; 28-wire bonding; 30-mold; 31-recess. DETAILED DESCRIPTION

[0034] The specific implementation methods of the present application are described below in conjunction with the accompanying drawings and embodiments. Through the contents recorded in this specification, those skilled in the art can easily understand the technical problems solved by the present application and the technical effects produced. It is understood that the specific embodiments described herein are only used to explain the relevant inventions and creations, rather than to limit the inventions and creations. In addition, for the convenience of description, only the parts related to the relevant inventions and creations are shown in the accompanying drawings.

[0035] It should be readily understood that the meanings of “on,” “over,” and “over” in this application should be interpreted in the broadest manner, so that “on” not only means “directly on something,” but also means “on something” including the presence of intermediate components or layers therebetween.

[0036] Additionally, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or component to another element or component illustrated in the drawings. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the drawings. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

[0037] The term "layer" as used herein refers to a material portion including an area with a certain thickness. The layer can extend over the entire lower or upper structure, or can have a degree less than the range of the lower or upper structure. In addition, the layer can be a region of a homogeneous or inhomogeneous continuous structure, and its thickness is less than the thickness of the continuous structure. For example, the layer can be located between the top surface and the bottom surface of the continuous structure or between any pair of horizontal planes therebetween. The layer can extend horizontally, vertically and / or along a tapered surface. A substrate can be a layer, one or more layers can be included therein, and / or one or more layers can be present thereon, above and / or below. A layer can include multiple layers. For example, a semiconductor layer can include one or more doped or undoped semiconductor layers, and can have the same or different materials.

[0038] The term "substrate" as used herein refers to a material on which subsequent material layers are added. The substrate itself may be patterned. The material added on top of the substrate may be patterned or may remain unpatterned. In addition, the substrate may include a variety of semiconductor materials, such as silicon, silicon carbide, gallium nitride, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of a non-conductive material, such as glass, plastic, or sapphire wafer, etc. Further alternatively, the substrate may have a semiconductor device or circuit formed therein.

[0039] It should be noted that the structures, proportions, sizes, etc. illustrated in the drawings of the specification are only used to match the contents recorded in the specification for the understanding and reading of those skilled in the art, and are not used to limit the limiting conditions for the implementation of the present application, so they have no substantial technical significance. Any modification of the structure, change in the proportional relationship, or adjustment of the size, without affecting the effects and purposes that can be achieved by the present application, should still fall within the scope of the technical content disclosed in the present application. At the same time, the terms such as "on", "first", "second" and "one" quoted in this specification are only for the convenience of narration, and are not used to limit the scope of the implementation of the present application. The change or adjustment of their relative relationship should also be regarded as the scope of the implementation of the present application without substantially changing the technical content.

[0040] As used herein, the terms "substantially," "substantial," "approximately," and "about" are used to indicate and explain minor variations. For example, when used in conjunction with a numerical value, the above terms may refer to a variation range of less than or equal to ±10% of the corresponding numerical value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. As another example, the thickness of a film or layer is "substantially uniform" and may refer to a standard deviation of less than or equal to ±10% of the average thickness of the film or layer, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. The term "substantially coplanar" may refer to two surfaces that are within tens of microns along the same plane, such as within 40 μm, 30 μm, 20 μm, 10 μm, or 1 μm along the same plane. If, for example, two components overlap or overlap within 200 μm, 150 μm, 100 μm, 50 μm, 40 μm, 30 μm, 20 μm, 10 μm, or 1 μm, then the two components may be considered to be "substantially aligned." If the angle between the two surfaces or components is, for example, 90°±10° (such as ±5°, ±4°, ±3°, ±2°, ±1°, ±0.5°, ±0.1°, or ±0.05°), then the two surfaces or components may be considered to be "substantially perpendicular." When used in conjunction with an event or situation, the terms "substantially," "substantial," "approximately," and "about" may refer to situations where the event or situation occurs exactly as well as situations where the event or situation occurs very approximately.

[0041] It should also be noted that the longitudinal section corresponding to the embodiment of the present application may be a section corresponding to the front view direction, the transverse section may be a section corresponding to the right view direction, and the horizontal section may be a section corresponding to the top view direction.

[0042] In addition, the embodiments and features in the embodiments of the present application may be combined with each other without conflict. The present application will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0043] refer to Figure 1 , Figure 1 This is a schematic diagram of the longitudinal cross-section structure of a power module currently using a DBC substrate. Figure 1As shown, the power module includes a DBC substrate 10, a power chip 11 and a heat sink 12. The DBC substrate 10 includes a ceramic substrate 101, and metal layers 102 respectively arranged on both sides of the ceramic substrate 101, and the metal layers 102 can be patterned to form a circuit pattern. The power chip 11 can be arranged on one side surface of the DBC substrate 10. In order to meet the heat dissipation requirements of the power module, the other side surface of the DBC substrate 10 opposite to the power chip 11 can be externally connected to the heat sink 12. The heat sink 12 and the metal layer 102 of the DBC substrate 10 can be thermally connected through thermal interface materials (TIM).

[0044] The applicant found that Figure 1 The structural scheme of the power module shown requires multiple bonding processes (such as external heat sink 12) in the assembly process, which makes the process complicated and the cost increased. In addition, an additional thermal interface is generated between the metal layer 102 of the DBC substrate 10 and the external heat sink 12, and there may be bubbles in the middle of the thermal interface that are not conducive to heat conduction. The presence of this thermal interface will reduce the heat dissipation efficiency and affect the heat dissipation effect.

[0045] Therefore, it is urgently needed in the industry to provide a structural design solution for a power module that is helpful in simplifying the manufacturing process and reducing costs, as well as improving the heat dissipation effect.

[0046] refer to Figure 2 , Figure 2 2a is a schematic diagram of a longitudinal cross-sectional structure of an embodiment 2a of an electronic device according to the present application. The electronic device 2a of the present application includes but is not limited to a power module.

[0047] like Figure 2 As shown, the electronic device of the present application includes: a power chip (power die) 21, a first heat sink 22 and a packaging glue 23. The first heat sink 22 is thermally connected to the power chip 21, configured to provide a heat dissipation path for the power chip 21, and the first heat sink 22 has a continuous side surface 220. The packaging glue 23 covers the power chip 21 and laterally covers a portion of the continuous side surface 220 of the first heat sink 22.

[0048] Here, the power chip 21 can be a high-power electronic device (for example, a current of tens to thousands of amperes and a voltage of hundreds of volts or more) used for power conversion or control circuits of power equipment. Exemplarily, the power chip 21 includes, but is not limited to, a metal-oxide semiconductor field effect transistor (MOSFET), an insulated gate bipolar transistor (IGBT) and a gallium nitride device (GaN). Among them, MOSFET is a semiconductor device that can be widely used in analog circuits and digital circuits. It controls conductivity through electric field effects to achieve current switching and regulation functions. IGBT is a composite fully controlled voltage-driven power semiconductor device composed of BJT (bipolar transistor) and MOS (insulated gate field effect transistor), which has the advantages of both the high input impedance of MOSFET and the low on-state voltage drop of GTR (power transistor, a type of BJT). GaN is a semiconductor device constructed using gallium nitride materials, such as transistors (HBT), field effect transistors (FET), diodes, etc.

[0049] Here, the first heat sink 22 may include a first heat sink (spreader) 221, a first circuit layer 222, and a first insulating layer 223 disposed between the heat sink 221 and the circuit layer 222. It is easy to understand that the first heat sink 22 in the present application is an improved insulated metal substrate (IMS), which is formed by replacing the metal substrate in the ordinary IMS with the first heat sink 221, and disposing the first insulating layer 223 with thermal conductivity and dielectric function on the heat sink 221 by lamination or other processes, and disposing the first circuit layer 222 on the other side of the first insulating layer 223 away from the heat sink 221 by electroplating or etching.

[0050] Here, the first heat sink 22 having a continuous side surface 220 refers to the Figure 1 As for the structure of the DBC substrate external heat sink shown, the side of the first heat sink 22 has no obvious interface or interval. Figure 1 There are additional thermal interfaces in the structure shown, and the thermal interfaces may be filled with thermal interface materials, resulting in the side of the structure being non-continuous and having obvious interfaces or intervals. The first heat sink 22 of the present application, its first heat sink 221 is an integral structure with a continuous side, and its side does not have obvious interfaces or intervals. Here, the continuous side 220 can be understood as the entire side of the first heat sink 22. Furthermore, the continuous side 220 can also be understood as the side of the first heat sink 221.

[0051] Here, the first insulating layer 223 can be an insulating material with better heat dissipation performance, such as ceramic material or FR-4 material. After special treatment, the thermal conductivity of some types of ceramic materials can be very excellent, such as diamond (C) and polycrystalline diamond ceramic (PCD), the theoretical thermal conductivity of diamond is 1642W / m·K; silicon carbide (SiC), the theoretical thermal conductivity can reach 270W / m·K; aluminum nitride (AlN, the thermal conductivity can reach 170~230W / m·K. FR-4 is a code for a flame retardant material grade. It is not a material name, but a material grade. There are many types of FR-4 materials generally used. This application preferably uses FR-4 materials with better heat dissipation performance, such as FR-4 materials with a thermal conductivity higher than 170W / m·K or higher than 100W / m·K or higher than 50W / m·K.

[0052] Here, the first circuit layer 222 includes but is not limited to copper, gold or silver or alloys thereof. Here, the first circuit layer 222 may be formed by etching rolled copper laminated on the first insulating layer 223, or the first circuit layer 222 may be electroplated copper formed by electroplating on the first insulating layer 223, or the first circuit layer 222 may be sputtered copper formed by sputtering on the first insulating layer 223.

[0053] Here, the first heat sink 221 includes but is not limited to metal materials such as copper, aluminum, or metal alloys. The first heat sink 221 can be formed by stamping, engraving, or etching a whole piece of metal. Optionally, one side surface of the first heat sink 221 is a flat surface, which is bonded to the first insulating layer 223, and a plurality of heat sink fins 2211 can be formed on the other side of the first heat sink 221 to increase the heat dissipation area and improve the heat dissipation efficiency. The heat sink fins 2211 can be arranged regularly, such as in rows and columns, or can be arranged irregularly.

[0054] Here, the first heat sink 22 can be arranged above the power chip 21, with its first heat sink 221 facing upward away from the power chip 21, and its first circuit layer 222 facing downward and connected to the power chip 21. The first heat sink 22 is thermally and / or electrically connected to the power chip 21 through its first circuit layer 222.

[0055] Here, the encapsulation glue 23 can cover the power chip 21 to encapsulate and protect the power chip 21; the encapsulation glue 23 can also laterally cover a portion of the continuous side 220 of the first heat sink 22 (which can be understood as a portion of the side of the first heat sink 221 that is laterally covered), so that the first heat sink 22 is partially embedded in the encapsulation glue 23 and partially protrudes from the encapsulation glue 23, thereby reinforcing the connection. Here, the encapsulation glue 23 can be formed by various molding materials (Molding Compound), and the molding materials may include epoxy resin (Epoxy resin), filler (Filler), catalyst (Catalyst), pigment (Pigment), release agent (Release Agent), flame retardant (Flame Retardant), coupling agent (Coupling Agent), hardener (Hardener), low stress absorber (Low Stress Absorber), adhesion promoter (Adhesion Promoter), ion trapping agent (Ion Trapping Agent) and other materials. Part or all. For example, the packaging glue 23 may be EMC (Epoxy molding compound).

[0056] In some optional embodiments, the packaging glue 23 covers the first circuit layer 222, covers the side surface of the first insulating layer 223, and extends upward to laterally cover a portion of the side surface of the first heat sink 221. In this way, it is ensured that the packaging glue 23 and the first heat sink 22 have a high connection strength, thereby ensuring that the power chip 21 located inside the packaging glue 23 and the first heat sink 22 have a high bonding strength.

[0057] In some optional embodiments, the width of the first insulating layer 223 is greater than the width of the first heat sink 221, and the width of the first insulating layer 223 is greater than the width of the first circuit layer 222, that is, the side of the first insulating layer 223 protrudes outwardly and laterally beyond the side of the first heat sink 221, and the side of the first insulating layer 223 protrudes outwardly and laterally beyond the side of the first circuit layer 222. If the continuous side 220 is understood as the side of the first heat sink 221, it can also be said that the side of the first insulating layer 223 protrudes outwardly and laterally beyond the continuous side 220. If the continuous side 220 is understood as the side of the first heat sink 22, it can be said that the continuous side 220 is non-flat, and the part of the first insulating layer 223 thereof has a shape that protrudes outwardly and laterally.

[0058] In some optional implementations, the thickness of the first heat sink 221 is greater than that of the first circuit layer 222. A thicker first heat sink 221 has a higher heat dissipation efficiency.

[0059] Continue to refer Figure 2 In some optional embodiments, the electronic device 2a of the present application further includes a second heat sink 26 disposed opposite to the first heat sink 22. The second heat sink 26 includes a second heat sink 261, a second circuit layer 262, and a second insulating layer 263 disposed between the second heat sink 261 and the second circuit layer 262. The structure and materials of each component of the second heat sink 26 are similar to those of the first heat sink 22. Please refer to the above description of the first heat sink 22, which will not be repeated here. However, it should be noted that the second circuit layer 262 and the first circuit layer 222 can have the same or different circuit patterns to meet design requirements.

[0060] Here, the second heat sink 26 may be located below the power chip 21 and carry the power chip 21. The second circuit layer 262 of the second heat sink 26 faces upward toward the power chip 21, and the second heat sink 261 faces downward away from the power chip 21. In other words, the power chip 21 may be disposed on the second circuit layer 262 and located between the first circuit layer 222 and the second circuit layer 262.

[0061] Here, the power chip 21 includes but is not limited to being soldered on the second circuit layer 262 by solder 24 .

[0062] Here, the second heat sink 26 can be thermally and / or electrically connected to the power chip 21 through its second circuit layer 262 .

[0063] In some optional embodiments, the encapsulation glue 23 can further cover the second circuit layer 262, cover the side of the second insulating layer 263, and extend downward to laterally cover a portion of the side of the second heat sink 261. In this way, it is ensured that the encapsulation glue 23 and the second heat sink 26 have a high connection strength, thereby ensuring that the power chip 21 located inside the encapsulation glue 23 and the second heat sink 26 have a high bonding strength.

[0064] In some optional implementations, the gap between the first heat sink 22 and the second heat sink 26 may be completely filled with the packaging glue 23 .

[0065] Continue to refer Figure 2 In some optional embodiments, the electronic device 2a of the present application may also include a lead frame, which includes at least a pin 27, one end of which may be electrically connected to the second circuit layer 262, and the other end of which may be exposed outside the packaging glue 23, and the pin 27 may be used to provide a signal / power output and input path for the power chip 21.

[0066] In some optional embodiments, the pins 27 and the power chip 21 may be electrically connected via wire bonding 28. Specifically, the second circuit layer 262 may include a first region electrically connected to the power chip 21 and a second region electrically connected to the pins 27, and the first region and the second region may be electrically connected via wire bonding 28.

[0067] here, Figure 2 The structure shown takes the pin 27 connected to the second circuit layer 262 as an example, but it should be understood that it is also possible to connect the pin 27 to the first circuit layer 222, or to connect a part of the pins 27 to the first circuit layer 222 and another part of the pins 27 to the second circuit layer 262.

[0068] Continue to refer Figure 2 In some optional embodiments, the electronic device 2a of the present application may further include at least one gasket 25 disposed between at least one power chip 21 and the first circuit layer 222 .

[0069] Here, the gasket 25 can play the role of electrical connection and / or thermal connection, as well as provide supporting force and balance the height difference.

[0070] In some optional embodiments, the gasket 25 may be made of a metal material with high electrical conductivity and / or high thermal conductivity and good rigidity. Exemplarily, the material of the gasket 25 includes but is not limited to copper or aluminum or alloys thereof.

[0071] In some optional embodiments, the gasket 25 and the first circuit layer 222 , and / or the gasket 25 and the power chip 21 may be electrically and / or thermally connected by welding using solder 24 .

[0072] In some optional embodiments, there may be multiple power chips 21, and the heights (thicknesses) of the multiple power chips 21 may be different. In this case, multiple gaskets 25 may be provided, and the multiple gaskets 25 are respectively provided between the multiple power chips 21 and the first circuit layer 222, and the thicknesses of the multiple gaskets 25 are not completely the same. For example, a thinner gasket 25 is provided on a taller power chip 21, and a thicker gasket 25 is provided on a shorter power chip 21, so that the height of the combination of each power chip 21 and the gasket 25 thereon is substantially the same. In this way, the height difference between different power chips 21 can be balanced (compensated).

[0073] In some optional embodiments, when the pin 27 and the power chip 21 are electrically connected via the bonding wire 28 , at least one gasket 25 may be provided to increase the spacing distance between the first circuit layer 222 and the second circuit layer 262 , leaving space for the bonding wire 28 .

[0074] It should be understood that a gasket 25 may be disposed above each power chip 21 , or a gasket 25 may be disposed above only a portion of the power chips 21 , while the other portion of the power chips 21 are directly connected to the first circuit layer 222 .

[0075] It should be noted that, in the embodiment of the present application, the first heat sink 22 is partially embedded in the packaging glue 23 and partially protrudes from the packaging glue 23, so that the power chip 21, the gasket 25 and the first circuit layer 222 can be completely embedded in the packaging glue 23, which can strengthen and stabilize the connection between the power chip 21, the gasket 25 and the first heat sink 22.

[0076] refer to Figure 3 , Figure 3 is a schematic diagram of a power chip 21 according to an embodiment of the present application. It should be understood that Figure 3 The structure of the power chip 21 shown is only an example of the present application, and the power chip 21 may also have other structures.

[0077] here, Figure 3 The power chip 21 shown takes an IGBT (insulated gate bipolar transistor) as an example. The IGBT may have multiple terminals, for example, a first terminal 211 located on the upper surface, and the first terminal 211 may be electrically connected to the first wiring layer 222 of the first heat sink 22. Exemplarily, the first terminal 211 may include a collector (Collector, C). The IGBT may also have a second terminal 212 located on the lower surface, and the second terminal 212 may be electrically connected to the second wiring layer 262 of the second heat sink 26. Exemplarily, the second terminal 212 may include an emitter (Emitter, E) and a gate (Gste, G).

[0078] The electronic device 2a of one embodiment of the present application is described above. The heat sink of the electronic device 2a (for example, the first heat sink 22) is equivalent to an insulated metal substrate (IMS) with a built-in heat sink, one side of which is a heat sink and the other side is a circuit layer. The heat sink can be an integrated structure formed by directly laminating an insulating layer that performs thermal conductivity and dielectric functions on the heat sink and arranging a circuit layer on the insulating layer (equivalent to replacing the metal substrate in the conventional IMS with a heat sink). Therefore, the electronic device 2a does not need an external heat sink, and thus no additional heat conduction interface is added. Therefore, compared with the existing structure of the DBC substrate with an external heat sink, the present application can reduce the heat conduction interface and improve the heat dissipation effect. It is also because an insulated metal substrate with a simpler process technology is used to replace the DBC substrate, and the step of external heat sink is eliminated, which can simplify the process and reduce costs.

[0079] The electronic device 2a of the present application can be a double-sided heat dissipation power module, which uses an IMS with a heat sink as a heat sink to connect the power chip 21, and plays the role of a conductive circuit and an electrical insulating medium as well as a heat conductor, thereby simplifying the process technology, shortening the production time, and reducing the production cost. The IMS with a heat sink as a heat sink has a thicker heat sink (relative to the metal layer of the DBC substrate), and has a better heat dissipation efficiency. In addition, the entire heat sink is integrally formed, and no additional bonding process is required to connect an external heat dissipation device. The overall thermal resistance will be smaller than the structure of the DBC substrate with an external heat dissipation device, which is more conducive to heat dissipation.

[0080] refer to Figure 4 , Figure 4 It is a schematic diagram of the longitudinal cross-sectional structure of an embodiment 4a of the electronic device according to the present application. Figure 4 The electronic device 4a shown is similar to Figure 2 The electronic device 2a shown is different in that:

[0081] The electronic device 4a does not include Figure 2 By using the bonding wires 28 in the electronic device 4 a , the pins 27 in the electronic device 4 a and the power chip 21 can be directly electrically connected through the second wiring layer 262 .

[0082] The electronic device 4a does not include Figure 2 By using the gasket 25 in the electronic device 4 a , the power chip 21 in the electronic device 4 a can be directly electrically connected to the first circuit layer 222 .

[0083] refer to Figure 5 , Figure 5 It is a schematic diagram of the longitudinal cross-sectional structure of an embodiment 5a of the electronic device according to the present application. Figure 5 The electronic device 5a shown is similar to Figure 2 The electronic device 2a shown is different in that:

[0084] The electronic device 5a does not include Figure 2 The gasket 25 in the first circuit layer 222 includes a boss 2221, and at least one power chip 21 is arranged at the boss 2221. Here, the boss 2221 is used to compensate (balance) the height difference between different power chips 21. The boss 2221 plays a role in Figure 2 The function of the middle gasket 25.

[0085] refer to Figure 6 and Figure 7 , Figure 6 According to one embodiment of the present application, Figure 2 The electronic device 2a shown is placed in a mold 30 for molding to form a packaging glue 23; Figure 7 According to another embodiment of the present application, Figure 4The electronic device 4 a shown is placed in a mold for molding to form a packaging glue 23 .

[0086] like Figure 6 and Figure 7 As shown, the inner surface of the mold cavity of the mold 30 includes a recess 31, for example, one recess is provided at the top and one recess is provided at the bottom. The first heat sink 221 of the first heat sink 22 (and / or the second heat sink 261 of the second heat sink 26) can be partially embedded in the recess 31, so that the portion embedded in the recess 31 is not covered by the molding material during the molding process, and is exposed outside the packaging glue 23 after the molding is completed.

[0087] Figure 6 and Figure 7 It shows how to use exposed mold to expose the heat sink part outside the packaging glue 23 when using mold material to protect the electronic device, and how to stabilize the connection between the first heat sink 22 and the gasket 25.

[0088] refer to Figure 8-11 , Figure 8-11 Schematic diagram of the manufacturing steps of an embodiment of the electronic device of the present application. For ease of understanding, Figure 8-11 Simplified.

[0089] First, refer to Figure 8 A second heat sink 26 is provided, the second heat sink 26 includes a second heat sink 261, a second circuit layer 262, and a second insulating layer 263 disposed between the second heat sink 261 and the second circuit layer 262. Optionally, solder may be disposed at a preset position of the third circuit layer 252.

[0090] Next, refer to Fig. 9 , the power chip 21 and the pin 27 are set on the second circuit layer 262, for example, by solder, and a part of the second circuit layer 262 carrying the power chip 21 and a part of the second circuit layer 262 carrying the pin 27 are connected by wire bonding 28, and a gasket 25 is set on the power chip 21, for example, by solder.

[0091] Next, refer to Fig.10 and Fig.11 , provide a first heat sink 22, the first heat sink 22 may include a first heat sink 221, a first circuit layer 222 and a first insulating layer 223 disposed between the heat sink 221 and the circuit layer 222. The first heat sink 22 is disposed above the gasket 25 with the first circuit layer 222 facing downward, so that the first circuit layer 222 is connected to the gasket 25, for example, by solder, so that the first circuit layer 222 is electrically connected to the power chip 21 through the gasket 25, such as Fig.11 shown.

[0092] Next, we will Fig.11 The structure shown is placed as Figure 6 In the mold 30 shown, a molding operation is performed to form a packaging glue 23 .

[0093] Finally, remove Figure 6 The mold 30 shown in FIG. Figure 2 The electronic device 2a is shown.

[0094] Although the present application has been described and illustrated with reference to the specific embodiments of the present application, these descriptions and illustrations do not limit the present application. It is clearly understood by those skilled in the art that various changes can be made, and equivalent elements can be substituted in the embodiments without departing from the true spirit and scope of the present application as defined by the appended claims. The illustrations may not necessarily be drawn to scale. Due to variables in the manufacturing process, etc., there may be differences between the technical reproduction in the present application and the actual implementation. There may be other embodiments of the present application that are not specifically described. The description and illustrations should be regarded as illustrative, not restrictive. Modifications may be made to adapt specific circumstances, materials, material compositions, methods or processes to the goals, spirits and scopes of the present application. All such modifications fall within the scope of the appended claims. Although the methods disclosed herein have been described with reference to specific operations performed in a specific order, it should be understood that these operations can be combined, subdivided or reordered to form equivalent methods without departing from the teachings of the present application. Therefore, unless specifically indicated herein, the order and grouping of operations do not limit the present application.

Claims

1. An electronic device, characterized in that: include: Power chip; A first heat sink having a continuous side surface and configured to provide a heat dissipation path for the power chip; A packaging adhesive, covering the power chip and laterally covering a portion of the continuous side surface of the first heat sink; The first heat sink includes a first heat sink, a first circuit layer, and a first insulating layer disposed between the heat sink and the circuit layer, and the first circuit layer is electrically connected to a first terminal of the power chip.

2. The electronic device according to claim 1, characterized in that: The packaging glue covers the side surfaces of the first insulating layer.

3. The electronic device according to claim 2, characterized in that: The continuous side surface includes a side surface of the first heat sink, and a side surface of the first insulating layer protrudes outward from a side surface of the first heat sink.

4. The electronic device according to claim 1, characterized in that: The power chip includes an insulated gate bipolar transistor (IGBT), and the first terminal includes a collector.

5. The electronic device according to claim 1, characterized in that: The thickness of the first heat sink is greater than that of the first circuit layer.

6. The electronic device according to claim 1, characterized in that: It also includes a gasket arranged between the power chip and the first circuit layer.

7. The electronic device according to claim 6, characterized in that: The plurality of gaskets are respectively arranged between the plurality of power chips and the first circuit layer, and the thicknesses of the plurality of gaskets are not completely the same.

8. The electronic device according to claim 1, characterized in that: It also includes a second heat sink arranged opposite to the first heat sink, the second heat sink includes a second heat sink, a second circuit layer and a second insulating layer arranged between the second heat sink and the second circuit layer, and the power chip is located between the first circuit layer and the second circuit layer.

9. The electronic device according to claim 8, characterized in that: The second circuit layer has a different circuit pattern from the first circuit layer.

10. The electronic device according to claim 1, characterized in that: The first circuit layer includes a boss, and the power chip is arranged on the boss.

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