Chip remote debugging device

Abstract

The utility model relates to a chip remote debugging device. The chip remote debugging device comprises a network interface; the server proxy module is coupled to the network interface so as to remotely communicate with a home server through the network interface; the circuit board is provided with an onboard chip and a debugging driving circuit; wherein the debugging driving circuit is coupled with the server agent module through a transmission bus, the debugging driving circuit is coupled with the onboard chip through a debugging bus, and the debugging driving circuit forms a coupling link between the server agent module and the onboard chip, and the coupling link is used for carrying out remote debugging on the onboard chip. On the basis of the scheme, remote debugging of the server on the onboard chip can be achieved, the risk of circuit board damage can be reduced, shutdown, box opening and field connection of an oscilloscope are not needed in the remote debugging process of the onboard chip through the method, the occupied time of debug on equipment can be shortened, and the debugging efficiency can be improved. And the debug efficiency of the on-board chip can be improved.

Description

Technical Field

[0001] The present disclosure relates to the field of chip testing, and in particular to a chip remote debugging device. Background Art

[0002] Debugging the integrated circuit chips (onboard chips) on product boards has always been a troublesome task. If a product board has a problem after delivery, engineers need to remove the product board from the device and weld a JTAG (Joint Test Action Group) interface (a test interface) to test the onboard chip through the JTAG interface to try to reproduce the problem. Only when the problem is reproduced can the debugging work be completed. This method leads to low work efficiency, high risk of board damage, and affects the use of equipment. Utility Model Content

[0003] In view of this, the present disclosure provides a chip remote debugging device to improve the debugging efficiency of onboard chips.

[0004] The technical solution of the present disclosure is achieved as follows:

[0005] According to one aspect of an embodiment of the present disclosure, a chip remote debugging device is provided, including:

[0006] Network interface;

[0007] a server proxy module coupled to the network interface for remotely communicating with a home server through the network interface;

[0008] A circuit board having an onboard chip and a debugging drive circuit;

[0009] Among them, the debugging driving circuit is coupled to the server agent module through a transmission bus, the debugging driving circuit is coupled to the onboard chip through a debugging bus, and the debugging driving circuit forms a coupling link between the server agent module and the onboard chip for remote debugging of the onboard chip.

[0010] In a possible implementation manner, the circuit board further has a controller, and the debugging driving circuit is integrated into the controller.

[0011] In a possible implementation manner, the controller is a logic device or an MCU.

[0012] In a possible implementation manner, the debugging driving circuit includes a transmission port, a debugging port, and a storage medium;

[0013] The transmission port is coupled to the server agent module via the transmission bus;

[0014] The debug port is coupled to the onboard chip via the debug bus;

[0015] The storage medium is shared and accessed by the transmission port and the debugging port.

[0016] In a possible implementation manner, the circuit board further has a controller, and the debugging drive circuit is integrated in the controller, wherein:

[0017] The controller is a logic device, and the storage medium includes a register group in the logic device;

[0018] or,

[0019] The controller is an MCU, and the storage medium includes a memory of the MCU.

[0020] In a possible implementation manner, there are at least two circuit boards.

[0021] In one possible implementation, the debug driving circuits of at least two of the circuit boards are respectively coupled to the downstream ports of the debug gating circuit via the transmission bus, and the upstream port of the debug gating circuit is coupled to the server agent module via the transmission bus.

[0022] In one possible implementation, the debug gating circuit selectively connects the server agent module to the debug driving circuits of at least two of the circuit boards.

[0023] In a possible implementation manner, the server agent module is a baseboard management controller BMC;

[0024] The transmission bus is an SM bus.

[0025] In a possible implementation manner, the onboard chip is any one of a central processing unit CPU, a graphics processing unit GPU, a tensor processing unit TPU, a neural network processor NPU, a deep learning processor DPU, an acceleration processing unit APU, and a general-purpose graphics processing unit GPGPU;

[0026] The debugging bus is a JTAG bus.

[0027] It can be seen from the above scheme that the chip remote debugging device disclosed in the present invention sets a debugging drive circuit in the circuit board and uses the debugging drive circuit as a transfer bridge between the debugging bus and the transmission bus when debugging the onboard chip, so as to realize the debugging of the onboard chip by using the transmission bus. Based on this, when the circuit board has a transmission bus interface, the existing transmission bus interface can be directly used to realize the debugging of the onboard chip, so it can replace the solution in the related art that requires the JTAG interface to be welded on site, which helps to reduce the risk of circuit board damage. At the same time, the server proxy module communicates remotely with the home server through the network interface, so as to realize the remote debugging of the onboard chip by the server. With the chip remote debugging device disclosed in the present invention, in the process of remote debugging of the onboard chip, there is no need to shut down, unpack, or connect an oscilloscope on site, so the debugging personnel do not need to enter the on-board chip site for debugging, which reduces the manual disassembly and assembly of the equipment on site, helps to reduce the time occupied by the debugger on the equipment, and helps to improve the debugging efficiency of the onboard chip. In addition, because the operating environment of the onboard chip of the debugger is not destroyed, it also helps to avoid the situation where the problem cannot be reproduced due to the change of the operating environment during the debugging process. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 is a schematic structural diagram of a chip remote debugging device according to an exemplary embodiment;

[0029] Figure 2 is a schematic diagram of a logic structure of a debugging driving circuit according to an exemplary embodiment;

[0030] Figure 3 is a second logical structure diagram of a debugging driving circuit according to an exemplary embodiment;

[0031] Figure 4 is a schematic structural diagram of another chip remote debugging device according to an exemplary embodiment;

[0032] Figure 5 is a schematic diagram of a logic structure of a debug gating circuit according to an exemplary embodiment;

[0033] Figure 6 The figure is a schematic diagram of the connection structure between the debugging driving circuit and the onboard chip according to an exemplary embodiment. DETAILED DESCRIPTION

[0034] In order to make the objectives, technical solutions and advantages of the present disclosure more clearly understood, the present disclosure is further described in detail below with reference to the accompanying drawings and examples.

[0035] It should be noted that the terms "first", "second", etc. in the specification and claims of the present disclosure and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the objects used in this way can be interchanged where appropriate, so that the embodiments of the present disclosure described herein can be implemented in examples other than those illustrated or described herein. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present disclosure. Instead, they are merely examples of devices and methods consistent with some aspects of the present disclosure as detailed in the appended claims.

[0036] Currently, in the debugging scheme for the onboard chip on the product board, maintenance personnel are required to enter the site, shut down the server, and weld the JTAG interface on site to reproduce the problem. This debugging method takes a long time and affects the use of the equipment. In addition, because the JTAG interface needs to be welded on the product board to test the onboard chip, there is a risk of damage to the board. In addition, when debugging, the problem needs to be reproduced on the device where the product board is located (such as a server), resulting in the occupation of the device and affecting the normal use of the device. If the problem is reproduced on other platforms, the problem may not be reproduced due to changes in the environment in which the product board is located. In particular, when the problems are relatively scattered and a problem occurs on a product board among multiple product boards in the device, it is difficult to determine the product board with the problem in advance, which further increases the difficulty of problem solving.

[0037] In view of this, an embodiment of the present disclosure provides a chip remote debugging device. When a problem occurs in an onboard chip and debugging is required, the onboard chip can be debugged directly, eliminating the step of on-site welding of the JTAG interface, thereby helping to improve the test and diagnosis efficiency of the integrated circuit chip on the circuit board.

[0038] Figure 1 is a schematic diagram of a chip remote debugging device according to an exemplary embodiment. Figure 1 As shown, the chip remote debugging device mainly includes a network interface 1, a server proxy module 2, and a circuit board 3. The circuit board 3 has an onboard chip 31 and a debugging drive circuit 32. The server proxy module 2 is coupled to the network interface 1 to remotely communicate with the home server through the network interface 1. The debugging drive circuit 32 is coupled to the server proxy module 2 through a transmission bus 4, and the debugging drive circuit 32 is coupled to the onboard chip 31 through a debugging bus 5. Moreover, the debugging drive circuit 32 forms a coupling link between the server proxy module 2 and the onboard chip 31 for remote debugging of the onboard chip 31.

[0039] The chip remote debugging device of the embodiment of the present disclosure sets a debugging driving circuit 32 in the circuit board 3 and uses the debugging driving circuit 32 as a transfer bridge between the debugging bus 5 and the transmission bus 4 when debugging the onboard chip 31, so as to realize the debugging of the onboard chip 31 by using the transmission bus 4. Based on this, when the circuit board 3 has a transmission bus interface, the existing transmission bus interface can be directly used to realize the debugging of the onboard chip 31, so it can replace the solution in the related art that requires the JTAG interface to be welded on site, which helps to reduce the risk of damage to the circuit board 3. At the same time, the server proxy module 2 remotely communicates with the home server through the network interface 1, so as to realize the remote debugging of the onboard chip 31 by the server. When the chip remote debugging device of the embodiment of the present disclosure is used, during the remote debugging of the onboard chip 31, there is no need to shut down the machine, unpack the machine, or connect an oscilloscope on site, so the debugging personnel do not need to enter the on-site location of the onboard chip 31 for debugging, which reduces the manual disassembly and assembly of the equipment on site, helps to reduce the time occupied by the debugging on the equipment, and helps to improve the debugging efficiency of the onboard chip 31. Furthermore, since the operating environment of the debug onboard chip 31 is not damaged, it helps to avoid the situation where the problem cannot be reproduced due to changes in the operating environment during the debugging process.

[0040] In the exemplary embodiment, the circuit board 3 also has a controller, and the debug drive circuit 32 is integrated in the controller. Based on this embodiment, the existing controller in the circuit board 3 can be used to implement the function of the debug drive circuit 32 in the chip remote debugging device of the embodiment of the present disclosure, without adding a new hardware device to the circuit board 3 to implement the function of the debug drive circuit 32.

[0041] In the exemplary embodiment, the controller is a logic device or an MCU (Microcontroller Unit). The logic device may be any one of a CPLD (Complex Programmable Logic Device), an FPGA (Field-Programmable Gate Array), and an EPLD (Erasable Programmable Logic Device). When the embodiment of the present disclosure is applied to a UBB (Unified Backplane Board), the debug drive circuit 32 in the embodiment of the present disclosure may be implemented using the CPLD already existing on the UBB, and therefore, no additional cost is added.

[0042] Figure 2is a schematic diagram of a logic structure of a debugging driving circuit according to an exemplary embodiment, such as Figure 2 As shown, the debugging driving circuit 32 mainly includes a transmission port 321, a debugging port 322 and a storage medium 323. Figure 1 As shown, the transmission port 321 is coupled to the server proxy module 2 through the transmission bus 4, the debug port 322 is coupled to the onboard chip 31 through the debug bus 5, and the storage medium 323 is shared and accessed by the transmission port 321 and the debug port 322. Based on this, using the chip remote debugging device of the embodiment of the present disclosure, in the debug driving circuit 32, the storage medium 323 can be used as an intermediate medium between the transmission port 321 and the debug port 322, caching the data written by the transmission port 321 for reading by the debug port 322, and caching the data written by the debug port 322 for reading by the transmission port 321. Based on the logical structure of the debug driving circuit 32 in the chip remote debugging device of the embodiment of the present disclosure, when the transmission port 321 and the debug port 322 belong to different protocol standards, the transmission port 321 can read and write data to the storage medium 323 according to its own protocol standard, and the debug port 322 can read and write data to the storage medium 323 according to its own protocol standard, and it is only necessary to ensure that the storage method in the storage medium 323 can be read and written by the transmission port 321 and the debug port 322 respectively.

[0043] In the exemplary embodiment, the circuit board 3 also has a controller, and the debugging driving circuit 32 is integrated in the controller. Based on this, the controller is a logic device, and the storage medium 323 includes a register group in the logic device; or, the controller is an MCU, and the storage medium 323 includes the memory of the MCU.

[0044] Figure 3 is a second logical structure diagram of a debugging driving circuit according to an exemplary embodiment, such as Figure 3 As shown, in the second logical structure of the debugging driving circuit 32, the storage medium 323 includes a first storage area 3231 and a second storage area 3232. The first storage area 3231 is written by the transmission port 321 and read by the debugging port 322, and the second storage area 3232 is written by the debugging port 322 and read by the transmission port 321. In the exemplary embodiment, the data stored in the first storage area 3231 may be downlink data, and the data stored in the second storage area 3232 may be uplink data; wherein the downlink data refers to the data flowing from the server agent module 2 to the onboard chip 31, and the downlink data may be, for example, the debugging instruction data sent by the server agent module 2 to the onboard chip 31; the uplink data refers to the data flowing from the onboard chip 31 to the server agent module 2, and the uplink data may be, for example, the debugging result data fed back by the onboard chip 31 to the server agent module 2.

[0045] The first storage area 3231 and the second storage area 3232 are used to store the downlink data and the uplink data respectively, which is beneficial to the access of the downlink data and the uplink data respectively, and does not interfere with each other. On this basis, the debug port 322 can read the downlink data in time based on the writing of the downlink data in the first storage area 3231, and the transmission port 321 can read the uplink data in time based on the writing of the uplink data in the second storage area 3232, which is beneficial to the smooth transmission of the downlink data and the uplink data respectively.

[0046] Figure 4 FIG. 1 is a schematic diagram showing a structure of another chip remote debugging device according to an exemplary embodiment. Figure 4 As shown, in the embodiment of the chip remote debugging device, the number of circuit boards 3 is at least two.

[0047] On this basis, the chip remote debugging device can further include a debugging gating circuit 6. The debugging driving circuits 32 of at least two circuit boards 3 are respectively coupled to the downlink ports of the debugging gating circuit 6 through the transmission bus 4, and the uplink port of the debugging gating circuit 6 is coupled to the server agent module 2 through the transmission bus 4.

[0048] In the exemplary embodiment, the debug gating circuit 6 selectively connects the server agent module 2 to the debug driving circuits 32 of at least two circuit boards 3 .

[0049] Figure 5 is a schematic diagram of a logic structure of a debug gating circuit according to an exemplary embodiment, such as Figure 5 As shown, the debug gating circuit 6 includes a gating switching circuit 61 and a gating control circuit 62. The gating switching circuit 61 has an uplink channel and at least two downlink channels, the uplink channel is connected to the uplink port 63 of the debug gating circuit 6, and the at least two downlink channels are connected to the downlink port 64 of the debug gating circuit 6, wherein the number of the downlink ports 64 of the debug gating circuit 6 is equal to the number of the circuit boards 3. The uplink channel and the at least two downlink channels are selectively connected. The gating control circuit 62 is connected to the uplink port 63 of the debug gating circuit 6 and the gating switching circuit 61, and is used to maintain the conductive state that the uplink channel and the at least two downlink channels are selectively connected.

[0050] In the exemplary embodiment, the gating control circuit 62 generates a level signal for determining the downstream channel currently connected to the upstream channel among the at least two downstream channels according to the gating configuration information obtained from the upstream port 63. In the exemplary embodiment, the gating control circuit 62 may include a register group, the gating configuration information may be a register value in the register group, and the level state of the level signal is determined by the register value. In the exemplary embodiment, the upstream port 63 receives the gating configuration information from the server agent module 2 through the transmission bus 4 and writes it into the register group of the gating control circuit 62.

[0051] In the exemplary embodiment, the server agent module 2 is a BMC (Baseboard Management Controller), and the transmission bus 4 is a SM (System Management) bus. The SM bus is based on I 2 C (Inter-Integrated Circuit) serial bus standard.

[0052] In the exemplary embodiment, the onboard chip 31 is any one of a CPU (Central Processing Unit), a GPU (Graphics Processing Unit), a TPU (Tensor Processing Unit), a NPU (Neural Network Processing Unit), a DPU (Deep Learning Processing Unit), an APU (Accelerated Processing Unit), and a GPGPU (General-Purpose computing on Graphics Processing Unit). The debug bus 5 is a JTAG bus.

[0053] Based on the chip remote debugging device of the embodiment of the present disclosure, the debugging driving circuit 32 forms a coupling link between the SM bus and the JTAG bus between the server proxy module 2 and the onboard chip 31 for remote debugging of the onboard chip 31. In the debugging driving circuit 32, the storage medium 323 is used as an intermediate medium between the SM bus and the JTAG bus, and the data written by the transmission port 321 on the SM bus side is cached for reading by the debugging port 322 on the JTAG bus side, and the data written by the debugging port 322 on the JTAG bus side is cached for reading by the transmission port 321 on the SM bus side. In the case where the transmission port 321 and the debugging port 322 belong to the SM bus protocol standard and the JTAG bus protocol standard respectively, the transmission port 321 can read and write data to the storage medium 323 according to the SM bus protocol standard, and the debugging port 322 can read and write data to the storage medium 323 according to the JTAG bus protocol standard. It only needs to ensure that the storage method in the storage medium 323 can be read and written by the transmission port 321 and the debugging port 322 respectively.

[0054] In an exemplary embodiment, the embodiment of the present disclosure further provides a server, which includes the chip remote debugging device of the above embodiments. Among them, the server may include one, two or more circuit boards 3, and the home server sends instructions to the server agent module 2 through the network interface 1 to debug the onboard chip 31 of the specified circuit board 3 in the server. In an exemplary embodiment, the home server can be a device that performs centralized management, setting, scheduling, data distribution, data collection, etc. on the server.

[0055] Since the home server is connected to the server through the network interface 1, the home server can be set up in a place far away from the server, thereby realizing remote debugging of the onboard chip 31. Therefore, the maintenance personnel do not need to enter the site where the server is located and perform manual operations such as shutting down the server, welding the JTAG interface, and reproducing the problem on site. The debugging of the onboard chip 31 can be completed in the form of remote instructions, saving the debugging time of the onboard chip 31. When there are multiple servers on site and multiple circuit boards 3 in the server, the embodiment of the present disclosure helps to save debugging time.

[0056] Figure 6 FIG. 1 is a schematic diagram of a connection structure between a debugging driving circuit 32 and an onboard chip 31 according to an exemplary embodiment. Figure 6As shown, the connection structure is a JTAG structure, wherein the debug driving circuit 32 is integrated in a logic device or an MCU. Specifically, the input and output interfaces of the debug driving circuit 32 are connected to the onboard chip 31. Among them, the interface IO1 is used as a TCK signal (clock signal) interface, and the debug driving circuit 32 sends a fixed frequency pulse as a TCK signal to the onboard chip 31 through the interface IO1; the interface IO2 is a TDI signal interface, and the debug driving circuit 32 sends commands or data to the onboard chip 31 through the interface IO2; the interface IO3 is a TDO signal interface, and the onboard chip 31 returns the register data of its internal corresponding address to the debug driving circuit 32 through the interface IO3; the interface IO4 is a TMS signal interface, and the debug driving circuit 32 sends a JTAG mode selection command to the onboard chip 31 through the interface IO4; the interface IO5 is a reset (RSTn) signal interface, and the debug driving circuit 32 sends a reset signal to the onboard chip 31 through the interface IO5. The timing of the interfaces IO1 to IO5 meets the design requirements of the JTAG of the onboard chip 31 itself. The debug driving circuit 32 reads the register value from the onboard chip 31 and temporarily stores it in the internal storage medium 323 , and the SM bus then takes the value in the storage medium 323 .

[0057] All the above optional technical solutions can be arbitrarily combined to form optional embodiments of the present disclosure, and will not be described in detail here.

[0058] The above description is only a preferred embodiment of the present disclosure and is not intended to limit the present disclosure. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present disclosure shall be included in the scope of protection of the present disclosure.

Claims

1. A chip remote debugging device, characterized in that: include: Network interface; a server proxy module coupled to the network interface for remotely communicating with a home server through the network interface; A circuit board having an onboard chip and a debugging drive circuit; Among them, the debugging driving circuit is coupled to the server agent module through a transmission bus, the debugging driving circuit is coupled to the onboard chip through a debugging bus, and the debugging driving circuit forms a coupling link between the server agent module and the onboard chip for remote debugging of the onboard chip.

2. The chip remote debugging device according to claim 1, characterized in that: The circuit board also has a controller, and the debugging driving circuit is integrated in the controller.

3. The chip remote debugging device according to claim 2, characterized in that: The controller is a logic device or an MCU.

4. The chip remote debugging device according to claim 1, characterized in that: The debugging driving circuit includes a transmission port, a debugging port and a storage medium; The transmission port is coupled to the server agent module via the transmission bus; The debug port is coupled to the onboard chip via the debug bus; The storage medium is shared and accessed by the transmission port and the debugging port.

5. The chip remote debugging device according to claim 4, characterized in that: The circuit board also has a controller, and the debugging drive circuit is integrated in the controller, wherein: The controller is a logic device, and the storage medium includes a register group in the logic device; or, The controller is an MCU, and the storage medium includes a memory of the MCU.

6. The chip remote debugging device according to claim 1, characterized in that: The number of the circuit boards is at least two.

7. The chip remote debugging device according to claim 6, characterized in that: The debugging driving circuits of at least two of the circuit boards are respectively coupled to the downstream ports of the debugging gating circuit through the transmission bus, and the upstream port of the debugging gating circuit is coupled to the server agent module through the transmission bus.

8. The chip remote debugging device according to claim 7, characterized in that: The debug gating circuit selectively connects the server agent module to the debug driving circuits of at least two of the circuit boards.

9. The chip remote debugging device according to claim 1, characterized in that: The server agent module is a baseboard management controller BMC; The transmission bus is an SM bus.

10. The chip remote debugging device according to claim 1, characterized in that: The onboard chip is any one of a central processing unit (CPU), a graphics processing unit (GPU), a tensor processing unit (TPU), a neural network processing unit (NPU), a deep learning processing unit (DPU), an acceleration processing unit (APU), and a general-purpose graphics processing unit (GPGPU); The debugging bus is a JTAG bus.

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