Circuit of frequency converter for suppressing bus voltage by using piezoresistor
By connecting the varistor in parallel at both ends of the inverter busbar and clamping the overvoltage with its threshold characteristics, the problem of capacitance damage caused by excessive inverter busbar voltage is solved, and effective protection of the inverter is achieved.
Patent Information
- Application Number
- CN202421294968.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-06-07
- Publication Date
- 2025-04-25
- Estimated Expiration
- 2034-06-07
AI Technical Summary
The existing inverters lack effective suppression measures when the bus voltage is too high, resulting in damage to the capacitor and affecting the normal operation of the equipment.
Two varistors are used to connect in parallel at both ends of the busbar. Using the threshold characteristics of the varistor, when the bus voltage rises to the threshold, the varistor is turned on, clamped the overvoltage, and protects other devices in the circuit.
It effectively suppresses abnormal overvoltage of busbar, prevents capacitor damage, and ensures the normal operation of the inverter.
Smart Images
Figure CN222802545U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to a circuit for a frequency converter which uses a varistor to suppress a bus voltage. Background Art
[0002] Frequency converter is a common speed regulating device in industrial automation. For example, it is widely used in the fields of steel, mining, and transportation. Equipment names such as stamping machines, sanding machines, belt conveyors, etc., frequency converter drives the motor to adjust the speed to meet specific working conditions.
[0003] The DC bus of the inverter rises. There are generally two situations in actual operating conditions: one is that the bus voltage will rise during the deceleration process of the inverter; the other is that when the motor is dragging the load and the motor connected to the inverter is in the power generation state, for the inverter, the power generation state means charging the capacitor of the DC bus, and the DC bus voltage will rise at this time. How high the voltage can rise is limited by the capacitor specifications. If the voltage continues to rise, the inverter must alarm and shut down, otherwise it will cause damage and burn of the capacitor. The aforementioned control circuit mainly solves the problem that when the inverter is running at a uniform speed, external factors cause the load speed ωr to be greater than the given speed ωe, commonly known as the motor being dragged. Under this condition, if there is no corresponding countermeasure, the inverter will cause an alarm and the machine will shut down due to overvoltage of the DC bus, affecting the normal operation of the equipment.
[0004] There are three existing strategies for DC bus voltage control:
[0005] One is to install a braking unit and a braking resistor on the inverter DC bus. This solution is currently the most commonly used. When the bus voltage rises to a certain level, the voltage will be discharged through the braking resistor to protect the capacitor. However, this solution is energy-consuming and is not suitable for flammable applications, such as oil mines, underground, chemical fibers, etc.
[0006] The second is to install an energy feedback device at the front end of the inverter. Although this solution is more energy-efficient than the above solution and can feed back the recovered bus voltage to the power system, a set of feedback equipment is equivalent to the price of nearly two sets of inverters. In addition to the high price, the large size of the feedback equipment and the requirements for grid noise resistance also make it beyond the reach of many owners.
[0007] The third is to connect the bus capacitors of multiple inverters in parallel. This solution is mostly used in applications where multiple inverters are used at the same time, such as belt conveyors. This solution is not suitable for a single inverter, and unstable control is also the main criticism.
[0008] Some of the existing circuits for suppressing bus voltage are not applicable in some scenarios, or affect the normal operation of the machine, or consume energy. In addition, the implementation method is complex and the implementation cost is high, which is obviously not a good choice. Utility Model Content
[0009] The utility model aims to overcome the existing defects and provides a frequency converter circuit which uses a varistor to suppress bus voltage, which can suppress abnormal bus overvoltage in the circuit and protect the circuit from damage by overvoltage.
[0010] The technical solution to achieve the above purpose is:
[0011] A frequency converter circuit that uses a varistor to suppress a bus voltage includes: a signal voltage input terminal, the signal voltage input terminal is respectively connected to one end of a first varistor and a second varistor, the other ends of the first varistor and the second varistor are both connected to a ground terminal, the other ends of the first varistor and the second varistor are also both connected to a test point terminal, the signal voltage input terminal is respectively connected to one end of a first energy storage capacitor and a second energy storage capacitor, the other ends of the first energy storage capacitor and the second energy storage capacitor are both connected to the ground terminal.
[0012] Preferably, the first varistor and the second varistor are respectively connected in parallel at two ends of the busbar.
[0013] Preferably, the first energy storage capacitor and the second energy storage capacitor are both connected in parallel with the first varistor and the second varistor.
[0014] Preferably, both ends of the first varistor and the second varistor are connected to other components of the inverter via a busbar.
[0015] The beneficial effect of the utility model is that the utility model connects two varistors in parallel at both ends of the bus, so that when the output end of the inverter is in a power generation state, the bus voltage increases. When the bus voltage reaches the threshold value of the varistor, the varistor is turned on to clamp the abnormal bus overvoltage, thereby protecting other devices in the circuit and preventing other components in the circuit from being damaged by the impact of overvoltage, thereby achieving the purpose of protecting the inverter. BRIEF DESCRIPTION OF THE DRAWINGS
[0016] Figure 1 The utility model discloses a circuit diagram of a frequency converter which utilizes a varistor to suppress bus voltage. DETAILED DESCRIPTION
[0017] The technical solution of the present invention will be described clearly and completely below in conjunction with the accompanying drawings. In the description of the present invention, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inside", "outside" and the like indicate directions or positional relationships based on the directions or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific direction, be constructed and operated in a specific direction, and therefore cannot be understood as a limitation on the present invention. In addition, the terms "first", "second", and "third" are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance.
[0018] The utility model will be further described below in conjunction with the accompanying drawings.
[0019] like Figure 1 As shown, a circuit of an inverter using a varistor to suppress a bus voltage includes: a signal voltage input terminal VIN, the signal voltage input terminal VIN is respectively connected to one end of a first varistor RV1 and a second varistor RV2, the other ends of the first varistor RV1 and the second varistor RV2 are both connected to a ground terminal GND, the other ends of the first varistor RV1 and the second varistor RV2 are also both connected to a test point terminal TP4, the signal voltage input terminal VIN is respectively connected to one end of a first energy storage capacitor C40 and a second energy storage capacitor C44, the other ends of the first energy storage capacitor C40 and the second energy storage capacitor C44 are both connected to the ground terminal GND.
[0020] In the embodiment, the first varistor RV1 and the second varistor RV2 are respectively connected in parallel at both ends of the bus. When the motor connected to the output terminal of the inverter is in a power generation state, that is, when the voltage of the signal voltage input terminal VIN increases, the bus voltage will increase. When the bus voltage is too high and reaches the threshold value of the first varistor RV1 and the second varistor RV2, the first varistor RV1 and the second varistor RV2 are turned on to release the overvoltage, thereby protecting other components of the inverter from damage.
[0021] In the embodiment, the first energy storage capacitor C40 and the second energy storage capacitor C44 are both connected in parallel with the first varistor RV1 and the second varistor RV2.
[0022] In the embodiment, two ends of the first varistor RV1 and the second varistor RV2 are connected to other components of the inverter through a bus bar.
[0023] The first varistor RV1 and the second varistor RV2 are connected in parallel to the bus voltage output. The biggest feature of the varistor is that when the voltage applied to it is lower than its threshold value "UN", the current flowing through it is extremely small, which is equivalent to a closed valve. When the input voltage exceeds its threshold value "UN", its resistance value becomes smaller, so that the current flowing through it surges while the impact on other circuits does not change much, thereby reducing the impact of overvoltage on subsequent sensitive circuits. By using this function, the abnormal bus overvoltage in the circuit can be suppressed, and the circuit can be protected from damage by overvoltage, thereby protecting other devices in the circuit and preventing other components in the circuit from being damaged by overvoltage, thereby achieving the purpose of protecting the inverter.
[0024] The above embodiments are only used to illustrate the technical solution of the utility model, rather than to limit it. Although the utility model is described in detail with reference to the above embodiments, ordinary technicians in this field should understand that they can still modify the technical solutions recorded in the above embodiments, or replace some or all of the technical features therein with equivalents. These modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the utility model.
Claims
1. A circuit for frequency converter using varistor to suppress bus voltage, characterized in that: include: A signal voltage input terminal (VIN), the signal voltage input terminal (VIN) is respectively connected to one end of a first varistor (RV1) and a second varistor (RV2), the other ends of the first varistor (RV1) and the second varistor (RV2) are both connected to a ground terminal (GND), the other ends of the first varistor (RV1) and the second varistor (RV2) are also both connected to a test point terminal (TP4), the signal voltage input terminal (VIN) is respectively connected to one end of a first energy storage capacitor (C40) and a second energy storage capacitor (C44), the other ends of the first energy storage capacitor (C40) and the second energy storage capacitor (C44) are both connected to the ground terminal (GND).
2. The circuit for suppressing bus voltage by using a varistor in a frequency converter according to claim 1, characterized in that: The first varistor (RV1) and the second varistor (RV2) are respectively connected in parallel at two ends of the busbar.
3. The circuit for suppressing bus voltage by using a varistor in a frequency converter according to claim 1, characterized in that: The first energy storage capacitor (C40) and the second energy storage capacitor (C44) are both connected in parallel with the first varistor (RV1) and the second varistor (RV2).
4. The circuit for suppressing bus voltage by using a varistor in a frequency converter according to claim 1, characterized in that: Two ends of the first varistor (RV1) and the second varistor (RV2) are connected to other components of the inverter through a busbar.