Full-localization shortwave board card type receiver

Abstract

The utility model discloses a full-localization shortwave board card type receiver, which belongs to the technical field of wireless communication equipment, and comprises a superheterodyne radio frequency module, an acquisition processing module and a source module, the superheterodyne radio frequency module is used for receiving carrier frequency signals and generating oscillation signals by arranging an oscillation circuit to mix the oscillation signals with the received carrier frequency signals; the acquisition and processing module comprises a radio frequency acquisition module and a digital processing module, the radio frequency acquisition module receives the intermediate frequency signal and the carrier frequency signal, carries out filtering processing on the received signal and then carries out digitization, and the digital processing module is connected with the acquisition and processing module. The digital processing module is used for performing digital-to-analog conversion on the digitized signals and distributing the digitized signals; the source module is used for calibrating and adjusting the clock frequency of the superheterodyne radio frequency module and the clock frequency of the acquisition processing module through an external input reference clock and pulse per second, and the application adopts a modular design to adapt to various application scenes, so that the receiving equipment has high portability and flexibility.

Description

Technical Field

[0001] The utility model belongs to the technical field of wireless communication equipment, and specifically relates to a domestically produced shortwave card-type receiver. Background Art

[0002] With the rapid development of digital technology, the digitalization degree of shortwave communication systems is also constantly improving. As the front-end equipment of shortwave communication systems, the digital processing capability of shortwave card-type receivers is crucial to improving the performance of the entire system. At the same time, shortwave card-type receivers meet the needs of a wide range of applications in the fields of communication equipment, improve communication quality, reduce manufacturing and maintenance costs, meet market demand, and promote technological innovation.

[0003] Existing receivers have the following disadvantages:

[0004] 1. The application scenarios of existing receivers are limited, it is inconvenient to connect to computers or other devices, and the portability and flexibility are low.

[0005] 2. Low compatibility and scalability, inconvenience in integration with other devices and systems. Utility Model Content

[0006] In order to solve the problems raised in the above background technology, the utility model provides a domestically produced shortwave board-type receiver to solve the problems that the probe fragments dropped during the EL detection method may damage the battery cell and the probe pressing down the silicon oxide film may cause inconsistent local excitation current.

[0007] In order to achieve the above purpose, the utility model provides the following technical solutions:

[0008] A nationally produced shortwave card-type receiver, comprising:

[0009] Superheterodyne RF module: The superheterodyne RF module is used to receive a carrier frequency signal, and generate an oscillation signal by setting an oscillation circuit to mix with the received carrier frequency signal to obtain an intermediate frequency signal;

[0010] Acquisition and processing module: The acquisition and processing module is connected to the superheterodyne RF module. The acquisition and processing module includes an RF acquisition module and a digital processing module. The RF acquisition module receives the intermediate frequency signal and digitizes the received signal after filtering. The digital processing module is connected to the acquisition and processing module. The digital processing module is used to perform digital-to-analog conversion on the digitized signal and distribute it.

[0011] Source module: The acquisition processing module and the superheterodyne RF module are both connected to the source module, which is used to calibrate and adjust the clock frequency of the superheterodyne RF module and the acquisition processing module through external input reference clock and second pulse.

[0012] Preferably, the superheterodyne radio frequency module comprises:

[0013] Attenuator; the attenuator is used to set the attenuation state of the received carrier frequency signal;

[0014] Limiter: The limiter is connected to the attenuator, and the limiter is used to limit the amplitude of the attenuated signal to a preset range;

[0015] Intermediate frequency amplifier: The intermediate frequency amplifier is connected to the limiter, and is used to amplify the signal output by the limiter;

[0016] Mixer: The mixer is connected to the intermediate frequency amplifier. The mixer is used to adjust the output signal of the intermediate frequency amplifier processor to the required frequency to obtain an intermediate frequency signal.

[0017] Preferably, the acquisition processing module includes:

[0018] Balun transformer: The balun transformer is connected to the mixer. The balun transformer is used to receive the intermediate frequency signal and perform impedance conversion.

[0019] Low-pass filter: The balun transformer is connected to the low-pass filter, and the signal after impedance conversion is suppressed by the low-pass filter;

[0020] Programmable gain amplifier: The programmable gain amplifier is used to amplify the suppression signal;

[0021] High-speed AD acquisition module: The high-speed AD acquisition module is connected to the programmable gain amplifier, and the high-speed AD acquisition module is used to digitize the amplified intermediate frequency signal at a sampling rate of 102.4 MHz.

[0022] Preferably, the digital processing module is constructed using FPGA+ARM, the FPGA is connected to the high-speed AD acquisition module, the FPGA is used to realize ADC analog-to-digital conversion, DAC digital-to-analog conversion and DDC digital signal processing, and the ARM is used to distribute the processing result data of the FPGA.

[0023] Compared with the prior art, the beneficial effects of the utility model are:

[0024] 1. The application adopts a modular design, which can be easily inserted into a computer or other device to adapt to various application scenarios, making the receiving device highly portable and flexible.

[0025] 2. This receiver has good compatibility and expansibility and can be easily integrated with other devices and systems. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 This is a schematic diagram of the working principle of this application;

[0027] Figure 2 This is a schematic diagram of the working principle of radio frequency collection of this application;

[0028] Figure 3 This is a schematic diagram of the working principle of the digital processing module of this application;

[0029] Figure 4 Figure 2 is a schematic diagram of the working principle of the source module. DETAILED DESCRIPTION

[0030] The following will be combined with the drawings in the embodiments of the utility model to clearly and completely describe the technical solutions in the embodiments of the utility model. Obviously, the described embodiments are only part of the embodiments of the utility model, not all of the embodiments. Based on the embodiments in the utility model, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the utility model.

[0031] like Figure 1 As shown, a domestically produced shortwave card-type receiver comprises:

[0032] Superheterodyne RF module: generates an oscillation signal by setting up a local oscillation circuit, and mixes it with the received carrier signal to obtain an intermediate frequency signal;

[0033] The superheterodyne RF module includes:

[0034] Attenuator: It has multiple attenuation state configuration functions such as serial, direct parallel, and latched parallel, which can reduce the blocking effect of large signals on the mixer, and at the same time improve the input second-order intercept point value and input third-order intercept point value indicators of the channel. Selecting direct pass can ensure the normal reception of small signals;

[0035] Limiter: The frequency coverage range is DC~6GHz, and the insertion loss is less than 0.1dB in the full frequency band. The limiter level is 10dBm, which protects the channel from damaging the circuit. The preselector ensures that the second-order intercept value of the entire receiving channel input meets the requirements.

[0036] Bandpass filter: can suppress the aliasing signal of AD sampling;

[0037] IF amplifier: low noise amplifier to ensure the overall gain of the link;

[0038] Mixer: ensures sensitivity and dynamics; adopts a single-conversion superheterodyne system. In order to ensure the performance of A / D sampling, a 50kHz bandwidth crystal filter is used in the intermediate frequency to ensure out-of-band suppression and smaller in-band loss.

[0039] like Figure 2As shown, the principle of the RF acquisition module is as follows: this part has a self-test signal input interface, and the self-test signal is switched through a relay. The 10dB attenuator can be selected to access the channel or bypass through the relay to realize the selection of the normal mode and the large dynamic mode. After the RF signal is input to the receiver, it is first connected to the self-test signal switching circuit. The self-test signal is attenuated by the attenuator and then switched through the relay, and the module performs offline detection; at the same time, the online detection function is reserved, and the self-test signal is coupled to the input end of the receiving module by the resistor coupler for self-test testing; only one of the two functions can be selected, which is selected by selecting the welding resistor. The self-test signal uses a single-chip SPI control oscillator. Then the signal enters the limiter, the maximum input power can reach 33dBm, and the typical output power is 13dBm. After that, the signal enters the receiving mode selection circuit. When the 10dB attenuator is bypassed through the relay, the normal receiving mode is realized; when the 10dB attenuator is enabled through the relay, the large dynamic receiving mode is realized. Finally, the signals enter the bandpass filter respectively. The passband range of the bandpass filter is 50MHz. In order to ensure the performance, high-performance bandpass filter finished products are purchased directly. The low-pass filter has a passband cutoff frequency of 50MHz and is built with a wound inductor.

[0040] All relays in the RF section use low insertion loss relays, with insertion loss below 0.05dB in the shortwave band. In addition, the relay has an isolation of more than 50dB, more than 100,000 switching times, and a switching time of less than 3ms. Since the relay switch is mainly used for self-test source switching and receiving mode switching, these switching are not frequent, so the switching time of 3ms is acceptable.

[0041] The programmable gain amplifier in the RF part adopts the industry's low-noise high-dynamic amplifier, with a maximum gain of 26dB, a variable gain range of more than 30dB, good HD2, HD3 suppression capabilities, and excellent output third-order intercept point indicators. In the three cases of gain of 6dB, 14dB and 26dB, the third-order intermodulation products are all below -100dBc. Since the output level is 2Vp-p in this case, the OIP3 is converted to more than 54dBm. The noise figure of the amplifier is 6.5dB at the maximum gain, especially when its link gain attenuation is no more than 12dB, its noise figure deterioration does not exceed 1.2dB, which is of great significance for broadband applications, and it is also relatively easy to achieve the best coordination between the digital processing part and the RF acquisition part.

[0042] Acquisition and processing module: The acquisition and processing module is mainly composed of the RF acquisition module and the digital processing module. The RF acquisition module mainly completes signal filtering processing, coupling input of self-test signals, normal / large dynamic mode realization, AD acquisition, etc.; the digital processing module mainly realizes digital signal processing, gain adjustment, digital down-conversion, demodulation and other processing, and performs data transmission and related control through the PCIe high-speed interface.

[0043] The main working module of the shortwave full-band RF acquisition part is the AD acquisition module. The AD acquisition module consists of 1 high-speed AD to complete the direct digitization of the shortwave full-band RF signal. Since the output impedance of the RF preselection module is 50 ohms, but most high-speed ADs have higher input impedance, the input coupling circuit needs to complete the matching between the two. At present, most high-speed AD acquisition cards can choose two input coupling methods: high-performance op amp coupling or transformer coupling. The former is suitable for relatively low-frequency digital acquisition, and the latter is mainly used in scenarios with harsh noise and dynamic indicators. The AD acquisition module adopts transformer coupling. After input coupling, the single-ended signal is converted into a differential signal through a balun, and then sent to the AD chip after passing through a low-pass filter. The low-pass filter ensures the anti-aliasing performance of AD sampling and is mainly used for AD image frequency suppression. The AD sampling clock of the module is 102.4MHz, and its image frequency suppression point is 102.4MHz-30MHz=72.4MHz. It is usually required that its image frequency suppression is better than 100dB. The digital signal output by the AD conversion is driven by the BUFFER and output to the FMC interface to the broadband monitoring processing module for processing.

[0044] like Figure 3 As shown, the digital processing module includes:

[0045] FPGA: It is used to realize various functions such as input and output interface, general digital logic, memory, digital signal processing, clock management, etc. It also provides abundant dedicated clock and wiring resources. It is suitable for realizing complex and high-speed digital logic circuits and has the characteristics of low power consumption, small size packaging and high performance.

[0046] ARM: It uses a high-performance and low-power application processor with a maximum frequency of 2.0GHz. It provides many embedded powerful hardware engines for high-end applications. It supports almost all formats of H.264 decoders and has a high-performance external memory interface (DDR3 / DDR3L / DDR3 / LPDDR3 / LPDDR4 / LPDDR4X) that can maintain the required memory bandwidth.

[0047] The digital processing module is built with FPGA+ARM. FPGA needs to complete ADC analog-to-digital conversion, DAC digital-to-analog conversion, RF control and other related functions, and realize broadband channelization, narrowband DDC digital signal processing and other related functions, which consumes a lot of logic resources. ARM is mainly used for receiver resource management, processing flow control and distribution of various processing result data. The working principle of the processing module is as follows Figure 3As shown in the figure, the ARM of the processing module is equipped with a Gigabit Ethernet port as standard, and the FPGA can select a 10G optical port or a Gigabit Ethernet port by configuring the IO port. The Gigabit Ethernet port of the ARM is used to receive external commands and output various processing results, such as: panoramic display spectrum, ITU monitoring, demodulation results, audio, etc. The 10G Ethernet port configured by the FPGA is mainly used for the output of broadband raw IQ data.

[0048] The digital processing module is built with FPGA+ARM. The FPGA needs to complete ADC analog-to-digital conversion, DAC digital-to-analog conversion, RF control and other related functions, and realize broadband channelization, narrowband DDC digital signal processing and other related functions, which consumes a lot of logic resources. ARM is mainly used for receiver resource management, processing flow control and distribution of various processing result data. The ARM of the processing module is equipped with a standard Gigabit network port, and the FPGA can select a 10G optical port or a Gigabit network port by configuring the IO port. The Gigabit network port of ARM is used to receive external commands and output various processing results, such as: panoramic display spectrum, ITU monitoring, demodulation results, audio, etc. The 10G network port configured by FPGA is mainly used for the output of broadband original IQ data.

[0049] Source module: Figure 4 As shown, the source module is mainly used in the receiver, and uses the external input reference high-precision clock, second pulse and software interface control to realize clock frequency calibration and adjustment, and divides the clock signal generated by the crystal oscillator for use by the RF module.

[0050] The reference high-precision clock, second pulse signal and adjustment control interface are all input into the FPGA. The FPGA detects each input signal, adjusts the input signal according to the priority, calculates the control code and outputs it to the DAC. The voltage output by the DAC is filtered and output to the control voltage input of the constant temperature crystal oscillator to control the output frequency of the crystal oscillator. The output signal of the constant temperature crystal oscillator is amplified and divided into two signals. One signal is fed back to the FPGA to participate in the frequency adjustment calculation, and the second signal is output to the backplane and sent to the receiving module after amplification and power distribution. It is used for the receiver local oscillator reference and AD sampling clock.

[0051] In this embodiment, this application uses domestic chips to achieve complete independent control from chips to the whole machine. It not only improves the stability of equipment performance, but also reduces dependence on external supply chains and enhances information security. This application receives radio signals in the frequency range of 1.5 to 30MHz, adopts modular design, has the characteristics of simple link structure, large dynamic range, adaptability to various application scenarios and high sensitivity, and the radio frequency has one antenna input. This device uses advanced large-scale FPGA and has powerful digital signal processing capabilities. It can output full-band I / Q sub-bands, broadband spectrum and multi-channel narrowband DDC data, and supports multi-channel signal demodulation.

Claims

1. A domestically produced shortwave card-type receiver, characterized in that: include: Superheterodyne RF module: The superheterodyne RF module is used to receive a carrier frequency signal, and generate an oscillation signal by setting an oscillation circuit to mix with the received carrier frequency signal to obtain an intermediate frequency signal; Acquisition and processing module: the acquisition and processing module is connected to the superheterodyne RF module, and the acquisition and processing module includes an RF acquisition module and a digital processing module. After receiving the intermediate frequency signal, the RF acquisition module filters the received signal and then digitizes it. The digital processing module is connected to the acquisition and processing module, and the digital processing module is used to perform digital-to-analog conversion on the digitized signal and distribute it; Source module: The acquisition processing module and the superheterodyne RF module are both connected to the source module, which is used to calibrate and adjust the clock frequency of the superheterodyne RF module and the acquisition processing module through external input reference clock and second pulse.

2. A domestically produced shortwave card-type receiver according to claim 1, characterized in that: The superheterodyne RF module includes: Attenuator; the attenuator is used to set the attenuation state of the received carrier frequency signal; Limiter: The limiter is connected to the attenuator, and the limiter is used to limit the amplitude of the attenuated signal to a preset range; Intermediate frequency amplifier: The intermediate frequency amplifier is connected to the limiter, and is used to amplify the signal output by the limiter; Mixer: The mixer is connected to the intermediate frequency amplifier. The mixer is used to adjust the output signal of the intermediate frequency amplifier processor to the required frequency to obtain an intermediate frequency signal.

3. The domestically produced shortwave card-type receiver according to claim 2 is characterized in that: The acquisition and processing modules include: Balun transformer: The balun transformer is connected to the mixer. The balun transformer is used to receive the intermediate frequency signal and perform impedance conversion. Low-pass filter: The balun transformer is connected to the low-pass filter, and the signal after impedance conversion is suppressed by the low-pass filter; Programmable gain amplifier: The programmable gain amplifier is used to amplify the suppression signal; High-speed AD acquisition module: The high-speed AD acquisition module is connected to the programmable gain amplifier, and the high-speed AD acquisition module is used to digitize the amplified intermediate frequency signal at a sampling rate of 102.4 MHz.

4. The domestically produced shortwave card-type receiver according to claim 3 is characterized in that: The digital processing module is built with FPGA+ARM. The FPGA is connected to the high-speed AD acquisition module. The FPGA is used to realize ADC analog-to-digital conversion, DAC digital-to-analog conversion and DDC digital signal processing. The ARM is used to distribute the processing result data of the FPGA.

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