Semiconductor device

Abstract

A semiconductor device includes a plurality of semiconductor layers each extending in a first lateral direction and vertically spaced apart from each other, and a metal gate structure extending in a second lateral direction and including a plurality of regions. Each semiconductor layer is surrounded by adjacent regions. The semiconductor device also comprises a plurality of inner spacing layer pairs which are respectively arranged beside one end part of one corresponding area part. The semiconductor device also includes a source / drain structure pair in contact with a plurality of end portions of each of the semiconductor layers, respectively. The region portion is electrically isolated from the source / drain structure pair by the inner spacer layer pair. Among the semiconductor layers in the first lateral direction, a lower semiconductor layer is shorter than an upper semiconductor layer.

Description

Technical Field

[0001] The utility model relates to a semiconductor technology, in particular to a semiconductor device. Background Art

[0002] The semiconductor industry has experienced rapid growth due to the increasing integration density of various electronic components, such as transistors, diodes, resistors, capacitors, etc. In most cases, this increase in integration density comes from the continuous reduction in the minimum feature size, which allows more components to be integrated into a given area. Utility Model Content

[0003] The purpose of the present invention is to provide a semiconductor device to solve at least one of the above problems.

[0004] In some embodiments, a semiconductor device is provided, comprising: a plurality of semiconductor layers vertically spaced apart from each other, wherein each semiconductor layer extends along a first lateral direction; a metal gate structure extending along a second lateral direction and comprising a plurality of sections, wherein each layer in the semiconductor layer is surrounded by adjacent sections in the sections; a plurality of inner spacer layer pairs, wherein the inner spacer layer pairs are respectively arranged beside an end of a corresponding section in the sections; and a source / drain structure pair respectively contacting a plurality of ends of each of the semiconductor layers, wherein the sections are electrically isolated from the source / drain structure pair by the inner spacer layer pairs; wherein along the first lateral direction, the semiconductor layer located below in the semiconductor layer is shorter than the semiconductor layer located above.

[0005] According to one embodiment of the present invention, along the first transverse direction, the lower section among the plurality of sections is shorter than the upper section.

[0006] According to one embodiment of the present invention, a dielectric layer pair is further included, formed correspondingly below the source / drain structure pair.

[0007] According to one embodiment of the present invention, the dielectric layer pair is separated from a lower surface of a lowermost section among the plurality of sections.

[0008] According to one embodiment of the present invention, a dielectric layer is further included, which is formed directly below the metal gate structure.

[0009] According to one embodiment of the present invention, the dielectric layer is in contact with a lower surface of a lowermost region among the plurality of regions and the source / drain structure pair.

[0010] According to one embodiment of the present invention, the dielectric layer further extends below the source / drain structure pair.

[0011] According to one embodiment of the present invention, the dielectric layer pair is in contact with a lower surface of a lowermost region among the plurality of regions and a lower surface of the source / drain structure pair.

[0012] According to one embodiment of the present invention, along the first lateral direction, the uppermost semiconductor layer among the plurality of semiconductor layers has a first length, and the uppermost region among the plurality of regions has a second length smaller than the first length.

[0013] According to one embodiment of the present invention, along the first lateral direction, the semiconductor layer located at the bottom of the plurality of semiconductor layers has a first length, and the region located at the bottom of the plurality of regions has a second length smaller than the first length. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 A schematic perspective view of a gate-all-around (GAA) field effect transistor (FET) device according to some embodiments is shown.

[0015] Figure 2 An exemplary flow chart illustrating a method of manufacturing a non-planar transistor device according to some embodiments.

[0016] Figure 3 , Figure 4 , Figure 5 , Figure 6 , Figure 7 , Figure 8 , Fig. 9 , Fig.10 , Fig.11 , Fig.12 , Fig.13 , Fig.14 and Fig.15 According to some embodiments, Figure 2 Schematic cross-sectional views of an exemplary gate-all-around field effect transistor (GAA FET) device (or a partial exemplary gate-all-around field effect transistor (GAA FET) device) fabricated by the method at various fabrication stages.

[0017] Fig.16 , Fig.17 , Fig.18 and Fig.19 According to some embodiments Fig.14 Schematic cross-section of a gate-all-around field-effect transistor (GAA FET) device.

[0018] The reference numerals are as follows:

[0019] 100: Gate All Around Field Effect Transistor (GAA FET) Device

[0020] 102: Base

[0021] 104,710,720: Semiconductor layer / nanostructure

[0022] 106: Quarantine

[0023] 108: Gate structure

[0024] 110: Source / drain structure

[0025] 112: Interlayer dielectric (ILD) layer

[0026] 200: Method

[0027] 202, 204, 206, 208, 210, 212, 214, 216, 218: Operation step 300: Gate all-around field effect transistor (GAAFET) device

[0028] 302: Semiconductor substrate

[0029] 401: Stacked structure

[0030] 401-1: Part 1

[0031] 401-2: Part 2

[0032] 401A: Side wall

[0033] 410: first semiconductor layer

[0034] 420: Second semiconductor layer

[0035] 502: Isolation Structure

[0036] 602: Virtual gate structure

[0037] 701: First etching process

[0038] 702: Gate spacer

[0039] 710A, 720A: The top semiconductor layer

[0040] 710B, 720B: The middle semiconductor layer

[0041] 710C, 720C: The bottom semiconductor layer

[0042] 801: Second etching process

[0043] 1002: Inner spacer

[0044] 1202: epitaxial structure

[0045] 1402: Active gate structure

[0046] 1402A, 1402B, 1402C: District Office

[0047] 1702,1802,1902: Dielectric layer

[0048] L 710A ,L 710B ,L 710C ,L 720A ,L 720B ,L 720C : Vertical length DETAILED DESCRIPTION

[0049] The following disclosure provides many different embodiments or examples to implement different characteristic components of the present invention. The following disclosure is a specific example describing each component and its arrangement in order to simplify the present disclosure. Of course, these are only examples and are not used to define the present invention. For example, if the following disclosure describes that a first characteristic component is formed on or above a second characteristic component, it means that it includes an embodiment in which the first characteristic component and the second characteristic component are in direct contact, and also includes an embodiment in which an additional characteristic component can be formed between the first characteristic component and the second characteristic component, so that the first characteristic component and the second characteristic component may not be in direct contact. In addition, the present disclosure will repeat numbers and / or text in each different example. Repetition is for the purpose of simplification and clarification, rather than listing and specifying the relationship between the various different embodiments and / or configurations discussed.

[0050] Spatially related terms such as "under", "below", "down", "above", "above", "top", "bottom", etc. are used herein to easily express the relationship between an element or feature in the drawings shown in this specification and another element or feature. These spatially related terms not only cover the orientation shown in the drawings, but also cover different orientations of the device during use or operation. The device can have different orientations (rotated 90 degrees or other orientations) and the spatially related symbols used herein are also interpreted accordingly.

[0051] As the semiconductor industry has advanced to nanometer technology process nodes in pursuit of higher device density, higher performance and lower cost, challenges from manufacturing and design issues have led to the development of three-dimensional designs, such as multi-gate field effect transistors (FETs) (including fin field effect transistors (FinFETs) and gate-all-around field effect transistors (GAAFETs). In a fin field effect transistor (FinFET), the gate electrode is adjacent to three side surfaces of the channel region / structure, and a gate dielectric layer is sandwiched between the gate electrode and the channel region / structure. Since the gate structure surrounds (encloses) the fin on three surfaces, the transistor essentially has three gates to control the current through the fin or channel region. Unfortunately, the fourth side (i.e., the bottom of the channel) is far away from the gate electrode and is therefore not tightly controlled by the gate. In contrast, in a gate-all-around field effect transistor (GAA FET), all side surfaces of the channel region can be surrounded by the gate electrode, which enables the channel region to be more fully depleted and has a lowered drain induced barrier (DBB) due to a steeper sub-threshold current swing (SS) and a smaller drain. lowering,DIBL) to make the short channel effect smaller.

[0052] As transistors continue to shrink to sub-10-15nm technology nodes, further improvements are needed in gate-all-around field effect transistors (GAAFETs). For example, a gate-all-around field effect transistor (GAA FET) typically has a channel structure formed by many nanostructures (e.g., nanosheets). These nanostructures are vertically spaced apart from each other in the vertical direction, allowing the gate structure of the gate-all-around field effect transistor (GAA FET) to surround each nanostructure. In the prior art, the source / drain structure of a gate-all-around field effect transistor (GAA FET) is typically formed by regrowth of an epitaxial structure from the exposed sidewalls of the nanostructure. Generally, the sidewalls are exposed by performing an anisotropic etching process on a stacked structure having nanostructures. The anisotropic etching process itself may etch the upper nanostructure more than the lower nanostructure. In other words, the lower nanostructure may have a longer longitudinal length than the upper nanostructure. Such "extended" length of one or more nanostructures may be detrimental to the performance of the corresponding GAAFET, such as higher channel resistance, higher channel capacitance, etc. Therefore, the GAAFET formed in the prior art is not completely satisfactory in many aspects.

[0053] Embodiments of the present disclosure are described in the context of forming a nanostructured field effect transistor (FET) device (sometimes referred to as a gate-all-around field effect transistor (GAAFET) device), and in particular in the context of forming a channel structure of a gate-all-around field effect transistor (GAA FET) device. In some aspects of the present disclosure, a stack (which includes a plurality of semiconductor channel layers separated from each other by corresponding semiconductor sacrificial layers) is patterned at least by a series of etching processes. For example, a first etching process having anisotropic properties may be first performed on the stack to remove a first portion of the stack and expose the sidewalls of each semiconductor channel layer. Next, a second etching process having isotropic properties may be performed to push the sidewalls of each semiconductor channel layer inward. Therefore, after the first etching process, the longer lower semiconductor channel layer may be trimmed to be shorter by the second etching process. In this way, the above-mentioned technical problem may be solved. Alternatively or additionally, for some applications, the lower semiconductor channel layer may be trimmed to be even shorter than the upper semiconductor channel layer.

[0054] Figure 1 A perspective schematic diagram of an exemplary nanostructure transistor device (e.g., a gate-all-around field effect transistor (GAA FET) device) 100 according to various embodiments is shown. The gate-all-around field effect transistor (GAA FET) device 100 includes a substrate 102 and a plurality of nanostructures (e.g., nanosheets, nanowires, etc.) 104 located above the substrate 102. The semiconductor layers 104 are vertically spaced apart from each other. An isolation region 106 is formed on two opposite sides of a protruding portion of the substrate 102, wherein the nanostructures 104 are disposed above the protruding portion. A gate structure 108 surrounds each nanostructure 104 (e.g., the entire periphery of each nanostructure 104). A source / drain structure is disposed on opposite sides of the gate structure 108, for example, Figure 1 The source / drain structure 110 is shown. An interlayer dielectric (ILD) layer 112 is disposed above the source / drain structure 110 .

[0055] It should be understood that Figure 1 A simplified GAA FET device is shown, and therefore, one or more features of a complete GAA FET device may not be shown. Figure 1 For example, Figure 1 Not shown in the figure is another source / drain structure of the gate structure 108 opposite to the source / drain structure 110 and an interlayer dielectric (ILD) layer disposed above the source / drain structure. Figure 1As a comparison, multiple cross sections in subsequent figures are shown. As shown in the figure, cross section AA is taken along the longitudinal axis of the gate structure 108 (e.g., along the X direction); cross section BB is taken along the longitudinal axis of one of the semiconductor layers 104 and the current flow direction between the source / drain structures (e.g., the Y direction). For clarity, subsequent figures can refer to these comparison cross sections.

[0056] Figure 2 A flow chart of a method 200 for forming a nanostructure transistor device according to one or more embodiments of the present disclosure is shown. For example, at least some operations (or steps) of method 200 may be used to form a fin field effect transistor (FinFET) device, a gate-all-around field effect transistor (GAA FET) device (e.g., gate-all-around field effect transistor (GAA FET) device 100), a nanosheet transistor device, a nanowire transistor device, a vertical transistor device, at least a portion of a complementary field effect transistor device, or the like. It should be noted that method 200 is merely an example and is not intended to limit the present invention. Therefore, it should be understood that the method 200 may be used in the following manner: Figure 2 Additional operations are provided before, during, and after method 200. Figure 2 , and some other operations are only briefly described here. In some embodiments, the operations of method 200 can be associated with a cross-sectional schematic diagram of an exemplary gate all-around field effect transistor (GAA FET) device at various manufacturing stages, such as Figure 2 and Figure 3 Please refer to Figure 3 , Figure 4 , Figure 5 , Figure 6 , Figure 7 , Figure 8 , Fig. 9 , Fig.10 , Fig.11 , Fig.12 , Fig.13 , Fig.14 and Fig.15 , which will be described in further detail below.

[0057] Briefly, the method 200 begins at operation step 202, where a substrate is provided. The method 200 proceeds to operation step 204, where a stacked structure including a plurality of first semiconductor layers and a plurality of second semiconductor layers is formed. The method 200 proceeds to operation step 206, where an isolation structure is formed. The method 200 proceeds to operation step 208, where a dummy gate structure is formed. The method 200 proceeds to operation step 210, where a first portion of the stacked structure that is not covered by the dummy gate structure is removed by a first etching process. The method 200 proceeds to operation step 212, where a second portion of the stacked structure is removed by a second etching process. The second portion is located on the side of the lower portion of the first portion along the longitudinal direction of the stacked structure. In some embodiments, the first etching process and the second etching process may have respective conditions to achieve different etching directions. The method 200 proceeds to operation step 214, where an inner isolation layer is formed. The method 200 proceeds to operation step 216, where a source / drain structure is formed. The method 200 proceeds to operation step 218, where an active gate structure surrounding each second semiconductor layer is formed.

[0058] As mentioned above, Figure 3-Figure 15 Show Figure 2 Schematic cross-sectional view of a partial gate all-around field effect transistor (GAA FET) device 300 at various stages of manufacturing of the method 200. The gate all-around field effect transistor (GAA FET) device 300 is similar to Figure 1 The gate-all-around field effect transistor (GAA FET) device 100 is shown, but for the purpose of simplicity, some features / structures / areas are not shown. For example, the gate-all-around field effect transistor (GAA FET) device 300 of the following figures does not include a source / drain structure (e.g., Figure 1 It should be understood that the gate all-around field effect transistor (GAAFET) device 300 may also include many other devices (not shown in the following figures), such as inductors, fuses, capacitors, coils, etc., but are still within the scope of the present disclosure.

[0059] Corresponds to Figure 2 Operation step 202. Figure 3 A schematic cross-sectional view of a gate-all-around field effect transistor (GAA FET) device 300 including a semiconductor substrate 302 is shown at one of various manufacturing stages. Figure 3 The image is taken perpendicular to the length direction of the active / dummy gate structure of the gate-all-around field effect transistor (GAA FET) device 300 (eg, Figure 1 AA in FIG.

[0060] Substrate 302 may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, or the like, which may be doped (e.g., with a p-type or n-type dopant) or undoped. Substrate 302 may be a wafer, such as a silicon wafer. In general, a semiconductor-on-insulator (SOI) substrate includes a semiconductor material layer formed on an insulating layer. The insulating layer may be a buried oxide (BOX) layer, a silicon oxide layer, or the like. The insulating layer is disposed on a substrate, typically a silicon or glass substrate. Other substrates, such as multilayer or gradient substrates, may also be used. In some embodiments, the semiconductor material of substrate 302 may include silicon, germanium; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide and / or indium antimonide); alloy semiconductors, including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP and / or GaInAsP; or combinations thereof.

[0061] Corresponds to Figure 2 Operation step 204. Figure 4 A schematic cross-sectional view of a gate all-around field effect transistor (GAA FET) device 300 is shown, wherein a plurality of first semiconductor layers 410 and a plurality of second semiconductor layers 420 are formed on a substrate 302 during one of various manufacturing stages. Figure 4 The image is taken perpendicular to the length direction of the active / dummy gate structure of the gate-all-around field effect transistor (GAA FET) device 300 (eg, Figure 1 AA in FIG.

[0062] As shown, the first semiconductor layer 410 and the second semiconductor layer 420 are alternately disposed on each other (e.g., along the Z direction) to form a stack. For example, one of the second semiconductor layers 420 is disposed on one of the first semiconductor layers 410, and then another of the first semiconductor layers 420 is disposed on the second semiconductor layer 410, and so on. The stack may include any number of first semiconductor layers 410 and second semiconductor layers 420 that are alternately disposed. For example, in Figure 4 , the first stack includes three first semiconductor layers 410, three second semiconductor layers 420 are alternately disposed therebetween, and one of the second semiconductor layers 420 is the uppermost semiconductor layer. It should be understood that the gate all-around field effect transistor (GAAFET) device 300 may include any number of first semiconductor layers and any number of second semiconductor layers, wherein either the first or second semiconductor layer may be the uppermost semiconductor layer, while still being within the scope of the present disclosure.

[0063] The first and second semiconductor layers 410 and 420 may have different thicknesses. Furthermore, the first semiconductor layer 410 may have different thicknesses from one layer to another. The second semiconductor layer 420 may have different thicknesses from one layer to another. The thickness of each of the first and second semiconductor layers 410 and 420 may be in the range from a few nanometers to tens of nanometers. The first layer in the stack may be thicker than the other first and second semiconductor layers 410 and 420. In one embodiment, each first semiconductor layer 410 has a thickness in the range of about 5 nanometers (nm) to 20 nm, and each second semiconductor layer 420 has a thickness in the range of about 5 nm to 20 nm.

[0064] The two first and second semiconductor layers 410 and 420 have different compositions. In different embodiments, the two first and second semiconductor layers 410 and 420 have compositions that provide different oxidation rates and / or different etching selectivities between layers. In one embodiment, the first semiconductor layer 410 includes silicon germanium (Si 1-x Ge x ), and the second semiconductor layer includes silicon (Si). In one embodiment, each second semiconductor layer 420 may be undoped or substantially undoped silicon (i.e., having an extrinsic dopant concentration of about 0 cm -3 Up to 1×10 17 cm -3 In some embodiments, each first semiconductor layer 410 is Si 1-x Ge x , including Ge in a molar ratio of less than 50% (x < 0.5). For example, Ge may account for 1-x Ge x The molar ratio of the composition of the first semiconductor layer 410 is about 15% to 35%. Furthermore, the first semiconductor layer 410 may include compositions different from each other, and the second semiconductor layer 420 may include compositions different from each other.

[0065] Any of the first and second semiconductor layers 410 and 420 may include other materials, for example, compound semiconductors (such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide and / or indium antimonide), alloy semiconductors (such as GaAsP, AlInAs, AlGaAs, InGaAs, GaInP and / or GaInAsP) or combinations thereof. The materials of the first and second semiconductor layers 410 and 420 may be selected based on providing different oxidation rates and / or etching selectivities.

[0066] The first and second semiconductor layers 410 and 420 may be epitaxially grown from the semiconductor substrate 302. For example, each of the first and second semiconductor layers 410 and 420 may be grown by a molecular beam epitaxy (MBE) process, a chemical vapor deposition (CVD) (e.g., a metal organic chemical vapor deposition (MOCVD) process, and / or other suitable epitaxial growth processes. During the epitaxial growth, the crystal structure of the semiconductor substrate 302 extends upward, so that the first and second semiconductor layers 410 and 420 have the same crystal orientation as the semiconductor substrate 302.

[0067] When the first and second semiconductor layers 410 and 420 are grown on the semiconductor substrate 302, the first and second semiconductor layers 410 and 420 may be patterned to form one or more stacked structures (e.g., 401). Each stacked structure is elongated in a lateral direction (e.g., Y direction) and includes a stack of patterned first and second semiconductor layers 410-420 alternately disposed on each other. The stacked structure 401 is formed by patterning the first and second semiconductor layers 410-420 and the semiconductor substrate 302 using, for example, photolithography and etching techniques. For example, a mask layer (which may include a plurality of film layers, such as a pad oxide layer and a pad nitride layer located thereon) is formed on the uppermost semiconductor layer (e.g., Figure 4 The pad oxide layer may be a thin film including silicon oxide formed, for example, using a thermal oxidation process. The pad oxide layer may serve as an adhesion layer between the uppermost first semiconductor layer 410 (or the second semiconductor layer 420 in some other embodiments) and the pad nitride layer located thereover. In some embodiments, the pad nitride layer is formed of silicon nitride, silicon oxynitride, silicon carbonitride, or the like, or a combination thereof. For example, the pad nitride layer may be formed using low-pressure chemical vapor deposition (LPCVD) or plasma enhanced chemical vapor deposition (PECVD).

[0068] The mask layer may be patterned using photolithography techniques. In general, photolithography techniques utilize depositing a photoresist material (not shown), irradiating (exposing) it, and developing it to remove a portion of the photoresist material. The remaining photoresist material protects the underlying material (e.g., the mask layer in this example) from subsequent process steps (e.g., etching). For example, the pad oxide layer and the pad nitride layer are patterned using the photoresist material to form a patterned mask.

[0069] The patterned mask can then be used to pattern the exposed portions of the first and second semiconductor layers 410-420 and the semiconductor substrate 302 to form grooves (or openings) to define the stacked structure 401 between adjacent grooves. When a plurality of stacked structures are formed, the grooves can be disposed between any adjacent stacked structures. In some embodiments, the stacked structure 401 is formed by etching grooves in the first and second semiconductor layers 410-420 and the semiconductor substrate 302 using, for example, reactive ion etching (RIE), neutral beam etching (NBE), similar etching, or a combination thereof. The etching may be anisotropic. In some embodiments, the grooves may be parallel to each other and closely spaced strips from each other (when viewed from above). In some embodiments, the grooves may be continuous and surround the stacked structure 401.

[0070] Corresponds to Figure 2 Operation step 206. Figure 5 A schematic cross-sectional view of a gate-all-around field effect transistor (GAA FET) device 300 including one or more isolation structures 502 is shown at one of various manufacturing stages. Figure 5 The image is taken perpendicular to the length direction of the active / dummy gate structure of the gate-all-around field effect transistor (GAA FET) device 300 (eg, Figure 1 AA in FIG.

[0071] Isolation structure 502 (which may include multiple parts) may be formed between adjacent stacked structures or adjacent to a single stacked structure. Isolation structure 502 (formed of insulating material) may electrically isolate adjacent stacked structures from each other. The insulating material may be an oxide (e.g., silicon oxide), a nitride, the like, or a combination thereof, and may be deposited by high density plasma chemical vapor deposition (HDP-CVD), flowable CVD (FCVD) (e.g., a CVD-based material is deposited in a remote plasma system and post-cured to convert it into another material (e.g., an oxide), the like, or a combination thereof. Other insulating materials and / or other formation processes may also be used. In one example, the insulating material is silicon oxide formed by a flow chemical vapor deposition (FCVD) process. Once the insulating material is formed, an annealing process may be performed. A planarization process (e.g., a chemical mechanical polish (CMP) process) may remove any excess insulating material and form an upper surface of the insulating material and an upper surface of a patterned mask (not shown) defining the stacked structure 401. In different embodiments, the mask may also be removed by the planarization process.

[0072] Next, the insulating material is recessed to form an isolation structure 502 (sometimes referred to as shallow trench isolation (STI)). Figure 5 As shown. The recessed isolation structure 502 causes the stacked structure 401 to protrude from between adjacent portions of the isolation structure 502. The upper surface of the isolation structure (STI) 502 may have a flat surface (as shown), a convex surface, a concave surface (e.g., dished), or a combination thereof. The upper surface of the isolation structure 502 may be formed to be flat, convex, and / or concave by appropriate etching. The isolation structure 502 may be recessed using an acceptable etching process (e.g., an etching process that is selective to the material of the isolation structure 502). For example, dry etching or wet etching using dilute hydrofluoric (DHF) acid may be performed to recess the isolation structure 502.

[0073] Corresponds to Figure 2 Operation step 208. Figure 6 A schematic cross-sectional view of a gate-all-around field effect transistor (GAA FET) device 300 including a dummy gate structure 602 at one of various manufacturing stages is shown. Figure 6 The active / dummy gate structure of the gate-all-around field effect transistor (GAA FET) device 300 is cut perpendicular to the length direction of the active / dummy gate structure (eg, Figure 1 AA in FIG.

[0074] Next, a dummy gate structure 602 is formed above the stacked structure 401 and the isolation structure 502. Generally speaking, the dummy gate structure 602 extends along a lateral direction (e.g., X direction) perpendicular to the length direction of the stacked structure 401. In different embodiments, the dummy gate structure 602 can be formed at the location of a subsequently formed active (e.g., metal) gate structure, i.e., defining the footprint of the active gate structure. The dummy gate structure 602 is placed above a local stacked structure 401. The above-mentioned covering portion of the stacked structure 401 includes a portion of the second semiconductor layer 420 configured together as a conductive channel and a portion of the first semiconductor layer 410 replaced by the active gate structure. In this way, the active gate structure can surround various portions of the second semiconductor layer 420, which will be further described in detail below.

[0075] In some embodiments, the dummy gate structure 602 may include one or more Si-based or SiGe-based materials similar to (or having a similar etching rate to) the first semiconductor layer 410, such as SiGe. The dummy gate structure 602 may be deposited by CVD, PECVD, ALD, FCVD, or a combination thereof. Figure 6 In the illustrated embodiment, the dummy gate structure 602 is shown as being formed as a single entity, however, it should be understood that the dummy gate structure 602 may be formed to have multiple parts, each of which may include different materials.

[0076] Corresponds to Figure 2 Operation step 210. Figure 7 1 is a schematic cross-sectional view of a gate all-around field effect transistor (GAA FET) device 300, wherein at one of the various manufacturing stages, a first portion of the stacked structure 401 not covered by the dummy gate structure 602 is removed by a first etching process 701. The first portion is indicated by a dotted line and is Figure 7 The mark is 401-1. Figure 7 is taken along the length direction of the fin structure of the gate all-around field effect transistor (GAA FET) device 300 (eg, Figure 1 BB in FIG.

[0077] After forming the dummy gate structure 602, a pair of gate spacers 702 may be formed along opposite sidewalls of the dummy gate structure 602. Figure 7As shown. In this way, each gate spacer 702 can also cross the stack structure 401. The gate spacer 702 can include a low-k value dielectric material and can be formed of a suitable dielectric material, such as silicon oxide, silicon oxycarbonitride, or the like. The gate spacer 702 can be formed using any suitable deposition method (such as thermal oxidation, chemical vapor deposition (CVD), or the like).

[0078] Next, during the first etching process 701, the dummy gate structure 602 may be used together with the gate spacer 702 as a mask to etch the non-covered portion of the stack structure 401. The first etching process 701 may have an anisotropic characteristic to directionally (e.g., vertically) etch the stack structure 401. Therefore, the stack structure 401 has corresponding remaining portions of the first and second semiconductor layers 410 and 420 that are alternately stacked with each other. For example, in Figure 7 , the semiconductor layers 710 and 720 (of the stacked structure 401) are the remaining portions of the first and second semiconductor layers 410 and 420 respectively covered by the dummy gate structure 602 (and the gate spacer 702). In some embodiments, the semiconductor layers 710 and 720 may sometimes be referred to as nanostructures (e.g., nanosheets) 710 and 720, respectively.

[0079] In some embodiments, when the first etching process 701 is performed, the stacked structure 401 may have its sidewalls 401A all in a bow shape, such as Figure 7 As shown. The term "arc" used herein may refer to a curve whose middle portion protrudes more than its side portions. With such an arched sidewall, the stacked structure 401 may have at least one of its upper or lower portions extend more in the Y direction than its middle portion. In other words, the uppermost semiconductor layer 720A, the middle semiconductor layer 720B, and the lowermost semiconductor layer 720C may have their own longitudinal lengths, represented as L720A, L720B, and L720C, respectively; the uppermost semiconductor layer 710A, the middle semiconductor layer 710B, and the lowermost semiconductor layer 710C may also have their own longitudinal lengths, represented as L710A, L710B, and L710C, respectively.

[0080] For example, in Figure 7 In the embodiment of the present invention, the bottom semiconductor layer 720C and the top semiconductor layer 720A may each have a longer longitudinal length than the middle semiconductor layer 720B. In other words, the longitudinal length L 720A Approximately equal to (or slightly less than) the longitudinal length L 720C , and the longitudinal length L 720A And longitudinal length L 720C Each of them is greater than the longitudinal length L 720B (L720A≈L720C >L 720B ). Similarly, the bottom semiconductor layer 710C and the top semiconductor layer 710A may each have a longer longitudinal length than the middle semiconductor layer 710B. That is, the longitudinal length L 710A Approximately equal to (or slightly less than) the longitudinal length L 710C , and the longitudinal length L 710A And longitudinal length L 710C Each of them is greater than the longitudinal length L 710B (L710A≈L 710C >L 710B ).

[0081] In some other embodiments, the bottom semiconductor layer 720C is longer than either the top semiconductor layer 720A or the middle semiconductor layer 720B (wherein the top semiconductor layer 720A and the middle semiconductor layer 720B may have substantially the same length); the bottom semiconductor layer 710C is longer than either the top semiconductor layer 710A or the middle semiconductor layer 710B (wherein the top semiconductor layer 710A and the middle semiconductor layer 710B may have substantially the same length). In other words, the longitudinal length L 720A Approximately equal to the longitudinal length L 720B , and the longitudinal length L 720A And longitudinal length L 720B Both are less than the longitudinal length L 720C (L 720A ≈L 720B <L 720C ); and the longitudinal length L 710A Approximately equal to the longitudinal length L 710B , and the longitudinal length L 710A And longitudinal length L 710B Both are less than the longitudinal length L 710C (L 710A ≈L 710B <L 710C ).

[0082] The first etching process 701 may include a plasma process using at least one of the following gases: hydrogen bromide (HBr), chlorine (Cl), or argon (Ar). In a non-limiting example, the first etching process 701 may be performed under the following conditions: a bias power of about 50 W to 3000 W, a pressure of about 2 mTorr to 80 Torr, a process time of about 5 seconds to 300 seconds, a temperature of about 25° C. to 100° C., an HBr gas flow rate of about 10 SCCM / min to 500 SCCM / min, a Cl gas flow rate of about 10 SCCM / min to 500 SCCM / min, and an Ar gas flow rate of about 30 SCCM / min to 300 SCCM / min. However, it should be noted that power supply power, bias power, pressure, and flow rate outside these ranges may also be envisioned.

[0083] Corresponds to Figure 2 Operation step 212, Figure 8 and Fig. 9 Each shows a schematic cross-sectional view of a gate all-around field effect transistor (GAA FET) device 300, wherein at one of the various manufacturing stages, a second portion of the stacked structure 401 is removed by a second etching process 801. The second portion is indicated by a dotted line and is Figure 8 It should be noted that the second part 401-2 is Figure 7 A portion of the stacked structure 401 is shown. Furthermore, the second portion 401-2 is laterally adjacent to the lower portion of the first portion 401-1. Figure 8 and Fig. 9 Each is taken along the length direction of the fin structure of the gate all-around field effect transistor (GAA FET) device 300 (eg, Figure 1 BB in FIG.

[0084] The second etching process 801 may have an isotropic property to etch the stacked structure 401 in multiple directions. Through the above-mentioned omnidirectional etching process, a particularly protruding portion of the stacked structure 401 (e.g., the lowermost semiconductor layers 710C and 720C) may be pushed back laterally or pushed inward. In other words, the lowermost semiconductor layers 710C and 720C may each be trimmed shorter in their longitudinal direction. Therefore, when the second etching process 801 is performed, the stacked structure 401 may have its sidewalls 401A, each of which presents a single-sided arch shape, such as Figure 8 As shown, or in an asymmetrical arch, such as Fig. 9 The term “unilateral arcuate” used herein may refer to a curve whose middle portion protrudes more than one of the side portions; the term “asymmetric arcuate” used herein may refer to a curve whose middle portion protrudes more than one of the side portions and less than the other side portion.

[0085] For example, in Figure 8 In the embodiment of the present invention, the uppermost semiconductor layer 720A may have a longer longitudinal length than the middle semiconductor layer 720B and the lowermost semiconductor layer 720C, wherein the middle semiconductor layer 720B and the lowermost semiconductor layer 720C may have substantially the same length. In other words, the longitudinal length L 720A Greater than the longitudinal length L 720C And longitudinal length L 720B , and the longitudinal length L 720C With longitudinal length L 720B Roughly the same (L 720B ≈L 720C <L 720A ). Similarly, the uppermost semiconductor layer 710A may have a longer longitudinal length than the middle semiconductor layer 710B and the lowermost semiconductor layer 710C, wherein the middle semiconductor layer 710B and the lowermost semiconductor layer 710C may have substantially the same length. That is, the longitudinal length L 710A Greater than the longitudinal length L 710C And longitudinal length L 710B , and the longitudinal length L 710C With longitudinal length L 710B Roughly the same (L 710B ≈L 710C <L 710A ). Therefore, the longitudinal length L 720C With longitudinal length L 720A Or longitudinal length L 720B The difference between 720C -L 720A or L 720C -L 720B ) is equal to or less than 0 nanometers; longitudinal length L 710C With longitudinal length L 710A Or longitudinal length L 710B The difference between 710C -L 710A or L 710C -L 710B ) is equal to or less than 0 nanometers.

[0086] For example, in Fig. 9 In the embodiment of the present invention, the uppermost semiconductor layer 720A may have a longer longitudinal length than the middle semiconductor layer 720B, and the middle semiconductor layer 720B may have a longer longitudinal length than the lowermost semiconductor layer 720C. That is, the longitudinal length L 720A Greater than the longitudinal length L 720B , and the longitudinal length L 720B Greater than the longitudinal length L 720C (L720A >L 720B >L 720C ). Similarly, the uppermost semiconductor layer 710A may have a longer longitudinal length than the middle semiconductor layer 710B, and the middle semiconductor layer 710B may have a longer longitudinal length than the lowermost semiconductor layer 710C. That is, the longitudinal length L 710A Greater than the longitudinal length L 710B , and the longitudinal length L 710B Greater than the longitudinal length L 710C (L 710A >L 710B >L 710C ). Therefore, the longitudinal length L 720C With longitudinal length L 720A Or longitudinal length L 720B The difference between 720C -L 720A or L 720C -L 720B ) is equal to or less than 0 nanometers; longitudinal length L 710C With longitudinal length L 710A Or longitudinal length L 710B The difference between 710C -L 710A or L 710C -L 710B ) is equal to or less than 0 nanometers.

[0087] The second etching process 801 may include a plasma process using at least one of the following gases: hydrogen (H2), fluorine-based gas or nitrogen (N2). The fluorine-based gas is selected from: difluoromethane (CH2F2), fluoromethane (CH3F), trifluoromethane (CHF3), tetrafluoromethane (CF4), sulfur hexafluoride (SF6), nitrogen trifluoride (NF3), octafluorocyclobutane (C4F8), hexafluorobutadiene (C4F6) and combinations thereof. The second etching process 801 may also include the following gases: methane (CH4) and argon (Ar). In a non-limiting example, the second etching process 801 may be performed under the following conditions: a bias power of about 30 W to 1000 W, a pressure of about 2 mTorr to 80 Torr, a process time of about 3 seconds to 150 seconds, a temperature of about 25° C. to 100° C., a H2 gas flow rate of about 50 SCCM / min to 500 SCCM / min, a CH4 gas flow rate of about 5 SCCM / min to 200 SCCM / min, a fluorine-based gas gas flow rate of about 5 SCCM / min to 200 SCCM / min, an Ar gas flow rate of about 20 SCCM / min to 300 SCCM / min, and a N2 gas flow rate of about 5 SCCM / min to 200 SCCM / min. However, it should be noted that source powers, bias powers, pressures, and flows outside these ranges may also be contemplated.

[0088] Although two etching processes (e.g., first and second etching processes 701 and 801) are shown, it should be understood that more etching processes may be performed to etch the stack structure 401. For example, after the first etching process 701 and the second etching process 801, a third etching process similar to the first etching process and a fourth etching process similar to the second etching process 801 may be performed. In another example, after the first etching process 701 and the second etching process 801, one or more etching processes may be performed, each etching process being similar to the second etching process 801.

[0089] Corresponds to Figure 2 Step 21, Fig.10 and Fig.11 Each of the figures shows a cross-sectional view of a gate-all-around field effect transistor (GAA FET) device 300 including a plurality of inner spacer layers 1002 at one of the various manufacturing stages. Fig.10 and Fig.11 Sequential Figure 8 and Fig. 9 Schematic diagram of the cross section afterwards. Fig.10 and Fig.11 Each is taken along the length direction of the fin structure of the gate all-around field effect transistor (GAA FET) device 300 (eg, Figure 1 BB in FIG.

[0090] To form the inner spacer layer 1002, the corresponding end of each nanostructure 710 is removed. The end of the nanostructure 710 can be removed (e.g., etched) by pulling the nanostructure 710 back to a pull-back distance using a "pull-back" process. 710A , L 710B and L 710C Each of the above may be reduced due to the pull-back distance. In an example where the semiconductor layer 720 includes Si and the semiconductor layer 710 includes SiGe, the pull-back process may include an isotropic etching process with hydrogen chloride (HCl) gas, which etches SiGe without etching Si. Therefore, the Si layer (nanostructure; semiconductor layer 720) may remain intact during this process. Therefore, multiple pairs of grooves may be formed. These grooves are then filled with a dielectric material to form an inner spacer layer 1002. As shown in FIG. Figure 10-11 As shown, each pair of inner spacer layers 1002 is formed along corresponding etched ends of the nanostructure 710 .

[0091] In some embodiments, the inner spacer layer 1002 may be conformally formed by chemical vapor deposition (CVD) or by monolayer doping (MLD) of nitride followed by spacer RIE. The inner spacer layer 1002 may be deposited using, for example, a conformal deposition process followed by an isotropic or anisotropic etch back to remove excess spacer material on the sidewalls of the stacked structure 401 and on the surface of the semiconductor substrate 302. The inner spacer layer 1002 may be made of silicon nitride, silicon boron carbide nitride, silicon carbide nitride, silicon oxycarbon nitride, or any other type of dielectric material suitable for forming an insulating gate sidewall spacer of a transistor (e.g., a dielectric material having a dielectric constant k less than about 5).

[0092] Corresponds to Figure 2 Operation step 216, Fig.12 and Fig.13 Each of the figures shows a cross-sectional view of a gate-all-around field effect transistor (GAA FET) device 300 including a pair of epitaxial structures 1202 at one of various manufacturing stages. Fig.12 and Fig.13 To continue Fig.10 and Fig.11 Schematic diagram of the cross section afterwards. Fig.12 and Fig.13 are each taken along the length direction of the fin structure of the gate all-around field effect transistor (GAAFET) device 300 (eg, Figure 1 BB in FIG.

[0093] The epitaxial structure 1202 may be formed to contact the corresponding ends (along the Y direction) of each nanostructure 720. Furthermore, the epitaxial structure 1202 is separated (or otherwise isolated) from the corresponding ends (along the Y direction) of the nanostructure 710 having the inner spacer layer 1002. The epitaxial structures 1202 may each have a plurality of film layers disposed on top of each other. In some embodiments, the doping concentration of the epitaxial structure 1202 may have a gradient from bottom to top. For example, the lower layer of the epitaxial structure 1202 may have a lower doping concentration, while the upper layer of the epitaxial structure 1202 may have a higher doping concentration. According to various embodiments of the present disclosure, the nanostructures 720 may together serve as a channel structure of a gate-all-wrap field effect transistor (GAA FET) device 300, and the epitaxial structure 1202 may serve as a drain structure and a source structure of the gate-all-wrap field effect transistor (GAA FET) device 300, respectively.

[0094] The epitaxial structures 1202 may each include silicon germanium (SiGe), indium arsenide (InAs), indium gallium arsenide (InGaAs), indium antimonide (InSb), germanium arsenide (GaAs), germanium antimonide (GaSb), indium aluminum phosphide (InAlP), indium phosphide (InP), any other suitable material or combination thereof. The epitaxial structures 1202 may be formed on the exposed ends of each nanostructure 720 using one or more epitaxial layer growth processes. For example, the growth process may include a selective epitaxial growth (SEG) process, a CVD deposition technique (e.g., vapor-phase epitaxy (VPE) and / or ultra-high vacuum CVD (UHV-CVD)), molecular beam epitaxy, or other suitable epitaxial processes. In-situ doping (ISD) may be applied to form the doped epitaxial structures 1202 to produce the junction of the gate all-around field effect transistor (GAA FET) device 300. For example, when the gate-all-around field effect transistor (GAAFET) device 300 is configured as n-type, the epitaxial structure 1202 can be doped by implanting n-type dopants (e.g., arsenic (As), phosphorus (P), etc.). When the gate-all-around field effect transistor (GAAFET) device 300 is configured as p-type, the epitaxial structure 1202 can be doped by implanting p-type dopants (e.g., boron (B), etc.).

[0095] Corresponds to Figure 2 Operation step 218, Fig.14 and Fig.15Each shows a schematic cross-sectional view of a gate-all-around field effect transistor (GAA FET) device 300 including an active (eg, metal) gate structure 1402 at one of various stages of fabrication. Fig.14 and Fig.15 To continue Fig.12 and Fig.13 Schematic diagram of the cross section afterwards. Fig.14 and Fig.15 are each taken along the length direction of the fin structure of the gate-all-around field effect transistor (GAA FET) device 300 (eg, Figure 1 BB in FIG.

[0096] After forming the epitaxial structure 1202, the dummy gate structure 602 and the nanostructure 710 may be removed together or separately. Figure 12-13 ) to form a gate trench. In some embodiments, the dummy gate structure 602 and / or the nanostructure 710 can be removed by applying a selective etch (e.g., hydrochloric acid (HCl)) while leaving the nanostructure 720, the gate spacer 702, and the inner spacer layer 1002 substantially intact. In one example, after removing the dummy gate structure 602, a portion of the gate trench (which exposes the corresponding sidewall of each nanostructure 720 facing the X direction) can be formed. After removing the nanostructure 710 to further extend the gate trench, the corresponding lower surface and / or upper surface of each nanostructure 720 can be exposed. Therefore, the entire periphery of each nanostructure 720 can be exposed.

[0097] Next, an active gate structure 1402 is formed to surround each nanostructure 720 (which together serves as a channel structure of the gate all-around field effect transistor (GAAFET) device 300). In some embodiments, the active gate structure 1402 includes a gate dielectric layer and a gate metal. The gate dielectric layer can surround each nanostructure 720, for example, the upper and lower surfaces and the sidewalls. The gate dielectric layer can be formed of different high-k dielectric materials or similar high-k dielectric materials. Exemplary high-k dielectric materials include metal oxides or silicates of Hf, Al, Zr, La, Mg, Ba, Ti, Pb and combinations thereof. The gate dielectric may include a stack of multiple high-k dielectric materials. The gate dielectric layer may be deposited using any suitable method, including, for example, molecular beam deposition (MBD), atomic layer deposition (ALD), PECVD or the like. In some embodiments, the gate dielectric layer may selectively include a substantially thin oxide (e.g., SiO x ) layer, which may be a native oxide layer formed on the surface of each nanostructure 720.

[0098] The gate metal may include a stack of multiple metal materials. For example, the gate metal may be a p-type work function layer, an n-type work function layer, multiple layers thereof, or a combination thereof. The work function layer may also be referred to as a work function metal. Exemplary p-type work function metals may include TiN, TaN, Ru, Mo, Al, WN, ZrSi2, MoSi2, TaSi2, NiSi2, WN, other suitable p-type work function materials, or a combination thereof. Example n-type work function metals may include Ti, Ag, TaAl, TaAlC, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, other suitable n-type work function materials, or a combination thereof. The work function value is related to the material composition of the work function layer, and therefore, the material of the work function layer is selected to adjust its work function value so that the target threshold voltage V is achieved in the device to be manufactured. t The work function layer may be deposited by CVD, physical vapor deposition (PVD), ALD, and / or other suitable processes.

[0099] Since the active gate structure 1402 substantially fills the gate trench (partially formed by removing the nanostructures 710), the active gate structure 1402 may have a number of sections corresponding to the number of nanostructures 710. Fig.14 and Fig.15 , active gate structure 1402 includes regions 1402A, 1402B, and 1402C. Regions 1402A and 1402B may together surround nanostructure 720B, and regions 1402B and 1402C may together surround nanostructure 720C. Furthermore, regions 1402A, 1402B, and 1402C may inherit the size and cross-sectional profile of nanostructures 710A, 710B, and 710C (e.g., Nos. 10-11), respectively. Thus, regions 1402B and 1402C may have similar lengths (L 710B or L 710C ), which is longer than the length of section 1402A (L 710A )short( Fig.14 ); the length of the area 1402C (L 710C ) is greater than the length (L) of the section 1402B 710B ) is short, and the length of the section 1402B (L 710B ) is greater than the length (L) of the section 1402A. 710A )short( Fig.15 ).

[0100] Fig.161 shows a schematic cross-sectional view of a gate all-around field effect transistor (GAAFET) device 300 according to another embodiment of the present disclosure. As shown, nanostructures 720A, 720B, and 720C (together with the protruding portion of substrate 302) each have a length (in the X direction) that is shorter than the corresponding (adjacent) portion of active gate structure 1402 together with the corresponding inner spacer layer 1002. The stacked structure 401 having these shorter nanostructures 720A-720C can sometimes be referred to as having a kink profile. In some embodiments, such shorter nanostructures 720A-720C can be formed during the second etching process 801 ( Figure 8-Figure 9 ) period.

[0101] Fig.17 , Fig.18 and Fig.19 Each of them is a cross-sectional schematic diagram of a gate-all-around field effect transistor (GAAFET) device 300 according to yet another embodiment of the present disclosure. Figure 17-Figure 19 The gate all-around field effect transistor (GAA FET) device 300 is shown to have a twisted cross-sectional profile along the sidewalls of the stack structure 401. However, it should be noted that Figure 17-Figure 19 Embodiments of the cross-sectional schematic diagram do not have the above-mentioned distorted cross-sectional profile while still being within the scope of the present disclosure. Fig.17 In FIG. 1 , a dielectric layer 1702 is disposed below the epitaxial structure 1202. Fig.18 In the embodiment, the dielectric layer 1802 is disposed below the lowermost region of the active gate structure 1402. Fig.19 As shown, dielectric layer 1902 is disposed below active gate structure 1402 and a lowermost portion of epitaxial structure 1202. In some embodiments, each of dielectric layers 1702 to 1902 may have a material selected from the group consisting of SiN, SiO2, SiON, SiCN, SiCON, SiCO, HfO, AlO, and combinations thereof.

[0102] In one aspect of the present disclosure, a method for manufacturing a semiconductor device is provided. The method includes: forming a stack extending along a first lateral direction on a substrate, wherein the stack includes a plurality of first semiconductor layers and a plurality of second semiconductor layers arranged alternately with each other; covering a first portion of the stack with a first gate structure, wherein the first gate structure extends along a second lateral direction perpendicular to the first lateral direction; removing a second portion of the stack by a first etching process, wherein the second portion is arranged beside the first portion along the first lateral direction; and removing a third portion of the stack by a second etching process, wherein the third portion is arranged beside the lower portion of the second portion.

[0103] In some embodiments, the first etching process includes an anisotropic etching process, and the second etching process includes an isotropic etching process. Furthermore, in some embodiments, the first etching process has a first plasma process with a first bias power, and the second etching process has a second plasma process with a second bias power, and wherein the first bias power is substantially higher than the second bias power. Furthermore, in some embodiments, the first etching process has a first plasma process using at least one of the following gases: hydrogen bromide (HBr), chlorine (Cl) or argon (Ar), and the second etching process has a second plasma process using at least one of the following gases: hydrogen (H2), fluorine-based gas or nitrogen (N2). In addition, in some embodiments, the fluorine-based gas is selected from the group consisting of difluoromethane (CH2F2), fluoromethane (CH3F), trifluoromethane (CHF3), tetrafluoromethane (CF4), sulfur hexafluoride (SF6), nitrogen trifluoride (NF3), octafluorocyclobutane (C4F8), hexafluorobutadiene (C4F6) and combinations thereof. In some embodiments, after the step of removing the third portion of the stack by the second etching process, the method further includes: replacing multiple ends of each first semiconductor layer with a pair of inner spacer layers; and epitaxially growing a source / drain structure from a remaining portion of the stack, wherein the source / drain structure contacts an end of each second semiconductor layer. Furthermore, in some embodiments, the method further includes: replacing the first semiconductor layer and the first gate structure with a second gate structure. Wherein, the second gate structure includes at least a high-k dielectric layer and a metal gate. Furthermore, in some embodiments, one of the lowermost layers in the second semiconductor layer has a first length along the first lateral direction, and one of the upper lowermost layers in the second semiconductor layer has a second length along the first lateral direction, and wherein the first length is equal to the second length. Alternatively, in some embodiments, one of the lowermost layers in the second semiconductor layer has a first length along the first lateral direction, and one of the upper lowermost layers in the second semiconductor layer has a second length along the first lateral direction, and wherein the first length is less than the second length. In addition, in some embodiments, the pair of inner spacer layers extend farther along the first lateral direction than at least one of the second semiconductor layers adjacent thereto.

[0104] In another aspect of the present disclosure, a method for manufacturing a semiconductor device is provided. The method includes: alternately growing a plurality of first semiconductor layers and a plurality of second semiconductor layers into a stack above a substrate; covering the stack with a dummy gate structure; removing a portion of the stack that is not covered by the dummy gate structure; and trimming a lower portion of a remaining portion of the stack.

[0105] In some embodiments, the step of removing a portion of the stack comprises an anisotropic etching process, and the step of trimming a lower portion of the remaining portion of the stack comprises an isotropic etching process. Furthermore, in some embodiments, the first etching process has a first plasma process with a first bias power, and the second etching process has a second plasma process with a second bias power, and wherein the first bias power is substantially higher than the second bias power. Furthermore, in some embodiments, the first etching process has a first plasma process using at least one of the following gases: hydrogen bromide (HBr), chlorine (Cl), or argon (Ar), and the second etching process has a second plasma process using at least one of the following gases: hydrogen (H2), a fluorine-based gas, or nitrogen (N2). In addition, in some embodiments, the fluorine-based gas is selected from the group consisting of difluoromethane (CH2F2), fluoromethane (CH3F), trifluoromethane (CHF3), tetrafluoromethane (CF4), sulfur hexafluoride (SF6), nitrogen trifluoride (NF3), octafluorocyclobutane (C4F8), hexafluorobutadiene (C4F6), and combinations thereof. In some embodiments, after the step of trimming the lower portion of the remaining portion of the stack, one of the lowermost layers in the second semiconductor layers has a first length along its longitudinal direction, and one of the upper lowermost layers in the second semiconductor layers has a second length along its longitudinal direction, and wherein the first length is equal to the second length. Alternatively, in some embodiments, after the step of trimming the lower portion of the remaining portion of the stack, one of the lowermost layers in the second semiconductor layers has a first length along its longitudinal direction, and one of the upper lowermost layers in the second semiconductor layers has a second length along its longitudinal direction, and wherein the first length is less than the second length. Furthermore, in some embodiments, after the step of trimming the lower portion of the remaining stack, it also includes: epitaxially growing a source / drain structure from an end portion of each second semiconductor layer; wherein the lower portion of the source / drain structure has a first doping concentration, and the upper portion of the source / drain structure has a second doping concentration higher than the first doping concentration.

[0106] In another aspect of the present disclosure, a semiconductor device is provided. The semiconductor device includes: a plurality of semiconductor layers spaced vertically apart from each other, wherein each semiconductor layer extends along a first lateral direction; a metal gate structure extending along a second lateral direction and including a plurality of sections, wherein each of the semiconductor layers is surrounded by adjacent sections of the sections; a plurality of pairs of inner spacer layers, each pair of inner spacer layers being respectively disposed beside an end of a corresponding section of the sections; a pair of source / drain structures respectively contacting a plurality of ends of each of the semiconductor layers, wherein the sections are electrically isolated from the pair of source / drain structures by the pair of inner spacer layers; wherein, along the first lateral direction, the semiconductor layer located below is shorter than the semiconductor layer located above.

[0107] In some embodiments, each of the source / drain structure pairs has a plurality of doping concentrations, wherein a higher doping concentration is formed above a lower doping concentration.

[0108] As used herein, the terms "about" and "approximately" generally mean plus or minus 10% of the stated value. For example, about 0.5 would include 0.45 and 0.55, about 10 would include 9 to 11, and about 1000 would include 900 to 1100.

[0109] The above briefly describes the characteristic components of several embodiments of the utility model, so that those skilled in the art can more easily understand the types of the present disclosure. Any person skilled in the art should understand that the present disclosure can be easily used as a basis for the change or design of other processes or structures to achieve the same purpose and / or obtain the same advantages as the embodiments described herein. Any person skilled in the art can also understand that structures equivalent to the above do not depart from the spirit and scope of protection of the present disclosure, and can be changed, replaced and modified without departing from the spirit and scope of the present disclosure.

Claims

1. A semiconductor device, characterized in that: include: A plurality of semiconductor layers are vertically spaced apart from each other, wherein each of the plurality of semiconductor layers extends along a first lateral direction; a metal gate structure extending along a second lateral direction and comprising a plurality of sections, wherein each of the plurality of semiconductor layers is surrounded by adjacent sections of the plurality of sections; a plurality of inner spacer layer pairs, each of the plurality of inner spacer layer pairs being disposed beside an end of a corresponding section among the plurality of sections; and a source / drain structure pair, respectively contacting a plurality of end portions of each of the plurality of semiconductor layers, wherein the plurality of regions are electrically isolated from the source / drain structure pair by a plurality of the inner spacer layer pairs; Along the first lateral direction, the semiconductor layer located below among the plurality of semiconductor layers is shorter than the semiconductor layer located above.

2. The semiconductor device according to claim 1, wherein Wherein along the first transverse direction, the lower section among the plurality of sections is shorter than the upper section.

3. The semiconductor device according to claim 1 or 2, wherein: The invention also comprises a dielectric layer pair formed under the source / drain structure pair.

4. The semiconductor device according to claim 3, wherein: The dielectric layer pair is separated from a lower surface of a lowermost region among the plurality of regions.

5. The semiconductor device according to claim 1 or 2, wherein: Also included is a dielectric layer formed directly below the metal gate structure.

6. The semiconductor device according to claim 5, wherein: The dielectric layer is in contact with a lower surface of a lowermost region among the plurality of regions and the source / drain structure pair.

7. The semiconductor device according to claim 5, wherein: The dielectric layer further extends below the source / drain structure pair.

8. The semiconductor device according to claim 7, wherein: The dielectric layer pair is in contact with a lower surface of a lowermost region among the plurality of regions and a lower surface of the source / drain structure pair.

9. The semiconductor device according to claim 1 or 2, wherein: Along the first lateral direction, the semiconductor layer located at the top of the plurality of semiconductor layers has a first length, and the region located at the top of the plurality of regions has a second length smaller than the first length.

10. The semiconductor device according to claim 1 or 2, wherein: Along the first lateral direction, the semiconductor layer located at the bottom among the plurality of semiconductor layers has a first length, and the region located at the bottom among the plurality of regions has a second length that is smaller than the first length.

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