Display substrate and display panel

Abstract

The utility model provides a display substrate and a display panel, belongs to the technical field of display, and can solve the problems that an existing display product is low in yield, poor in display and the like. The display substrate disclosed by the utility model comprises a dielectric substrate, wherein a conductive device is integrated in the dielectric substrate; the planarization layer is arranged on the dielectric substrate, and the side, away from the dielectric substrate, of the planarization layer is a flat surface; a first electrode layer including first electrodes of the plurality of light emitting devices; the charge generation layer includes charge generation units of a plurality of light emitting devices; the display substrate further comprises a first partition opening penetrating through at least part of thickness of the planarization layer, and the first partition opening meets the requirement that the charge generation layer is disconnected to form the charge generation unit. Normal preparation of the first electrode can be ensured, and the yield of the display substrate is improved.

Description

Technical Field

[0001] The present disclosure belongs to the field of display technology, and particularly relates to a display substrate and a display panel. Background Art

[0002] In recent years, organic light-emitting diode (OLED) microdisplays have been widely used in virtual reality (VR) or augmented reality (AR) as near-eye displays. During the production and transportation of OLED dielectric substrates, foreign matter is easily accumulated on their upper surfaces. However, the existing product structure and process routes of display factories limit the treatment of dielectric substrates to cleaning, plasma gas treatment or etching. Usually, stubborn foreign matter on the dielectric substrate cannot be completely removed, resulting in poor display after OLED display-related processes, such as line dots, cross-color white dots and other abnormalities. In addition, the cutting path difference of most dielectric substrates is large, and the process is affected by the spin coating of the dielectric substrate, which is prone to diagonal Mura, resulting in yield loss and waste of production capacity of display products. Utility Model Content

[0003] The utility model aims to solve at least one of the technical problems existing in the prior art, and provides a display substrate and a preparation method thereof, and a display panel for shielding the first electrode abnormality of a light-emitting device, improving the yield of display products, and improving the display effect.

[0004] In the first aspect, the technical solution adopted to solve the technical problem of the utility model is a display substrate, comprising:

[0005] A dielectric substrate having a conductive device integrated therein;

[0006] A planarization layer is arranged on the dielectric substrate, and a side of the planarization layer facing away from the dielectric substrate is a flat surface;

[0007] A first electrode layer, arranged on a side of the planarization layer away from the dielectric substrate, the first electrode layer comprising first electrodes of a plurality of light-emitting devices;

[0008] A charge generation layer is arranged on a side of the first electrode layer away from the dielectric substrate, and the charge generation layer includes a plurality of charge generation units of light-emitting devices; wherein,

[0009] The display substrate further comprises:

[0010] A first isolation opening penetrating through at least a portion of the thickness of the planarization layer, wherein the first isolation opening is sufficient to disconnect the charge generation layer to form the charge generation unit;

[0011] The first partition opening includes a first sub-partition opening and a second sub-partition opening which are sequentially arranged in a direction away from the dielectric substrate, and an orthographic projection of the second sub-partition opening on the dielectric substrate is located within an orthographic projection of the first sub-partition opening on the dielectric substrate.

[0012] In some embodiments, the display substrate further includes a pixel defining layer, which is disposed on a side of the first electrode layer close to the charge generating layer, the pixel defining layer having a pixel opening and a second isolating opening extending through the thickness thereof, the pixel opening being disposed corresponding to the first electrode of the light emitting device, and the second isolating opening being disposed corresponding to the first isolating opening; wherein,

[0013] The second partition opening includes a third sub-partition opening and a fourth sub-partition opening which are sequentially arranged away from the dielectric substrate, and the orthographic projection of the fourth sub-partition opening on the dielectric substrate is located within the orthographic projection of the third sub-partition opening on the dielectric substrate.

[0014] In some embodiments, the orthographic projection of the second isolation opening on the dielectric substrate covers the orthographic projection of the first isolation opening on the dielectric substrate, and the first isolation opening and the second isolation opening together enable the pixel defining layer and the planarization layer to form a first height buffer structure;

[0015] The display substrate further includes a second electrode layer, which is arranged on a side of the charge generating layer away from the dielectric substrate; the first height buffer structure satisfies the requirement that the second electrode layer is formed on a side of the charge generating layer away from the dielectric substrate, so that the second electrode layer is disconnected from the first electrode layer through the charge generating layer; wherein,

[0016] The orthographic projection of the fourth sub-partition opening on the dielectric substrate covers the orthographic projection of the second sub-partition opening on the dielectric substrate.

[0017] In some embodiments, the pixel defining layer includes a first pixel defining layer, a second pixel defining layer, and a third pixel defining layer which are sequentially stacked in a direction away from the dielectric substrate.

[0018] The second partition opening further includes a fifth sub-partition opening, the fifth sub-partition opening penetrates the first pixel defining layer, the third sub-partition opening penetrates the second pixel defining layer, and the fourth sub-partition opening penetrates the third pixel defining layer;

[0019] The orthographic projection of the fifth sub-partition opening on the dielectric substrate coincides with the orthographic projection of the fourth sub-partition opening on the dielectric substrate.

[0020] In some embodiments, the planarization layer includes a first planarization layer and a second planarization layer stacked in sequence in a direction away from the dielectric substrate, and the first isolation opening only passes through the second planarization layer;

[0021] The display substrate further includes a first opening penetrating through the second planarization layer, and the first electrode of the light emitting device is located in the first opening, wherein:

[0022] The thickness of the first electrode of the light emitting device is h1, the depth of the first opening along the thickness direction of the second planarization layer is h2, and h1≥h2.

[0023] In some embodiments, the planarization layer includes a first planarization layer and a second planarization layer stacked in sequence in a direction away from the dielectric substrate, and the first isolation opening penetrates the first planarization layer and the second planarization layer;

[0024] The display substrate further comprises a height compensation layer, which is arranged on a side of the second planarization layer close to the charge generation layer, the height compensation layer comprises a plurality of height compensation structures, and one of the height compensation structures is arranged between the first electrodes of any two adjacent light-emitting devices; the height compensation structure has a second opening that penetrates through the thickness thereof, the second opening is arranged in one-to-one correspondence with the first isolation opening, and the orthographic projection of one of the second openings on the dielectric substrate covers the orthographic projection of one of the first isolation openings on the dielectric substrate; wherein,

[0025] The first isolation opening and the second opening enable the planarization layer and the height compensation structure to form a second height buffer structure;

[0026] The display substrate also includes a second electrode layer, which is arranged on a side of the charge generating layer away from the dielectric substrate; the second height buffer structure satisfies the requirement that the second electrode layer is formed on a side of the charge generating layer away from the dielectric substrate, so that the second electrode layer is disconnected from the first electrode layer through the charge generating layer.

[0027] In some embodiments, the display substrate is divided into a display area and a non-display area surrounding the display area.

[0028] The dielectric substrate includes a cutting path opening that penetrates a portion of its thickness, and the cutting path opening is located in the non-display area;

[0029] The planarization layer covers the cutting path opening, the maximum thickness of the planarization layer is h3, the depth of the cutting path opening along the thickness direction of the dielectric substrate is h4, and h3>h4.

[0030] In some embodiments, the dielectric substrate is made of silicon-based material.

[0031] In a second aspect, an embodiment of the present disclosure further provides a display panel, comprising a display substrate as described in any one of the above-mentioned first aspects. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 A plan view of a display substrate provided by the present disclosure;

[0033] Figure 2 It is a schematic diagram of a display substrate in the prior art;

[0034] Figure 3-Figure 4 Schematic diagrams of two display substrates provided in embodiments of the present disclosure;

[0035] Figure 5a-5e They are Figure 3 A schematic diagram of an intermediate product formed in a method for preparing a display substrate;

[0036] Figure 6a-6f They are Figure 4 Schematic diagram of an intermediate product formed in a method for preparing a display substrate. DETAILED DESCRIPTION

[0037] In order to enable those skilled in the art to better understand the technical solution of the present invention, the present invention is further described in detail below in conjunction with the accompanying drawings and specific implementation methods.

[0038] Unless otherwise defined, the technical terms or scientific terms used in the present disclosure should be understood by people with ordinary skills in the field to which the present disclosure belongs. The "first", "second" and similar words used in the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, similar words such as "one", "one" or "the" do not indicate quantity restrictions, but indicate that there is at least one. Similar words such as "include" or "comprise" mean that the elements or objects appearing before the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Similar words such as "connect" or "connected" are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0039] Figure 1 A plan view of a display substrate provided by the present disclosure, such as Figure 1 As shown, the display substrate 10 may include a display area 10 a and a non-display area 10 c surrounding the display area 10 a .

[0040] Figure 2 is a schematic diagram of a display substrate in the prior art, such as Figure 2 As shown, the display substrate includes: a dielectric substrate 101; a plurality of first electrodes 121 of light-emitting devices arranged on the dielectric substrate 101; a height compensation layer 180, including a plurality of height compensation structures, the height compensation structure being located between any two adjacent first electrodes 121; a pixel defining layer 140, arranged on a side of a layer where the first electrodes 121 are located away from the dielectric substrate 101, including a plurality of pixel openings and a separation opening, and the pixel openings are arranged in a one-to-one correspondence with the first electrodes 121, and a separation opening is arranged between any two adjacent first electrodes 121 of the light-emitting devices; a charge generation layer 150, arranged on a side of a layer where the first electrodes 121 are located away from the dielectric substrate 101, and the charge generation layer 150 includes charge generation units of a plurality of light-emitting devices.

[0041] Among them, in the display substrate of the prior art, firstly, due to the conductive device integrated in the dielectric substrate 101, or the presence of foreign matter in the incoming material of the dielectric substrate 101, the surface of the dielectric substrate 101 close to the first electrode 121 (for example Figure 2 There is a protrusion TP or other defects at A of the dielectric substrate 101, which may cause foreign matter in the first electrode 121 of the light-emitting device when the first electrode 121 of the first electrode layer is prepared later, resulting in abnormalities of the first electrode 121; at the same time, in the subsequent process preparation process, the TP may also cause deformation of the display substrate, resulting in poor display of the display substrate (such as line dots, cross-color white dots, etc.). Secondly, the portion of the dielectric substrate 101 located in the non-display area 10c has a cutting path opening 3 that partially penetrates the dielectric substrate 101. Since the depth of the cutting path opening is too large, the step difference is too large. During the process of displaying the substrate, it is easy to be affected by the spin coating of the dielectric substrate 101. Figure 2 The appearance of diagonal Mura at B will also cause yield loss and waste of production capacity of the display substrate. Thirdly, the separation between the charge generating units in the prior art is generally completed by using the common separation opening of the pixel defining layer 140, and the common separation opening structure requires a large step difference to separate the charge generating layer 150 and form a charge generating unit. However, if the step difference of the opening structure is too large, when the second electrode layer 160 is subsequently prepared on the side of the charge generating layer 150 away from the dielectric substrate 101, Figure 2 At C in the figure, the second electrode of the light-emitting device is prone to piercing the charge generation layer 150, causing leakage and resulting in defects.

[0042] In order to solve at least one problem existing in the above-mentioned existing display substrates, in a first aspect, an embodiment of the present disclosure provides a new display substrate.

[0043] Figure 3-Figure 4 They are schematic diagrams of two display substrates provided in the embodiments of the present disclosure, such as Figure 3 and Figure 4 As shown, the display substrate includes: a dielectric substrate 101, wherein the dielectric substrate 101 is integrated with a conductive device; a planarization layer 116, which is arranged on the dielectric substrate 101, and the side of the planarization layer 116 facing away from the dielectric substrate 101 is a flat surface; a first electrode layer, which is arranged on the dielectric substrate 101, and the first electrode layer includes a first electrode 121 of a plurality of light-emitting devices; a charge generation layer 150, which is arranged on a side of the first electrode layer facing away from the dielectric substrate 101, and the charge generation layer 150 includes a charge generation unit of a plurality of light-emitting devices.

[0044] Among them, the display substrate also includes a first isolation opening 1 that penetrates at least part of the thickness of the planarization layer 116, and the first isolation opening 1 is sufficient to disconnect the charge generation layer 150 to form a charge generation unit; the first isolation opening 1 includes a first sub-isolation opening and a second sub-isolation opening that are arranged in sequence along a direction away from the dielectric substrate 101, and the orthographic projection of the second sub-isolation opening on the dielectric substrate 101 is located within the orthographic projection of the first sub-isolation opening on the dielectric substrate 101.

[0045] Optionally, the material of the dielectric substrate 101 may be a silicon-based material. The silicon-based semiconductor process is mature, highly integrated, and can achieve ultra-high pixel per inch (PPI) display, and is widely used in the field of virtual reality (VR) / augmented reality (AR). In addition, foreign matter is easily accumulated on the upper surface of the silicon-based substrate during production and transportation, which may cause the first electrode 121 of the light-emitting device to be abnormal, thereby affecting the yield of the display product.

[0046] The planarization layer 116 is usually made of organic materials, such as photoresist, acrylic polymer, silicon polymer, etc. The display substrate provided by the embodiment of the present disclosure can cover and fill the concave and convex surface of the dielectric substrate 101 caused by defects such as integrated conductive devices or foreign matter in the dielectric substrate 101 in advance by arranging the planarization layer 116 on the dielectric substrate 101, so that there is no deformation caused by the protrusion TP in the subsequent preparation process of the display substrate, thereby improving the display effect of the display substrate.

[0047] The first electrode layer can be a single-layer structure or a multi-layer structure. Figure 3 and Figure 4 As shown, the first electrode layer includes a four-layer structure of titanium / aluminum / titanium / indium tin oxide (Ti / Al / Ti / ITO) stacked in sequence along the dielectric substrate 101. Optionally, the first electrode 121 can be an anode of the light-emitting device.

[0048] In addition, a charge generating unit is correspondingly arranged on the side of the first electrode 121 of each light-emitting device facing away from the dielectric substrate 101, and the charge generating units of two adjacent light-emitting devices should be disconnected, otherwise, cross-color will occur between the two adjacent light-emitting devices, affecting the display effect. The display substrate in the embodiment of the present disclosure is provided with a first partition opening 1, wherein the first sub-partition opening in the first partition opening 1 is larger than the second sub-partition opening, that is, the first partition opening 1 is an undercut structure. In this way, in the process of preparing the charge generating layer 150, due to the obstruction above the first sub-partition opening, the material of the charge generating layer 150 will appear discontinuous below and above the material in the first partition opening 1, thereby realizing the isolation of the charge generating layer 150 and finally forming a disconnected charge generating unit. The first partition opening 1 in the embodiment of the present disclosure is different from the ordinary partition opening structure (such as Figure 2 Compared with the isolation opening shown in the figure, the charge generating layer 150 can be isolated without setting a too large step difference to form a disconnected charge generating unit. Furthermore, the first isolation opening 1 provided in the embodiment of the present disclosure can also prevent the second electrode layer from piercing the charge generating layer 150 and causing leakage when the second electrode layer is subsequently prepared on the charge generating layer 150.

[0049] It can be understood that in the display substrate provided in the embodiment of the present disclosure, the planarization layer 116 is a multi-layer structure. With such a configuration, in the process of preparing the display substrate, a first isolating opening 1 of an undercut structure can be formed on the multi-layer structure in the planarization layer 116 according to the different etching rates of the multi-layer structure in the planarization layer 116, and the charge generation layer 150 can be isolated to form a charge generation unit. In addition, the first isolating opening 1 that passes through at least part of the thickness of the planarization layer 116 can include only one undercut structure, or it can include multiple undercut structures according to the number of layers of the multi-layer structure in the planarization layer 116. For example, if the planarization layer 116 is a four-layer structure, the first layer and the second layer along the direction away from the dielectric substrate 101 can form an undercut structure, and the third layer and the fourth layer can form another undercut structure, which is not limited in the present disclosure.

[0050] In some embodiments, the display substrate includes not only a dielectric substrate 101, a planarization layer 116, a first electrode layer, and a charge generation layer 150, but also a pixel defining layer 140, which is disposed on a side of the first electrode layer close to the charge generation layer 150. The pixel defining layer 150 has a pixel opening and a second isolation opening 2 that penetrates the thickness thereof. The pixel opening is disposed correspondingly to the first electrode 121 of the light-emitting device, and the second isolation opening 2 is disposed correspondingly to the first isolation opening 1. The second isolation opening 2 includes a third sub-isolation opening and a fourth sub-isolation opening that are sequentially disposed away from the dielectric substrate 101, and the orthographic projection of the fourth sub-isolation opening on the dielectric substrate 101 is located within the orthographic projection of the third sub-isolation opening on the dielectric substrate 101.

[0051] In other words, the second partition opening 2 is also an undercut structure, and the first partition opening 1 is arranged below the second partition opening 2, forming two overlapping undercut structures. Compared with only the first partition opening 1 (that is, only one undercut structure), the two overlapping undercut structures can enhance the ability to isolate the charge generation layer 150, forming a plurality of charge generation units that are arranged in a disconnected manner.

[0052] In some embodiments, the orthographic projection of the second isolating opening 2 on the dielectric substrate 101 covers the orthographic projection of the first isolating opening 1 on the dielectric substrate 101, and the first isolating opening 1 and the second isolating opening 2 together form a first height buffer structure with the pixel defining layer 140 and the planarization layer 116. The display substrate further includes a second electrode layer 160, which is disposed on a side of the charge generating layer 150 away from the dielectric substrate 101; the first height buffer structure satisfies the requirement that the second electrode layer 160 is formed on a side of the charge generating layer 150 away from the dielectric substrate 101, so that the second electrode layer 160 is separated from the first electrode layer through the charge generating layer 130.

[0053] Specifically, the second isolating opening 2 is disposed above the first isolating opening 1, and the second isolating opening 2 is larger than the first isolating opening 1. The sidewalls of the second isolating opening 2 and the first isolating opening 1 form a gradient, so that the pixel defining layer 140 and the planarizing layer 116 form a first height buffer structure with a buffering effect, so that when the second electrode layer 160 is evaporated, the step difference of the second electrode material can be reduced, thereby preventing the second electrode material from puncturing the charge generating layer 150, causing the second electrode layer 160 to short-circuit with the first electrode 121, and affecting the performance of the display substrate.

[0054] The orthographic projection of the second partition opening 2 on the dielectric substrate 101 covers the orthographic projection of the first partition opening 1 on the dielectric substrate 101, specifically, the orthographic projection of the fourth sub-partition opening on the dielectric substrate 101 covers the orthographic projection of the second sub-partition opening on the dielectric substrate 101. That is, the smallest opening in the second partition opening 2 is larger than the largest opening in the first partition opening 1.

[0055] It can be understood that the pixel defining layer 140 is a multi-layer structure. With such a configuration, during the preparation of the display substrate, a second isolation opening 2 with an undercut structure can be formed on the multi-layer structure in the pixel defining layer 140 according to the different etching rates of the multi-layer structure in the pixel defining layer 140. In this way, on the basis of the first isolation opening 1, the ability to isolate the charge generating layer 150 is enhanced.

[0056] In some embodiments, the pixel defining layer 140 includes a first pixel defining layer 141, a second pixel defining layer 142 and a third pixel defining layer 143 which are stacked in sequence along a direction away from the dielectric substrate 101, and the second isolation opening 2 also includes a fifth sub-isolation opening, the fifth sub-isolation opening penetrates the first pixel defining layer 141, the third sub-isolation opening penetrates the second pixel defining layer 142, and the fourth sub-isolation opening penetrates the third pixel defining layer 143; and the orthographic projection of the fifth sub-isolation opening on the dielectric substrate 101 coincides with the orthographic projection of the fourth sub-isolation opening on the dielectric substrate 101.

[0057] Specifically, the pixel defining layer 140 is a three-layer structure, and the materials of the first pixel defining layer 141, the second pixel defining layer 142, and the third pixel defining layer 143 may be silicon oxide SiOx, silicon nitride SiN, and silicon oxide SiOx, respectively. When the three-layer structure of the pixel defining layer 140 is etched to form the second isolation opening 2, the silicon nitride of the second pixel defining layer 142 forms an indented structure. Since the first pixel defining layer 141 and the third pixel defining layer 143 are made of the same material and have the same etching rate, the sizes of the fifth sub-isolation opening and the fourth sub-isolation opening corresponding to the two layers may be the same.

[0058] In addition, the first isolation opening 1 penetrates at least a portion of the thickness of the planarization layer 116 , including two situations: the first isolation opening 1 only penetrates a portion of the thickness of the planarization layer 116 ; and the first isolation opening 1 penetrates the entire thickness of the planarization layer 116 .

[0059] For the case where the first isolating opening 1 only penetrates part of the thickness of the planarization layer 116: in some embodiments, the planarization layer 116 includes a first planarization layer 116a and a second planarization layer 116b stacked in sequence along a direction away from the dielectric substrate 101, and the first isolating opening 1 only penetrates the second planarization layer 116b; the display substrate also includes a first opening penetrating the second planarization layer 116b, and the first electrode 121 of the light-emitting device is located in the first opening, wherein the thickness of the first electrode 121 of the light-emitting device is h1, and the depth of the first opening along the thickness direction of the second planarization layer 116b is h2, and h1≥h2.

[0060] Specifically, Figure 3 As shown, the first isolation opening 1 only penetrates part of the thickness of the planarization layer 116. In this case, before preparing the first electrode 121, a first planarization layer 116a is prepared in advance to cover the protruding PT foreign matter and the concave defect, ensuring the normal preparation of the first electrode 121 and ensuring that the OLED works normally without causing yield loss. Optionally, the thickness of the first planarization layer 116a ranges from 0.2um to 20um, so as to ensure that the first planarization layer 116a can cover the protruding TP foreign matter and the concave defect, and will not be too thick to cause the display substrate to be too large.

[0061] In addition, when the first isolation opening 1 only penetrates a portion of the thickness of the planarization layer 116, the first electrode 121 is disposed in the first opening of the planarization layer 116. Generally, the thickness h1 of the first electrode 121 is equal to the depth h2 of the first opening. Figure 2Compared with the display substrate shown in the figure, the first planarization layer 116a in the planarization layer 116 can not only wrap the defects such as the protrusion TP of the dielectric substrate 101 in advance to ensure that no abnormality will occur in the subsequent preparation process, but the second planarization layer 116b also has a height compensation function. The second planarization layer 116b fills the area between two adjacent first electrodes 121 to ensure that the surface of the first electrode 121 away from the dielectric substrate 101 is level with the height of the inorganic layer in the spacing area between the adjacent first electrodes 121, and reduces the step difference between the surface of the first electrode 121 and the spacing area between the adjacent first electrodes 121, so as to prevent the second electrode material from being punctured due to the large step difference when the second electrode layer 160 is prepared later, thereby affecting the performance of the display substrate. In addition, in the process of preparing the display substrate, the first electrode 121 is first prepared on the first planarization layer 116a, and then the second planarization layer 116b is prepared. When the material of the second planarization layer 116b is evaporated, the material of the second planarization layer 116b may wrap the first electrode 121, affecting the connection between the first electrode 121 and the charge generation layer 150, resulting in a short circuit. Therefore, after evaporating the material of the second planarization layer 116b, it is necessary to etch the position corresponding to the first electrode 121 in the second planarization layer 116b so that the material of the second planarization layer does not affect the connection between the first electrode 121 and the charge generation layer 150. Therefore, the second planarization layer 116b is generally etched more by a certain thickness, resulting in the thickness h1 of the first electrode 121 being greater than the thickness of the second planarization layer 116b (the first opening penetrates the second planarization layer 116b, that is, h1≥h2). Optionally, the difference between h1 and h2 ranges from 100 Å to 200 Å, that is, the second planarization layer 116 b is generally etched 100 Å to 200 Å more.

[0062] In some embodiments, the second planarization layer 116b includes a first sub-planarization layer 110 and a second sub-planarization layer 120 which are stacked in sequence away from the dielectric substrate 101, wherein the first sub-partitioning opening penetrates the first sub-planarization layer 110, the second sub-partitioning opening penetrates the second sub-planarization layer 120, and the thickness of the second sub-planarization layer 120 is less than the thickness of the first sub-planarization layer 110.

[0063] Specifically, Figure 3As shown, as described above, the first partition opening 1 is an undercut structure, and the first sub-partition opening in the first partition opening 1 is larger than the second sub-partition opening. Therefore, in the process of preparing the charge generation layer 150, due to the obstruction above the first sub-partition opening, the material of the charge generation layer 150 will be discontinuous below and above the first partition opening 1, thereby realizing the isolation of the charge generation layer 150, and finally forming a charge generation unit with a disconnected setting. That is, the role of the second sub-planarization layer 120 corresponding to the top of the first sub-partition opening is to play a shielding role during the subsequent vapor deposition of the charge generation layer 150. Therefore, the second sub-planarization layer 120 can be set thinner as long as it is ensured that no collapse occurs during the subsequent vapor deposition. In some embodiments, the thickness of the second sub-planarization layer 120 ranges from 50A to 300A.

[0064] For the case where the first isolation opening 1 penetrates the entire thickness of the planarization layer 116: in some embodiments, as Figure 4 As shown, the planarization layer 116 includes a first planarization layer 116a and a second planarization layer 116b which are stacked in sequence in a direction away from the dielectric substrate 101, and the first isolation opening 1 penetrates the first planarization layer 116a and the second planarization layer 116b.

[0065] Specifically, Figure 4 As shown, when the first isolation opening 1 completely penetrates the planarization layer 116, the first electrode 121 of the light-emitting device is arranged above the second planarization layer 116b. That is, before preparing the first electrode 121, two layers of film, the first planarization layer 116a and the second planarization layer 116b, are prepared in advance to cover the protruding PT foreign matter and the concave defect, so as to ensure the normal preparation of the first electrode 121 and ensure that the OLED works normally without causing yield loss. At the same time, the first planarization layer 116a and the second planarization layer 116b can also form the first isolation opening 1 for disconnecting the charge generation layer 150 to form a charge generation unit.

[0066] In some embodiments, the thickness of the second planarization layer 116b is less than the thickness of the first planarization layer 116a. The second planarization layer 116b corresponding to the opening of the first sub-partition serves to shield the charge generation layer 150 during the subsequent evaporation. Therefore, the second planarization layer 116b can be set thinner as long as it is ensured that it does not collapse during the subsequent evaporation. The thickness of the second planarization layer 116b ranges from 50A to 300A.

[0067] In the case where the first isolating opening 1 passes through the entire thickness of the planarizing layer 116, the display substrate includes not only the dielectric substrate 101, the planarizing layer 116, the first electrode layer, the pixel defining layer 140, and the charge generating layer 150, but also includes a height compensation layer 180, which is arranged on the side of the second planarizing layer 116b close to the charge generating layer 150. The height compensation layer 180 includes a plurality of height compensation structures, and a height compensation structure is arranged between the first electrodes 121 of any two adjacent light-emitting devices; the height compensation structure has a second opening that passes through its thickness, and the second opening is arranged one-to-one with the first isolating opening 1, and the orthographic projection of one second opening on the dielectric substrate 101 covers the orthographic projection of one first isolating opening 1 on the dielectric substrate 101.

[0068] Among them, the first isolation opening 1 and the second opening, together, make the flattening layer 116 and the height compensation structure form a second height buffer structure; the display substrate also includes a second electrode layer 160, which is arranged on the side of the charge generation layer 150 away from the dielectric substrate 101; the second height buffer structure satisfies the requirement that the second electrode layer 160 is formed on the side of the charge generation layer 150 away from the dielectric substrate 101, so that the second electrode layer 160 is disconnected from the first electrode layer through the charge generation layer 150.

[0069] Specifically, the height compensation structure has a height compensation function, which ensures that the surface of the first electrode 121 facing away from the dielectric substrate 101 is level with the inorganic layer in the spacer between adjacent first electrodes 121, and reduces the step difference between the surface of the first electrode 121 and the spacer between adjacent first electrodes 121, thereby preventing the second electrode material from being punctured due to the large step difference when the second electrode layer 160 is subsequently prepared, thereby affecting the performance of the display substrate. At the same time, the second opening that runs through the thickness of the height compensation structure cooperates with the first isolation opening 1 to disconnect the charge generation layer 150 to form a charge generation unit.

[0070] The orthographic projection of the second opening on the dielectric substrate 101 covers the orthographic projection of the first isolating opening 1 on the dielectric substrate 101, that is, the second opening is arranged above the first isolating opening 1, and the second opening is larger than the first isolating opening 1. The sidewalls of the second opening and the first isolating opening 1 form a gradient, so that the height compensation layer 180 and the planarization layer 116 form a second height buffer structure with a buffering effect, so that when the second electrode layer 160 is evaporated, the step difference of the second electrode material can be reduced, thereby preventing the second electrode material from puncturing the charge generating layer 150, causing the second electrode layer 160 to short-circuit with the first electrode 121, and affecting the performance of the display substrate.

[0071] In some embodiments, Figure 3-Figure 4As shown, the display substrate is divided into a display area 10a and a non-display area 10c surrounding the display area 10a. The dielectric substrate 101 includes a cutting path opening 3 that penetrates a portion of its thickness, and the cutting path opening 3 is located in the non-display area 10c. The planarization layer 116 covers the cutting path opening 10c, and the maximum thickness of the planarization layer is h3. The depth of the cutting path opening 3 along the thickness direction of the dielectric substrate 101 is h4, and h3>h4.

[0072] Specifically, Figure 3-Figure 4 As shown, the planarization layer 116 uses its leveling effect to fill the gap of the incoming cutting path of the dielectric substrate, improve the diagonal Mura, optimize the display quality, and improve the competitiveness of the product. Wherein, when the planarization layer 116 includes a multi-layer structure, only one layer of the planarization layer 116 can be used to fill the cutting path opening 3 (for example, Figure 4 As shown), the cutting path opening 3 can also be filled with a multi-layer structure of the planarization layer 116 (for example Figure 3 As shown), it can be specifically determined according to the thickness of each layer structure in the planarization layer 116.

[0073] The display substrate provided by the embodiment of the present disclosure, in the first aspect, before preparing the first electrode 121, the planarization layer 116 is prepared in advance to cover the protruding PT foreign matter and the concave defect in the dielectric substrate 101, to ensure the normal preparation of the first electrode 121, thereby ensuring the normal operation of the OLED without causing yield loss. In the second aspect, the planarization layer 116 can also use its leveling effect to fill the gap of the opening 3 of the incoming cutting path, improve the twill Mura, optimize the display quality, and improve the product competitiveness. In the third aspect, the first isolation opening 1 that at least penetrates part of the thickness of the planarization layer 116 can also isolate the charge generation layer 150 to form a charge generation unit; at the same time, the second isolation opening 2 that penetrates the pixel defining layer and the first isolation opening 1 form an overlapping undercut structure, which can also enhance the ability to isolate the charge generation layer 150. Further, the second isolation opening 2 and the first isolation opening 1 form a gradient buffer structure, which can improve the puncture of the second electrode layer 160 and ensure the normal display of the display substrate.

[0074] In a second aspect, based on the same concept, the present disclosure also provides a method for preparing a display substrate, the method comprising the following steps:

[0075] S101, providing a dielectric substrate 101; wherein the dielectric substrate 101 includes a conductive component.

[0076] S102, forming a planarization layer 116 and a first electrode layer, wherein the side of the planarization layer 116 facing away from the dielectric substrate 101 is a flat surface; the first electrode layer is located on the flat surface of the planarization layer 116, and the first electrode layer includes a plurality of first electrodes 121 of light-emitting devices.

[0077] S103 , forming a charge generation layer 150 , wherein the charge generation layer 150 includes a plurality of charge generation units of the light emitting device.

[0078] Before forming the charge generation layer 150 in step S103, the preparation method further includes:

[0079] S104, forming a first isolation opening 1 that penetrates at least a portion of the thickness of the planarization layer 116, wherein the first isolation opening 1 satisfies the requirement of disconnecting the charge generation layer 150 to form a charge generation unit; the first isolation opening 1 includes a first sub-isolation opening and a second sub-isolation opening that are sequentially arranged in a direction away from the dielectric substrate 101, and an orthographic projection of the second sub-isolation opening on the dielectric substrate 101 is located within the orthographic projection of the first sub-isolation opening on the dielectric substrate 101.

[0080] The method for preparing a display substrate provided in an embodiment of the present disclosure prepares a planarization layer 116 in advance before preparing the first electrode 121 to cover the protruding PT foreign matter and the concave defect in the dielectric substrate 101, thereby ensuring that the first electrode 121 is normally prepared on a flat surface, thereby ensuring that the OLED works normally without causing yield loss.

[0081] In some embodiments, before S103, forming the charge generation layer 150, and after S104, forming the first isolation opening 1, the preparation method further includes:

[0082] S106. Form a pixel defining layer 140, wherein the pixel defining layer 140 has a pixel opening and a second isolating opening 2 that penetrate through the thickness thereof, the pixel opening is arranged corresponding to the first electrode 121 of the light-emitting device, the second isolating opening 2 is arranged corresponding to the first isolating opening 1, the second isolating opening 2 and the first isolating opening 1; wherein the second isolating opening 2 includes a third sub-isolating opening and a fourth sub-isolating opening that are arranged in sequence away from the dielectric substrate 101, and the orthographic projection of the fourth sub-isolating opening on the dielectric substrate 101 is located within the orthographic projection of the third sub-isolating opening on the dielectric substrate 101.

[0083] In the embodiment of the present disclosure, on the basis of the first isolation opening 1 , a second isolation opening 2 penetrating the pixel defining layer 140 is further formed, and the cooperation of the two can enhance the ability to isolate the charge generating layer 150 .

[0084] In step S104, in forming the first isolating opening 1 penetrating at least a portion of the thickness of the planarization layer 116, the first isolating opening 1 may only penetrate a portion of the thickness of the planarization layer 116; the first isolating opening 1 may also penetrate the entire thickness of the planarization layer 116. The following is a detailed description of the method for preparing the display substrate in two cases using specific embodiments.

[0085] Figure 5a-5eThey are Figure 3 Schematic diagram of an intermediate product formed in the method for preparing a display substrate in the embodiment, wherein the first isolation opening 1 in the display substrate only penetrates a portion of the thickness of the planarization layer 116; wherein, Figure 5a for Figure 3 Schematic diagram of an intermediate product formed in step S501 of the substrate preparation method is shown in FIG. Figure 5b for Figure 3 A schematic diagram of an intermediate product formed in steps S501 to S502 in the substrate preparation method is shown in FIG. Figure 5c for Figure 3 A schematic diagram of an intermediate product formed in steps S501 to S503 in the substrate preparation method is shown in FIG. Figure 5d for Figure 3 A schematic diagram of an intermediate product formed in steps S501 to S504 in the substrate preparation method is shown in FIG. Figure 5e for Figure 3 FIG. 2 is a schematic diagram of an intermediate product formed in steps S501 to S505 in the substrate preparation method.

[0086] like Figure 5a-5e As shown, the embodiment of the present disclosure provides a method for preparing a display substrate, and the preparation method specifically includes:

[0087] S501, providing a dielectric substrate 101, and forming a first planarization layer 116a on the dielectric substrate 101. The dielectric substrate 101 is integrated with a conductive device, and the side of the first planarization layer 116a facing away from the dielectric substrate 101 is a flat surface.

[0088] S502 , forming a first electrode layer on the first planarization layer 116 a , and forming a plurality of first electrodes 121 through a patterning process.

[0089] S503, forming a second planarization layer 116b on the first electrode layer, and etching to make the thickness of the first electrode 121 greater than the thickness of the second planarization layer 116b to ensure that the first electrode 121 is subsequently electrically connected to the charge generation layer 150; and forming a first isolation opening 1 that passes through the second planarization layer 116b by a composition process.

[0090] S504 , forming a pixel defining layer 140 , and forming a first opening corresponding to the first electrode 121 and a second isolating opening 2 corresponding to the first isolating opening 1 through a patterning process.

[0091] S505 , sequentially forming a charge generation layer 150 , a second electrode layer 160 and an encapsulation layer 170 . The charge generation layer 150 is separated by the first isolation opening 1 and the second isolation opening 2 to form a charge generation unit.

[0092] In the embodiment of the present disclosure, before preparing the first electrode 121, a first planarization layer 116a is prepared in advance to cover the protruding PT foreign matter and the concave defect, so as to ensure the normal preparation of the first electrode 121 and ensure the normal operation of the OLED without causing yield loss. Optionally, the thickness of the first planarization layer 116a ranges from 0.2um to 20um, so as to ensure that the first planarization layer 116a can cover the protruding PT foreign matter and the concave defect, and will not be too thick to cause the display substrate to be too large.

[0093] Figure 6a-6f They are Figure 4 Schematic diagram of an intermediate product formed in the method for preparing a display substrate, wherein the first isolation opening 1 in the display substrate penetrates the entire thickness of the planarization layer 116; wherein, Figure 6a for Figure 4 ] A schematic diagram of an intermediate product formed in step S601 of the substrate preparation method is shown in FIG. Figure 6b for Figure 4 Schematic diagram of an intermediate product formed in steps S601 to S602 in the substrate preparation method is shown in FIG. Figure 6c for Figure 4 Schematic diagram of an intermediate product formed in steps S601 to S603 in the substrate preparation method is shown in FIG. Figure 6d for Figure 4 Schematic diagram of an intermediate product formed in steps S601 to S604 in the substrate preparation method is shown in FIG. Figure 6e for Figure 4 Schematic diagram of an intermediate product formed in steps S601 to S605 in the substrate preparation method is shown in FIG. Figure 6f for Figure 4 FIG. 4 is a schematic diagram showing an intermediate product formed in steps S601 to S606 in the substrate preparation method.

[0094] like Figure 6a-6f As shown, the embodiment of the present disclosure provides another method for preparing a display substrate, and the preparation method specifically includes:

[0095] S601, providing a dielectric substrate 101, and sequentially forming a first planarization layer 116a and a second planarization layer 116b on the dielectric substrate 101. The dielectric substrate 101 is integrated with a conductive device, and the surfaces of the first planarization layer 116a and the second planarization layer 116b facing away from the dielectric substrate 101 are both flat surfaces.

[0096] S602 , forming a first isolation opening 1 penetrating the first planarization layer 116 a and the second planarization layer 116 b through a patterning process.

[0097] S603 , forming a first electrode layer on the second planarization layer 106 b , and forming a first electrode 121 through a patterning process.

[0098] S604, forming a height compensation layer 180. The height compensation layer 180 includes a height compensation structure, wherein a height compensation structure is disposed between any two adjacent first electrodes 121, and a second opening corresponding to the first isolation opening 1 is formed on the height compensation structure through a patterning process.

[0099] S605 , forming a pixel defining layer 140 , and forming a first opening corresponding to the first electrode 121 and a second isolating opening 2 corresponding to the first isolating opening 1 through a patterning process.

[0100] S606, sequentially forming a charge generation layer 150, a second electrode layer 160 and an encapsulation layer 170. The charge generation layer 150 is separated by the first isolation opening 1 and the second isolation opening 2 to form a charge generation unit.

[0101] In the method for preparing a display substrate provided by the embodiment of the present disclosure, the first isolation opening 1 completely penetrates the planarization layer 116. Before preparing the first electrode 121, two film layers, the first planarization layer 116a and the second planarization layer 116b, are prepared in advance to cover the protruding PT foreign matter and the concave defect, so as to ensure the normal preparation of the first electrode 121 and ensure that the normal operation of the OLED does not cause yield loss. The difference from the embodiment corresponding to FIG. 5 is that the embodiment of the present disclosure also needs to prepare a height compensation layer 180 to ensure that when preparing the second electrode layer 160, the second electrode layer 160 will not puncture the charge generation layer 150 due to the large step difference, causing the second electrode layer 160 to short-circuit with the first electrode 121.

[0102] It can be understood that the specific design details in the embodiment of the display substrate provided in the first aspect are also applicable to the method for preparing the display substrate in the second aspect, and will not be repeated here.

[0103] In a third aspect, based on the same concept, an embodiment of the present disclosure further provides a display panel, which includes any display substrate in the embodiment of the first aspect mentioned above.

[0104] It is understood that the above embodiments are merely exemplary embodiments used to illustrate the principles of the present invention, but the present invention is not limited thereto. For those skilled in the art, various modifications and improvements can be made without departing from the spirit and essence of the present invention, and these modifications and improvements are also considered to be within the scope of protection of the present invention.

Claims

1. A display substrate, characterized in that: include: A dielectric substrate having a conductive device integrated therein; A planarization layer is arranged on the dielectric substrate, and a side of the planarization layer facing away from the dielectric substrate is a flat surface; A first electrode layer, arranged on a side of the planarization layer away from the dielectric substrate, the first electrode layer comprising first electrodes of a plurality of light-emitting devices; A charge generation layer is arranged on a side of the first electrode layer away from the dielectric substrate, and the charge generation layer includes a plurality of charge generation units of light-emitting devices; wherein, The display substrate further comprises: A first isolation opening penetrating through at least a portion of the thickness of the planarization layer, wherein the first isolation opening is sufficient to disconnect the charge generation layer to form the charge generation unit; The first partition opening includes a first sub-partition opening and a second sub-partition opening which are sequentially arranged in a direction away from the dielectric substrate, and an orthographic projection of the second sub-partition opening on the dielectric substrate is located within an orthographic projection of the first sub-partition opening on the dielectric substrate.

2. The display substrate according to claim 1, characterized in that: The display substrate further includes a pixel defining layer, which is arranged on a side of the first electrode layer close to the charge generating layer, and the pixel defining layer has a pixel opening and a second isolation opening that penetrates the thickness thereof, the pixel opening is arranged corresponding to the first electrode of the light emitting device, and the second isolation opening is arranged corresponding to the first isolation opening; wherein, The second partition opening includes a third sub-partition opening and a fourth sub-partition opening which are sequentially arranged away from the dielectric substrate, and the orthographic projection of the fourth sub-partition opening on the dielectric substrate is located within the orthographic projection of the third sub-partition opening on the dielectric substrate.

3. The display substrate according to claim 2, characterized in that: The orthographic projection of the second isolation opening on the dielectric substrate covers the orthographic projection of the first isolation opening on the dielectric substrate, and the first isolation opening and the second isolation opening together enable the pixel defining layer and the planarization layer to form a first height buffer structure; The display substrate further includes a second electrode layer, which is arranged on a side of the charge generating layer away from the dielectric substrate; the first height buffer structure satisfies the requirement that the second electrode layer is formed on a side of the charge generating layer away from the dielectric substrate, so that the second electrode layer is disconnected from the first electrode layer through the charge generating layer; wherein, The orthographic projection of the fourth sub-partition opening on the dielectric substrate covers the orthographic projection of the second sub-partition opening on the dielectric substrate.

4. The display substrate according to claim 2, characterized in that: The pixel defining layer includes a first pixel defining layer, a second pixel defining layer and a third pixel defining layer which are sequentially stacked in a direction away from the dielectric substrate. The second partition opening further includes a fifth sub-partition opening, the fifth sub-partition opening penetrates the first pixel defining layer, the third sub-partition opening penetrates the second pixel defining layer, and the fourth sub-partition opening penetrates the third pixel defining layer; The orthographic projection of the fifth sub-partition opening on the dielectric substrate coincides with the orthographic projection of the fourth sub-partition opening on the dielectric substrate.

5. The display substrate according to claim 1, characterized in that: The planarization layer comprises a first planarization layer and a second planarization layer which are sequentially stacked in a direction away from the dielectric substrate, and the first isolation opening only passes through the second planarization layer; The display substrate further includes a first opening penetrating through the second planarization layer, and the first electrode of the light emitting device is located in the first opening, wherein: The thickness of the first electrode of the light emitting device is h1, the depth of the first opening along the thickness direction of the second planarization layer is h2, and h1≥h2.

6. The display substrate according to claim 1, characterized in that: The planarization layer comprises a first planarization layer and a second planarization layer which are sequentially stacked in a direction away from the dielectric substrate, and the first isolation opening penetrates the first planarization layer and the second planarization layer; The display substrate further comprises a height compensation layer, which is arranged on a side of the second planarization layer close to the charge generation layer, the height compensation layer comprises a plurality of height compensation structures, and one of the height compensation structures is arranged between the first electrodes of any two adjacent light-emitting devices; the height compensation structure has a second opening that penetrates through the thickness thereof, the second opening is arranged in one-to-one correspondence with the first isolation opening, and the orthographic projection of one of the second openings on the dielectric substrate covers the orthographic projection of one of the first isolation openings on the dielectric substrate; wherein, The first isolation opening and the second opening enable the planarization layer and the height compensation structure to form a second height buffer structure; The display substrate also includes a second electrode layer, which is arranged on a side of the charge generating layer away from the dielectric substrate; the second height buffer structure satisfies the requirement that the second electrode layer is formed on a side of the charge generating layer away from the dielectric substrate, so that the second electrode layer is disconnected from the first electrode layer through the charge generating layer.

7. The display substrate according to claim 1, characterized in that: The display substrate is divided into a display area and a non-display area surrounding the display area. The dielectric substrate includes a cutting path opening that penetrates a portion of its thickness, and the cutting path opening is located in the non-display area; The planarization layer covers the cutting path opening, the maximum thickness of the planarization layer is h3, the depth of the cutting path opening along the thickness direction of the dielectric substrate is h4, and h3>h4.

8. The display substrate according to claim 1, characterized in that: The material of the dielectric substrate is silicon-based material.

9. A display panel, characterized in that: Comprising the display substrate as described in any one of claims 1-8.

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