High-speed radar signal processing system

Abstract

The utility model relates to a high-speed radar signal processing system, belongs to the technical field of radars, and solves the problem of existing radar signal processing in the prior art. The system comprises a radar signal acquisition chipset, an FPGA chipset, an SRIO exchange chip, a DSP chipset, a signal acquisition power supply circuit and an upper computer. The radar signal acquisition chip set is in communication connection with the FPGA chip set; the FPGA chipset, the DSP chipset and the upper computer are all in communication connection with the SRIO exchange chip; the signal acquisition power supply circuit supplies power to the radar signal acquisition chip set. And efficient and flexible radar signal processing is realized.

Description

Technical Field

[0001] The utility model relates to the technical field of radar set, in particular to a high-speed radar signal processing system. Background Art

[0002] Today's radars have developed from single-mode to multi-mode. The functions of new composite radars are becoming increasingly complex, the amount of data transmitted is increasing, and the requirements for communication speed are increasing accordingly.

[0003] Traditional radars transmit information in the form of RS422, 1553B, CAN and other buses, and the communication rate is too low to meet the demand. At the same time, the requirement for national production of weapon systems is also on the agenda, which requires radars to find new communication methods that are efficient, high-speed, and highly reliable, and to achieve independent control of all products. Utility Model Content

[0004] In view of the above analysis, the utility model aims to provide a high-speed radar signal processing system to solve the problem of low transmission efficiency of existing radar signal processing.

[0005] The purpose of this utility model is mainly achieved through the following technical solutions:

[0006] A high-speed radar signal processing system, comprising: a radar signal acquisition chipset, an FPGA chipset, an SRIO switching chip, a DSP chipset, a signal acquisition power supply circuit and a host computer;

[0007] The radar signal acquisition chipset is communicatively connected with the FPGA chipset;

[0008] The FPGA chipset, DSP chipset and host computer are all communicatively connected with the SRIO switching chip;

[0009] The signal acquisition power supply circuit supplies power to the radar signal acquisition chipset.

[0010] Based on the further improvement of the above system, each power pin of the switching chip is connected to a first capacitor; the capacitance value of the first capacitor ranges from 0.01uF to 0.1uF.

[0011] Based on further improvement of the above system, among the power pins of the switching chip, a second capacitor is connected to every power pin of a first preset value; the capacitance value of the second capacitor is 1uF.

[0012] Based on further improvement of the above system, among the power pins of the switching chip, a third capacitor is connected to every second preset power pin; the capacitance value of the third capacitor is greater than 10uF.

[0013] Based on further improvement of the above system, the FPGA chipset, DSP chipset and host computer are electrically connected to the SRIO switch chip via an MVPX high-speed inter-board connector.

[0014] Based on the further improvement of the above system, each chip ID configuration pin of the SRIO switch chip is grounded through a first resistor, and each chip ID configuration pin is also connected to a power supply through a second resistor.

[0015] Based on further improvement of the above system, the system also includes a configuration chip of the switching chip, and the IO pins of the configuration chip are connected to the reset pin, IIC configuration clock pin, and IIC configuration data pin of the SRIO switching chip.

[0016] Based on further improvements of the above system, the high-speed radar signal processing system also includes a clock circuit; the clock circuit includes a clock chip and a clock buffer, the output pin of the clock chip is connected to the input pin of the clock buffer; the clock pin of each high-speed ADC converter is connected to the clock output pin of the clock buffer.

[0017] Based on further improvement of the above system, the signal acquisition power supply circuit includes 4 LDO power chips, the LDO power chip includes an enable pin, the enable pin EN of the LDO power chip is grounded through a resistor R209; the enable pin EN of the LDO power chip is also connected to the IO pin of the FPGA chip.

[0018] Based on the further improvement of the above system, the radar signal acquisition chipset, FPGA chipset, SRIO switching chip, DSP chipset, and signal acquisition power supply circuit of the high-speed radar signal processing system are arranged on multiple PCB boards, and the multiple PCB boards are a stacked structure;

[0019] Both adjacent sides of the plane layer where the signal lines and data lines of the high-speed radar signal processing system are located are ground layers;

[0020] The vias on the PCB board for signal connections between the radar signal acquisition chipset and the FPGA chipset are back-drilled vias, and non-functional pads are removed.

[0021] Compared with the prior art, the utility model realizes multi-channel radar signal detection through a radar signal acquisition chipset and an FPGA chipset, and supplies power to the radar signal acquisition chipset through a signal acquisition power supply circuit, thereby improving the stability and rate of acquisition, and connecting the FPGA chipset, the DSP chipset and the host computer through an SRIO switching chip, so that data transmission is no longer point-to-point, but interface time-division multiplexing is realized through the switching chip, so that radar signal data acquisition and processing can be performed simultaneously through multiple channels, thereby increasing the transmission bandwidth, improving the data acquisition and transmission efficiency, and having higher flexibility.

[0022] In the present invention, the above-mentioned technical solutions can also be combined with each other to achieve more preferred combination solutions. Other features and advantages of the present invention will be described in the following content, and some advantages can be obvious from the description or understood by implementing the present invention. The purpose and other advantages of the present invention can be achieved and obtained through the contents specifically pointed out in the text and the drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] The accompanying drawings are only used for the purpose of illustrating specific embodiments and are not to be considered as limiting the present invention. In the entire drawings, the same reference symbols represent the same components.

[0024] Figure 1 A block diagram of a high-speed radar signal processing system according to an embodiment of the utility model;

[0025] Figure 2 This is a circuit diagram of an LDO power chip according to an embodiment of the utility model;

[0026] Figure 3 This is a configuration pin circuit diagram of the SRIO switch chip according to an embodiment of the utility model. DETAILED DESCRIPTION

[0027] The preferred embodiments of the present invention are described in detail below in conjunction with the accompanying drawings, wherein the accompanying drawings constitute a part of the present application and are used together with the embodiments of the present invention to illustrate the principles of the present invention, but are not used to limit the scope of the present invention.

[0028] A specific embodiment of the utility model discloses a high-speed radar signal processing system, such as Figure 1 As shown, including:

[0029] Radar signal acquisition chipset, FPGA chipset, SRIO switch chip, DSP chipset, signal acquisition power supply circuit and host computer;

[0030] The radar signal acquisition chipset is communicatively connected with the FPGA chipset;

[0031] The FPGA chipset, DSP chipset and host computer are all communicatively connected with the SRIO switching chip;

[0032] The signal acquisition power supply circuit supplies power to the radar signal acquisition chipset.

[0033] During implementation, the radar signal acquisition chipset may include multiple ADC chips for acquiring radar signals. The radar signal acquisition chip transmits the acquired signals to the FPGA chipset, which performs signal preprocessing, such as channelization and angle resolution, and sends the processed signals to the DSP chipset through the SRIO switching chip, where the calculations for target sorting and target recognition are implemented, and the calculation results are sent to the host computer through the SRIO switching chip for display and analysis.

[0034] Compared with the prior art, the utility model realizes multi-channel radar signal detection through a radar signal acquisition chipset and an FPGA chipset, supplies power to the radar signal acquisition chipset through a signal acquisition power supply circuit, improves the stability and rate of acquisition, connects the FPGA chipset, the DSP chipset and the host computer through an SRIO switching chip, so that data transmission is no longer point-to-point, but interface time-division multiplexing is realized through the switching chip, so that radar signal data acquisition and processing can be performed simultaneously in multiple channels, the transmission bandwidth is increased, the data acquisition and transmission efficiency is improved, and it has higher flexibility.

[0035] It should be noted that the radar signal processing and data processing involved in FPGA chips and DSP chips are existing technologies. The existing radar signal processing methods and data processing methods can be run in FPGA and DSP. The utility model does not involve any software improvements.

[0036] During implementation, the high-speed radar signal processing system is arranged on a PCB board, and the PCB board is a multi-layer PCB board.

[0037] During implementation, the high-speed radar signal processing system includes 4 high-speed ADC converters, and the high-speed ADC converter can use the YA12D2G6A chip. The YA12D2G6A is a 12-bit, 2600MSPS, dual-channel high-performance analog-to-digital converter. The radar signal acquisition chipset uses 4 high-speed ADC chips. The entire radar signal acquisition chipset can simultaneously perform analog-to-digital conversion of eight-way high-speed signals, realize eight-way synchronous sampling within the board, and support multi-way synchronous sampling between expandable boards.

[0038] During implementation, the system also includes a clock circuit. The clock circuit includes a clock chip and a clock buffer, the output pin of the clock chip is connected to the input pin of the clock buffer; the clock pin of each high-speed ADC converter is connected to the clock output pin of the clock buffer. The sampling clock of the radar signal acquisition chipset is 2.4GHz, and a high-speed clock chip and a clock buffer are used to provide sampling clocks for four ADC chips. During implementation, the clock chip can use GMD7043, and the clock buffer can use GMD946.

[0039] During implementation, four high-speed ADC converters are connected to an FPGA chip in the FPGA chipset to send the collected data to the FPGA. The data converted by the ADC is output to the GTH bank of the FPGA. The interface between the ADC and the FPGA uses the JESD204B interface, and the data of each channel is transmitted using four lanes.

[0040] During implementation, the ADC chip requires four power supplies: analog 1.0V, digital 1.0V, 1.8V, and 2.2V. Therefore, the system also includes a power circuit to power the ADC chipset. During implementation, the power circuit includes 4 LDO power chips; each power chip provides power of different voltages, that is, each chip provides a power supply. LDO-type power chips have small ripple and good output power quality, which can help improve the performance of ADC, but LDO itself consumes a lot of power, so the input and output voltage difference should be as small as possible. The sampling rate of the radar signal acquisition chipset is relatively high, and special attention should be paid to PCB layout and wiring. The four ADCs, clock chips, and FPGAs should be as close as possible to avoid the clock line and data line being too long, and the three chips should be placed on the same layer of the printed circuit board to reduce the design of punching holes on the printed line during signal transmission. ADC and LDO should also be as close as possible to shorten the power transmission length and avoid excessive voltage drop on the PCB copper. During implementation, the LDO power chip can use SM74401.

[0041] For example, an LDO power chip that provides a simulated 1.0V voltage is Figure 2 As shown, each voltage output pin of the LDO power chip is also grounded through a fifth capacitor C70 and a sixth capacitor C563, and the fifth capacitor C70 and the sixth capacitor C563 are connected in parallel;

[0042] In order to isolate the ADC and avoid burning the ADC due to abnormal output, each voltage output pin of the LDO power chip is also connected to the radar signal acquisition chip through the first inductor L65 and the second inductor L18, and the first inductor L65 and the second inductor L18 are connected in parallel.

[0043] The LDO power chip includes a feedback pin FB, which is connected to the voltage output pin through a third resistor R242, and is also grounded through a fourth resistor R211. The LDO power chip adjusts the output voltage through the third resistor R242 and the fourth resistor R211.

[0044] The LDO power chip includes an enable pin, and the enable pin EN of the LDO power chip is grounded through a resistor R209; the enable pin EN of the LDO power chip is also connected to an IO pin of the FPGA chip;

[0045] The LDO power chip includes a BIAS pin, and the BIAS pin is grounded through a seventh capacitor C67;

[0046] The LDO power chip includes a soft start pin, and the soft start pin is grounded through an eighth capacitor C435.

[0047] The other three power supplies, namely the digital 1.0V, 1.8V and 2.2V LDO power supplies, have the same structure as the LDO power chip providing the analog 1.0V voltage, and the only difference is the input voltage and the resistance values ​​of the third resistor R242 and the fourth resistor R211.

[0048] During implementation, in order to ensure synchronous sampling of all channels, the clock lines output by the clock chip to the four ADCs are all of equal length, and the data lines output by the four ADCs to the FPGA are also all of equal length.

[0049] During implementation, the radar signal acquisition chipset, FPGA chipset, SRIO switching chip, DSP chipset, and signal acquisition power supply circuit of the high-speed radar signal processing system are arranged on multiple PCB boards, and the multiple PCB boards are of a stacked structure;

[0050] Both adjacent sides of the plane layer where the signal lines and data lines of the high-speed radar signal processing system are located are ground layers;

[0051] The vias on the PCB board for signal connections between the radar signal acquisition chipset and the FPGA chipset are back-drilled vias, and non-functional pads are removed.

[0052] When working at full speed, the data transmission rate between ADC and FPGA is as high as 9Gbps. Therefore, when the PCB of each board of the high-speed radar signal processing system is designed for stacking, the adjacent two sides of the plane layer where the signal line and the data line are located are ground layers. The vias on the PCB board for the signal connection between the radar signal acquisition chipset and the FPGA chipset are back-drilled vias, and non-functional pads are removed.

[0053] The AC coupling capacitor on the transmission line should be on the same layer as the ADC and FPGA. The signal should be routed as close to the bottom layer as possible, and the via stub on the signal line should be as short as possible. If the layout is difficult and the capacitor must be routed on the bottom layer, the via on the signal line should be back-drilled during PCB production, and the non-functional pads of the via should be removed to make the transmission path impedance of the entire signal line as continuous as possible. All clock lines and data lines must have complete ground planes on both sides to ensure that the signal has the shortest return path. The analog signal area at the front end of the ADC should be grounded, and a hollow area should be made between two adjacent channels to increase the isolation between channels.

[0054] During implementation, the FPGA chip can be JFM7VX690T80-N and JFM7VX690T36-N. JFM7VX690T80-N has an 80X GTH high-speed interface, which can simultaneously receive eight channels of collected data, and transfer the data to the next level through the GTH interface after pre-processing. JFM7VX690T36-N has rich resources such as Block RAM and CLB, which can meet the needs of general radar signal processing.

[0055] In order to improve data transmission efficiency, SRIO switching chips are used to connect the FPGA chipset, DSP chipset and host computer. That is, the FPGA chipsets, FPGA and DSP, DSP and host computer, and FPGA and host computer all communicate through SRIO switching chips.

[0056] During implementation, the switching chip used is JYCSW1848 switching chip.

[0057] The JYCSW1848 switch chip includes 12 groups of 4X GTX high-speed interfaces, supports 4 standard RapidIO priorities, supports unicast, multicast and broadcast. The maximum line rate is 6.25Gbaud, and each port provides a maximum of 20Gbps.

[0058] During implementation, the system clock of the switching chip is provided by an external differential crystal oscillator, and the crystal oscillator can use JZPB-33-L-156.25-V3-A4-C3-A-1.

[0059] Specifically, in order to improve the reliability of the SRIO switch chip, each chip ID configuration pin of the SRIO switch chip is grounded through a first resistor, and each chip ID configuration pin is also connected to a power supply through a second resistor.

[0060] During implementation, the configuration pins of the exchange chip, such as IIC address width selection, IIC master-slave mode selection, input reference clock frequency selection, quadrant configuration, IIC slave address, etc., are configured and connected by means of resistor pull-up or pull-down, and cannot be left floating to avoid generating an indeterminate state that causes unreliable chip operation.

[0061] The system also includes a configuration chip of the switching chip, and the IO pins of the configuration chip are connected to the reset pin RESET, the IIC configuration clock pin SCL, and the IIC configuration data pin SDA of the SRIO switching chip, for configuring the SRIO switching chip. During implementation, the configuration chip is connected to a FLASH chip. During implementation, the configuration chip uses a FMQL45T900-N fully programmable fusion chip, and the FLASH chip uses a GD25LB256EFIR FLASH chip for storing the configuration program.

[0062] It should be noted that the configuration program involved in the configuration circuit is a prior art, and the existing configuration program can be run in the configuration chip and the FLASH chip. The utility model does not involve any improvement in software.

[0063] In order to improve the power quality of the switching chip, the PCB layout and wiring should consider placing enough filter capacitors on the power pins of the switching chip. During implementation, each power pin of the switching chip is connected to a first capacitor; the capacitance value of the first capacitor ranges from 0.01uF to 0.1uF. During implementation, each power pin is connected to a first capacitor, which is a small capacitor. The first capacitor should be used interspersed, that is, the capacitance values ​​of the first capacitors connected to two adjacent power pins should be different, so as to evenly cover the noise in a wider frequency range and achieve the effects of filtering and decoupling.

[0064] In order to further improve the stability of the circuit, among the power pins of the switching chip, a second capacitor is connected to every power pin of a first preset value; the capacitance value of the second capacitor is 1uF.

[0065] During implementation, the first preset value may be 4, that is, the second capacitor is connected to every four power pins to improve filtering performance.

[0066] In order to increase the ability of the circuit to resist instantaneous large current changes, in the power pins of the switching chip, a third capacitor is also connected to the power pins of every second preset value; the capacitance value of the third capacitor is greater than 10uF. During implementation, the second preset value can be 9, that is, a large capacitor, namely the third capacitor, is connected to every 10 power pins, thereby improving the ability of the circuit to resist instantaneous large current changes. During implementation, the small capacitor of 0402 package can be directly placed on the back of the chip power pin for nearby filtering; the large-capacity capacitor of 1210 package can be placed nearby around the chip to achieve the function of filtering and energy storage. In the case of insufficient space, two power pins can share a small capacitor to ensure that more than two-thirds of the power pins are covered. Good power supply capacity can help the switching chip work more stably. The withstand voltage value of all capacitors selected in the circuit should be more than twice the actual working circuit voltage value to avoid the capacitor affecting the circuit function due to short circuit or open circuit. The pin functions of the switching chip TCK, TDI, TMS, TRST, etc. are not used, and they are grounded with pull-down resistors to avoid external signals from interfering with them and causing disorder in the working of the switching chip.

[0067] When implementing, Figure 3 As shown, each chip ID configuration pin of the SRIO switch chip is grounded through a first resistor, and each chip ID configuration pin is also connected to a power supply through a second resistor.

[0068] The switching chip is connected to the FPGA and DSP. The DSP processing chip performs the final processing of the radar data. The data processed by the DSP is uploaded to the host computer through the switching chip for display. Traditional radar signal processing and transmission signal transmission methods are mostly point-to-point transmission, that is, the FPGA or DSP chips that need to be transmitted are connected, and data is exchanged through a high-speed interface. Therefore, when multiple FPGAs or DSPs are used for signal transmission, a large number of printed lines need to be designed on the board. After using the switching chip, all processors only need to be connected to the switching chip, and data is exchanged centrally through the switching chip. Under the premise of unchanged transmission efficiency, the hardware overhead is greatly reduced.

[0069] It should be noted that the data routing involved in the switching chip is a common method in the prior art. For example, the existing data routing method can be run in the switching chip. The present utility model does not involve any improvement in software.

[0070] During implementation, the DSP processor chip may be a FT-M6678N DSP chip, which is connected to the switching chip via an SRIO pin.

[0071] During implementation, in order to facilitate wiring, the FPGA chipset, DSP chipset and host computer are electrically connected to the SRIO switch chip through an MVPX connector to achieve high-speed data transmission.

[0072] During implementation, the power supply of other components except the acquisition chip adopts a switching power supply; the power supply adopts SM4644MPY and SM4630AMPV switching power supply chips. SM4644MPY is a four-channel DC / DC step-down regulator that can provide 4A current per output, and can provide 16A current output capacity through parallel connection. SM4630AMPV is a two-channel DC / DC step-down regulator that can provide 18A current per output, and can provide 36A current output capacity through parallel connection. Only these two chips are used in combination to provide the system with a variety of power supplies such as 0.9V, 1.0V, 1.2V, 1.5V, 1.8V, 3.3V, etc. There are few types of power supply chips, which are easy to design and manage, and effectively improve the quality of board design. Filters, tantalum capacitors, magnetic dielectric capacitors, magnetic beads and other components are also used at the output end of the power chip and the power use end of the power supply system to reduce power supply noise and ripple, enhance the ability of the power plane to resist instantaneous current changes in high-speed communication systems, improve the power supply quality in the circuit, and ensure stable operation of the system.

[0073] Those skilled in the art can understand that the programs / software involved in the FPGA in the above embodiments are common methods in the prior art, such as running the existing data transmission method in the FPGA, and the programs / software involved in the DSP are common methods in the prior art, such as running the existing telemetry data processing method in the DSP, and the present utility model does not involve any software improvements. The present utility model only requires that each device with corresponding functions be connected through the connection relationship given in the embodiment of the present utility model, and does not involve any program software improvements. As for the connection method between the hardware devices with corresponding functions, it can be implemented by those skilled in the art using the existing technology, and will not be described in detail here.

[0074] The above description is only a preferred specific implementation manner of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by any technician familiar with the technical field within the technical scope disclosed in the present invention should be included in the protection scope of the present invention.

Claims

1. A high-speed radar signal processing system, characterized in that: include: Radar signal acquisition chipset, FPGA chipset, SRIO switch chip, DSP chipset, signal acquisition power supply circuit and host computer; The radar signal acquisition chipset is communicatively connected with the FPGA chipset; The FPGA chipset, DSP chipset and host computer are all communicatively connected with the SRIO switching chip; The signal acquisition power supply circuit supplies power to the radar signal acquisition chipset.

2. The high-speed radar signal processing system according to claim 1, characterized in that: Each power pin of the switching chip is connected to a first capacitor; the capacitance value of the first capacitor ranges from 0.01uF to 0.1uF.

3. The high-speed radar signal processing system according to claim 2, characterized in that: Among the power pins of the switching chip, a second capacitor is connected to every power pin of a first preset value; the capacitance value of the second capacitor is 1uF.

4. The high-speed radar signal processing system according to claim 2, characterized in that: Among the power pins of the switching chip, a third capacitor is connected to every second preset power pin; the capacitance value of the third capacitor is greater than 10uF.

5. The high-speed radar signal processing system according to claim 1, characterized in that: The FPGA chipset, the DSP chipset and the host computer are electrically connected to the SRIO switching chip via an MVPX high-speed inter-board connector.

6. The high-speed radar signal processing system according to claim 1, characterized in that: Each chip ID configuration pin of the SRIO switch chip is grounded through a first resistor, and each chip ID configuration pin is also connected to a power supply through a second resistor.

7. The high-speed radar signal processing system according to claim 1, characterized in that: The system also includes a configuration chip of the switching chip, and the IO pins of the configuration chip are connected to the reset pin, the IIC configuration clock pin, and the IIC configuration data pin of the SRIO switching chip.

8. The high-speed radar signal processing system according to claim 1, characterized in that: The high-speed radar signal processing system further includes a clock circuit; the clock circuit includes a clock chip and a clock buffer, and the output pin of the clock chip is connected to the input pin of the clock buffer; The clock pin of each high-speed ADC converter is connected to the clock output pin of the clock buffer.

9. The high-speed radar signal processing system according to claim 1, characterized in that: The signal acquisition power supply circuit includes four LDO power supply chips, each of which includes an enable pin. The enable pin EN of the LDO power supply chip is grounded through a resistor R209; the enable pin EN of the LDO power supply chip is also connected to an IO pin of the FPGA chip.

10. The high-speed radar signal processing system according to claim 1, characterized in that: The radar signal acquisition chipset, FPGA chipset, SRIO switching chip, DSP chipset, and signal acquisition power supply circuit of the high-speed radar signal processing system are arranged on multiple PCB boards, and the multiple PCB boards are in a stacked structure; Both adjacent sides of the plane layer where the signal lines and data lines of the high-speed radar signal processing system are located are ground layers; The vias on the PCB board for signal connections between the radar signal acquisition chipset and the FPGA chipset are back-drilled vias, and non-functional pads are removed.

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