Package structure

Abstract

The utility model provides a packaging structure, comprising an interposer comprising a connection structure and an electrostatic discharge protection device; the chip module comprises a first chip and a second chip, and the first chip and the second chip are arranged on one side of the intermediate layer and are mutually connected through the connecting structure; wherein the electrostatic discharge protection device is electrically connected with the first chip through the connecting structure and is configured to perform electrostatic discharge protection on the first chip. According to the packaging structure, effective electrostatic discharge protection can be carried out on the chip, meanwhile, the area of the chip is reduced, the design and manufacturing flexibility of the electrostatic discharge protection device is improved, and the design and manufacturing cost of the chip can be reduced.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to the field of semiconductor packaging technology, and in particular to a packaging structure. Background Art

[0002] With the continuous development of integrated circuit technology, the integration of devices in the chip continues to increase, which makes semiconductor devices more sensitive to electrostatic discharge (ESD). ESD may generate extremely high voltage and transient current, which may cause permanent damage to semiconductor devices or degrade their performance. In addition to semiconductor devices, ESD protection circuits may also be provided in the chip to protect the semiconductor devices in the chip from damage by ESD. Utility Model Content

[0003] According to at least one embodiment of the present disclosure, a packaging structure is provided, comprising: an interposer, comprising a connection structure and an electrostatic discharge protection device; a chip module, comprising a first chip and a second chip, which are arranged on one side of the interposer and interconnected with each other through the connection structure; wherein the electrostatic discharge protection device is electrically connected to the first chip through the connection structure and is configured to perform electrostatic discharge protection on the first chip.

[0004] In the packaging structure provided according to at least one embodiment of the present disclosure, the connection structure includes a first interconnection part and a second interconnection part; the first interconnection part provides at least partial interconnection between the first chip and the second chip; and the second interconnection part provides an electrical connection between the electrostatic discharge protection device and the integrated circuit module of the first chip.

[0005] In the packaging structure provided according to at least one embodiment of the present disclosure, the first interconnection portion and the second interconnection portion are electrically isolated from each other.

[0006] In the packaging structure provided according to at least one embodiment of the present disclosure, the interposer further includes a semiconductor substrate, the first interconnection portion and the second interconnection portion are located on one side of the semiconductor substrate, and at least a portion of the electrostatic discharge protection device is embedded in the semiconductor substrate.

[0007] In the packaging structure provided according to at least one embodiment of the present disclosure, the electrostatic discharge protection device includes a diode, and the diode includes a PN junction formed by a P-type doping region and an N-type doping region embedded in the semiconductor substrate.

[0008] In the packaging structure provided according to at least one embodiment of the present disclosure, the orthographic projection of the second interconnection part on the semiconductor substrate overlaps with the orthographic projection of the electrostatic discharge protection device on the semiconductor substrate; and the orthographic projection of the first interconnection part on the semiconductor substrate and the orthographic projection of the second interconnection part on the semiconductor substrate are offset from or partially overlap with each other.

[0009] In the packaging structure provided according to at least one embodiment of the present disclosure, the first chip does not include an electrostatic discharge protection device; or the first chip includes an additional electrostatic discharge protection device, and the electrostatic discharge protection device and the additional electrostatic discharge protection device together constitute an electrostatic discharge protection module of the first chip.

[0010] In the packaging structure provided according to at least one embodiment of the present disclosure, the interposer is an organic interposer and includes: an organic body, including an organic dielectric structure and a conductive structure; and a bridge chip, embedded in the organic dielectric structure, and including a semiconductor substrate, a first interconnection structure and the electrostatic discharge protection device, wherein the first interconnection structure is located on one side of the semiconductor substrate, and at least a portion of the electrostatic discharge protection device is embedded in the semiconductor substrate; wherein the first interconnection structure of the bridge chip and the conductive structure of the organic body together constitute the connection structure of the interposer.

[0011] In the packaging structure provided according to at least one embodiment of the present disclosure, the organic dielectric structure includes: an encapsulation layer, which at least encapsulates the side wall of the bridge chip; a first organic dielectric layer, which is located on the side of the encapsulation layer and the bridge chip close to the chip module; and a second organic dielectric layer, which is located on the side of the encapsulation layer and the bridge chip away from the chip module; the conductive structure includes: a conductive column, which is located on the side of the bridge chip and is encapsulated by the encapsulation layer; a first redistribution layer, which is embedded in the first organic dielectric layer and is electrically connected to the chip module, the conductive column and the bridge chip; and a second redistribution layer, which is embedded in the second organic dielectric layer and is electrically connected to the conductive column.

[0012] In the packaging structure provided according to at least one embodiment of the present disclosure, the interposer is a silicon-based interposer and includes: a silicon substrate; a substrate through-hole extending through the silicon substrate; the electrostatic discharge protection device, at least partially embedded in the silicon substrate; and a second interconnect structure, located on a side of the silicon substrate close to the chip module and electrically connected to the chip module, the substrate through-hole and the electrostatic discharge protection device, the second interconnect structure serving as the connection structure.

[0013] In the packaging structure provided according to at least one embodiment of the present disclosure, the first chip is a logic chip, and the second chip is a memory chip.

[0014] The packaging structure provided according to at least one embodiment of the present disclosure also includes: a conductive bump, which is arranged between the chip module and the intermediary layer to provide an electrical connection between the chip module and the intermediary layer; and a conductive terminal, which is located on a side of the intermediary layer away from the chip module and is electrically connected to the intermediary layer and the chip module.

[0015] The packaging structure provided according to at least one embodiment of the present disclosure further includes: a packaging substrate, which is arranged on a side of the interposer away from the chip module and is electrically connected to the interposer through the conductive terminals.

[0016] The packaging structure provided according to at least one embodiment of the present disclosure can reduce the chip area while effectively protecting the chip from electrostatic discharge, improve the flexibility of designing and manufacturing the electrostatic discharge protection device, and reduce the design and manufacturing cost of the chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present disclosure, but are not intended to limit the present disclosure.

[0018] Figure 1 A schematic cross-sectional view showing a package structure according to some embodiments of the present disclosure is shown.

[0019] Figure 2 A schematic cross-sectional view showing a more specific structure of a package structure according to some embodiments of the present disclosure.

[0020] Figure 3 A schematic cross-sectional view showing a bridge chip in a package structure according to some embodiments of the present disclosure.

[0021] Figure 4 A schematic diagram of circuit connections between a chip module and an interposer according to some embodiments of the present disclosure is shown.

[0022] Figure 5 Schematic cross-sectional views of package structures according to other embodiments of the present disclosure are shown.

[0023] Figure 6 A schematic enlarged cross-sectional view showing a second chip in a chip module of a packaging structure according to some embodiments of the present disclosure.

[0024] Figures 7 to 10 Schematic cross-sectional views showing intermediate structures of various steps in a manufacturing process of a bridge chip of a package structure according to some embodiments of the present disclosure.

[0025] Fig.11Schematic cross-sectional views of package structures according to still other embodiments of the present disclosure are shown. DETAILED DESCRIPTION

[0026] In order to make the purpose, technical solution and advantages of the embodiments of the present disclosure clearer, the technical solution of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0027] Unless otherwise defined, the technical terms or scientific terms used in the present disclosure should be understood by people with ordinary skills in the field to which the present disclosure belongs. "First", "second" and similar words used in the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. "Include" or "comprise" and similar words mean that the elements or objects appearing before the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Connect" or "connected" and similar words are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect.

[0028] In semiconductor packaging technology, multiple chips can be packaged to achieve chip protection, physical and / or electrical connection, etc. Multiple chips can be integrated together through packaging technology; for example, logic chips such as system on chip (SoC) and memory chips can be integrated together to achieve high-performance computing.

[0029] Generally speaking, each functional chip is provided with an ESD protection circuit, that is, the functional chip includes a functional circuit for realizing its chip function and an ESD protection circuit to protect the semiconductor devices in the chip from damage by ESD.

[0030] For example, for a logic chip such as a system chip, a logic circuit and an ESD protection circuit are set in the chip, but the ESD protection circuit will occupy a certain chip area (for example, the area in the direction parallel to the main surface of the chip). Moreover, with the continuous reduction of process nodes, for example, the semiconductor devices that constitute the chip functional circuit have developed from complementary metal oxide semiconductor (CMOS) transistors to fin field-effect transistors (FinFET), the characteristic size of semiconductor devices has continued to decrease, the device integration in the chip has continued to increase, and the internal structure of the chip has become more compact, which makes the semiconductor devices in the functional circuit more sensitive and fragile to ESD, and thus it is necessary to set the devices of the ESD protection circuit (for example, clamps, diodes, etc.) larger to effectively protect the semiconductor devices in the chip functional circuit from ESD. However, this will lead to a further increase in the area of ​​the chip, and may further increase the complexity and cost of chip design and manufacturing.

[0031] In this regard, the embodiments of the present disclosure provide a packaging structure that can provide effective ESD protection for the chip while reducing the chip area, improving the flexibility of designing and manufacturing the ESD protection device, and reducing the design and manufacturing costs of the chip.

[0032] For example, an embodiment of the present disclosure provides a packaging structure, including: an interposer, including a connection structure and an electrostatic discharge protection device; a chip module, including a first chip and a second chip, which are arranged on one side of the interposer and interconnected with each other through the connection structure; wherein the electrostatic discharge protection device is electrically connected to the first chip through the connection structure, and is configured to perform electrostatic discharge protection on the first chip.

[0033] In the embodiment of the present disclosure, by setting the electrostatic discharge protection device in the interposer and electrically connecting it to the first chip, the occupied area of ​​the ESD protection module for electrostatic discharge protection of the first chip in the first chip can be reduced, thereby reducing the chip area. Moreover, the ESD protection device is set in the interposer and is not limited by the process node of the first chip, thereby improving the flexibility of the design and manufacture of the ESD protection device and reducing the design and manufacturing cost of the first chip.

[0034] Figure 1 A schematic cross-sectional view showing a package structure according to some embodiments of the present disclosure is shown.

[0035] refer to Figure 1In some embodiments, the package structure 500 includes a chip module 100, a conductive bump 120, an interposer 200, and a conductive terminal 300. The interposer 200 includes a connection structure 201 and an electrostatic discharge protection device 202. The chip module 100 includes a plurality of chips, for example, a first chip 101 and a second chip 102. The plurality of chips of the chip module 100 are arranged on one side of the interposer 200, and are interconnected with each other through the connection structure 201 of the interposer 200. One or more electrostatic discharge protection devices 202 may be provided in the interposer 200, and the electrostatic discharge protection device 202 is electrically connected to at least some of the chips in the chip module 100 through the connection structure 201, and is configured to provide electrostatic discharge protection to the at least some of the chips. For example, the at least some of the chips may be or include the first chip 101.

[0036] In some embodiments, the connection structure includes a first interconnection portion and a second interconnection portion; the first interconnection portion provides at least partial interconnection between the first chip and the second chip; the second interconnection portion provides electrical connection between the electrostatic discharge protection device and the first chip. For example, the first interconnection portion and the second interconnection portion may be electrically isolated from each other.

[0037] In some embodiments, the interposer further includes a semiconductor substrate, the first interconnect portion and the second interconnect portion are located on one side of the semiconductor substrate, and at least a portion of the electrostatic discharge protection device is embedded in the semiconductor substrate.

[0038] In some embodiments, the electrostatic discharge protection device includes a diode, and the diode includes a PN junction formed by a P-type doped region and an N-type doped region embedded in the semiconductor substrate.

[0039] In some embodiments, the orthographic projection of the first interconnection portion on the semiconductor substrate overlaps with the orthographic projection of the electrostatic discharge protection device on the semiconductor substrate; the orthographic projection of the first interconnection portion on the semiconductor substrate and the orthographic projection of the second interconnection portion on the semiconductor substrate are offset from or partially overlap with each other.

[0040] It should be understood that Figure 1 The interposer 200 shown in FIG. 2 only schematically shows that the interposer includes an electrostatic discharge protection device 202 and a connection structure 201, and specifically shows all components of the interposer 200. For a more specific structure of the interposer 200, refer to the following Figure 2 and Figure 5 Embodiment of the invention.

[0041] By providing an electrostatic discharge protection device in the interposer and electrically connecting the electrostatic discharge protection device to the first chip, the electrostatic discharge protection device can provide electrostatic discharge protection to the first chip. In some embodiments, the first chip may not include an electrostatic discharge protection device; or, the first chip may include an additional electrostatic discharge protection device (not shown), and the additional electrostatic discharge protection device and the electrostatic discharge protection device in the interposer together constitute an electrostatic discharge protection module of the first chip to provide electrostatic discharge protection to the first chip 101. That is, the electrostatic discharge protection module of the first chip 101 can be moved as a whole to the interposer, so that no electrostatic discharge protection device is provided in the first chip 101; or, the electrostatic discharge protection module of the first chip 101 can be partially moved to the interposer, so that part of the electrostatic discharge protection module (for example, the electrostatic discharge protection device 202) is located in the interposer, and another part of the electrostatic discharge protection module is located in the first chip 101; different parts of the electrostatic discharge protection module located in the first chip and the interposer can also be connected to each other through the connection structure of the interposer (for example, including the first interconnection part).

[0042] In some embodiments, the interposer may be an organic interposer including a bridge chip or a silicon-based interposer. When the interposer is an organic interposer including a bridge chip, the electrostatic discharge protection device may be disposed in the bridge chip (e.g., its chip substrate); when the interposer is a silicon-based interposer, the electrostatic discharge protection device may be embedded in the substrate of the silicon-based interposer.

[0043] Generally speaking, the bridge chip and the silicon-based interposer are formed by a chip manufacturing process and include a semiconductor substrate and an interconnection structure. The electrostatic discharge protection device can be embedded in the semiconductor substrate, and the conductive connection structure between the electrostatic discharge protection device and the first chip can be integrated with the formation process of the interconnection structure, that is, formed by the same patterning process. In this way, the substrate utilization rate of the interposer components such as the bridge chip and the silicon-based interposer can be improved, so that the interposer has the function of realizing the chip-to-chip interconnection of the chip module and also realizing the ESD protection of the chip module.

[0044] For example, in some embodiments, the interposer is an organic interposer and includes: an organic body, including an organic dielectric structure and a conductive structure; and a bridge chip, embedded in the organic dielectric structure, and including a semiconductor substrate, a first interconnection structure and the electrostatic discharge protection device, the first interconnection structure is located on one side of the semiconductor substrate, and at least part of the electrostatic discharge protection device is embedded in the semiconductor substrate; wherein the first interconnection structure of the bridge chip and the conductive structure of the organic body together constitute the connection structure of the interposer.

[0045] In some embodiments, the organic dielectric structure includes: an encapsulation layer, encapsulating at least the side wall of the bridge chip; a first organic dielectric layer, located on the side of the encapsulation layer and the bridge chip close to the chip module; and a second organic dielectric layer, located on the side of the encapsulation layer and the bridge chip away from the chip module. The conductive structure includes: a conductive column, located on the side of the bridge chip and encapsulated by the encapsulation layer; a first redistribution layer, embedded in the first organic dielectric layer, and electrically connected to the chip module, the conductive column and the bridge chip; and a second redistribution layer, embedded in the second organic dielectric layer, and electrically connected to the conductive column.

[0046] Figure 2 A schematic cross-sectional view of a package structure according to some embodiments of the present disclosure is shown, which shows a more specific structure of an interposer.

[0047] refer to Figure 2 , the package structure 500 includes a chip module 100 and an interposer 200. In some embodiments, the interposer 200 may be an organic interposer, and includes a bridge chip 210 and an organic body, the bridge chip 210 is embedded in the organic body, and includes an electrostatic discharge protection device 202 and an interconnection structure. The organic body encapsulation layer 211, the conductive pillar 212, the first rewiring structure 220 and the second rewiring structure 230. For example, a plurality of conductive pillars 212 are located on the side of the bridge chip 210 and are spaced apart from each other; the encapsulation layer 211 encapsulates the sidewalls of the bridge chip 210 and the plurality of conductive pillars 212.

[0048] The first rewiring structure 220 and the second rewiring structure 230 are located on opposite sides of the bridge chip 210 in a direction perpendicular to the main surface of the chip module. For example, the first rewiring structure 220 is located on a side of the bridge chip 210 and the encapsulation layer 211 close to the chip module 100, and includes a first organic dielectric layer 221 and a first rewiring layer 222; the second rewiring structure 230 is located on a side of the bridge chip 210 and the encapsulation layer 211 away from the chip module 100, and includes a second organic dielectric layer 231 and a second rewiring layer 232.

[0049] The encapsulation layer 211, the first organic dielectric layer 221 and the second organic dielectric layer 231 together constitute the organic dielectric structure of the organic body; the conductive pillar 212, the first redistribution layer 222 and the second redistribution layer 232 together constitute the conductive structure of the organic body. In this embodiment, the interconnection structure of the bridge chip 210 and the conductive structure in the organic body together constitute the connection structure of the intermediate layer, that is, corresponding to Figure 1 The connection structure 201 is shown.

[0050] Figure 3 A schematic enlarged cross-sectional view of the bridge chip 210 is shown.

[0051] refer to Figure 2 and Figure 3 , the bridge chip 210 includes a semiconductor substrate 20, an electrostatic discharge protection device 202 and a first interconnect structure 30. The semiconductor substrate 20 includes a semiconductor material such as silicon. In some embodiments, the semiconductor substrate 20 may be a doped semiconductor, for example, a silicon substrate doped with a P-type dopant such as boron. That is, the semiconductor substrate 20 may be a P-type substrate, but the present disclosure is not limited thereto. In an alternative embodiment, the semiconductor substrate 20 may also be an N-type substrate doped with an N-type dopant such as phosphorus or arsenic.

[0052] In some embodiments, the electrostatic discharge protection device 202 includes a diode composed of a PN junction embedded in the semiconductor substrate 20. For example, the electrostatic discharge protection device 202 may include a dual-diode structure, and may include a first diode Dd1 and a second diode Dd2. For example, the first diode Dd1 includes a PN junction composed of a first doping region 24 and a second doping region 25; the second diode Dd2 includes a PN junction composed of a third doping region 26 and a fourth doping region 27. In some examples, the first doping region 24 and the third doping region 26 are P-type doping regions, such as P+ regions; the second doping region 25 and the fourth doping region 27 are N-type doping regions, such as N+ regions.

[0053] For example, a first well region 21 and a second well region 22 are further provided in the semiconductor substrate 20, and the conductivity types of the first well region 21 and the second well region 22 are opposite. For example, the first well region 21 may be a P-type well region, and the second well region 22 may be an N-type well region. The first doping region 24 and the second doping region 25 are located in the first well region 21, and the doping concentrations of the first doping region 24 and the second doping region 25 are greater than the doping concentration of the first well region 21. The third doping region 26 and the fourth doping region 27 are located in the second well region 22, and the doping concentrations of the third doping region 26 and the fourth doping region 27 are greater than the doping concentration of the second well region 22. An isolation structure 23 is also embedded in the semiconductor substrate 20, and the isolation structure 23 is arranged between adjacent doping regions and between adjacent well regions.

[0054] In some embodiments, the first dielectric structure 28 and the first interconnect structure 30 are disposed on one side of the semiconductor substrate 20 , for example, on a side of the semiconductor substrate 20 close to the chip module 100 .

[0055] The first dielectric structure 28 may include a plurality of stacked dielectric layers, and may include inorganic dielectric materials such as silicon oxide, silicon nitride, and silicon oxynitride. The first interconnect structure 30 includes a conductive material, such as a metal material such as copper and titanium. At least a portion of the first interconnect structure 30 is embedded in the first dielectric structure 28, and may include a conductive contact, a multilayer conductive wire, a conductive via, a conductive pad, and the like. The conductive contact is connected to the anode, cathode (e.g., its corresponding doping region), and the like of the diode, and is connected to the conductive wire; the conductive via is located between the conductive wires of adjacent layers to electrically connect the conductive wires of adjacent layers; the conductive pad is located at the top of the interconnect structure, and is electrically connected to the conductive wires, conductive vias, conductive contacts, and the like below, and serves as an external connection point of the bridge chip, for example, for connecting the bridge chip to the chip module.

[0056] In some embodiments, the first interconnection structure 30 includes a first interconnection portion 31 and a second interconnection portion 32, wherein the first interconnection portion 31 provides partial interconnection between the first chip 101 and the second chip 102, and the second interconnection portion 32 provides electrical connection between the electrostatic discharge protection device 202 and the first chip 101. In some embodiments, the conductive pads in the first interconnection portion 31 may also be referred to as interconnection pads, which are used to electrically connect to multiple chips in a chip module; the conductive pads in the second interconnection portion 32 may also be referred to as ESD pads, which are used to electrically connect the electrostatic discharge protection device 202 to some chips (e.g., the first chip) in the chip module.

[0057] In this example, the first interconnection portion 31 includes multiple layers of conductive wires, conductive vias and interconnection pads, but does not include conductive contacts; the second interconnection portion 32 includes multiple layers of conductive wires, conductive vias and ESD pads, and includes conductive contacts for electrical connection between a conductive component located above the conductive contacts in the second interconnection portion and the electrostatic discharge protection device 202.

[0058] For example, the semiconductor substrate 20 has a first region R1 and a second region R2, the second region R2 can be configured as a device region, and the diode of the electrostatic discharge protection device 202 is arranged in the second region R2. No electronic device may be arranged in the first region R1, for example, the region may only include a substrate without active or passive devices. The first region R1 may also be referred to as a blank substrate region. In some embodiments, other regions in the semiconductor substrate 20 except the electrostatic discharge protection device 202 may all be blank substrate regions, that is, no active or passive devices are arranged therein. In other embodiments, passive devices such as capacitors may also be arranged in the first region R1, and the corresponding first interconnection portion may include a conductive contact connected to the passive device, but no active device is arranged in the first region R1.

[0059] In some embodiments, the first interconnection portion 31 is disposed above the first region R1 of the semiconductor substrate 20, and may not extend above the second region R2. For example, the orthographic projection of the first interconnection portion 31 on the semiconductor substrate 20 is located within the first region R1. In other embodiments, the first interconnection portion 31 is located above the first region R1, and may also partially extend above the second region R2. That is, the orthographic projection of the first interconnection portion 31 on the semiconductor substrate 20 is partially located within the first region R1, and may be partially located within the second region R2.

[0060] In some embodiments, the second interconnection portion 32 is disposed above the second region R2 of the semiconductor substrate 20, and the orthographic projection of the second interconnection portion 32 on the main surface of the semiconductor substrate 20 overlaps with the orthographic projection of the electrostatic discharge protection device 202 on the main surface of the semiconductor substrate 20. For example, the conductive components such as the conductive contact and the conductive pad connected to the first diode Dd1 and the second diode Dd2 in the second interconnection portion 32 can also be referred to as part of the electrostatic discharge protection module.

[0061] In some embodiments, the first interconnection portion 31 and the second interconnection portion 32 are spaced apart from each other, for example, they may be electrically isolated from each other. The orthographic projections of the first interconnection portion 31 and the second interconnection portion 32 on the main surface of the semiconductor substrate 20 may be offset from each other, that is, not overlapped; or, the orthographic projections of the first interconnection portion 31 and the second interconnection portion 32 on the main surface of the semiconductor substrate may also partially overlap each other, thereby saving space and reducing the size of the bridge chip.

[0062] Figure 4 The schematic diagram of the circuit connection between the chip module 100 and the interposer 200 is shown schematically. It should be understood that Figure 4 The connection relationship of the corresponding components is briefly shown. The specific structure of the interposer 200 can be referred to Figure 3 .

[0063] refer to Figure 3 and Figure 4 In some embodiments, the interposer 200 provides electrical connections between the first chip 101 and the second chip 102 in the chip module 100, and between the first chip 101 and the electrostatic discharge protection device 202. The first chip 101 includes an integrated circuit module 11; for example, the integrated circuit module 11 may include a logic circuit and may include a plurality of transistors. The electrostatic discharge protection device 202 includes a first diode Dd1 and a second diode Dd2.

[0064] The anode of the first diode Dd1 and the corresponding device in the integrated circuit module 11 are electrically connected to the first end E1; the cathode of the first diode Dd1, the anode of the second diode Dd2 and the corresponding device in the integrated circuit module 11 are electrically connected to the second end E2; the cathode of the second diode Dd2 and the corresponding device in the integrated circuit module 11 are electrically connected to the third end E3. For example, the first end E1 can be a low potential end, such as a VSS end; the second end E2 can be an input / output (I / O) end, such as an interface of the first chip for information exchange between its internal integrated circuit module and a circuit or system outside the chip, such as being used for the first chip to receive signals from the outside, or to send data information in the chip to the outside. The third segment E3 can be a high potential end, such as a VDD end.

[0065] The electrostatic discharge protection device is connected to the integrated circuit module 11 in the first chip 101, so that the integrated circuit module 11 of the first chip 101 can be protected from electrostatic discharge, and the devices in the integrated circuit module 11 are prevented from being damaged by electrostatic discharge. For example, through the above-mentioned ESD protection circuit, when an ESD event occurs, the protection circuit can guide the excessive voltage and current generated by electrostatic discharge to the low potential end (for example, the VSS end) or the high potential end (for example, the VDD end), thereby protecting the devices in the integrated circuit module 11 from damage by electrostatic discharge, thereby ensuring the reliability and stability of the first chip.

[0066] Meanwhile, the ESD protection device 202 is embedded in the interposer 200 , for example, disposed in the bridge chip 210 , which can reduce the occupied area of ​​the ESD protection module in the first chip 101 , thereby reducing the overall size of the first chip 101 .

[0067] It should be understood that Figure 3 and Figure 4 The structure of the ESD protection circuit shown is only an example. The ESD protection circuit may also include other structures or may include other types of ESD protection devices, which is not limited in the present disclosure.

[0068] Continue to refer Figure 4 , the first chip 101 and the second chip 102 are interconnected with each other through a connection circuit IS. The connection circuit IS may be independent of the electrostatic discharge protection circuit.

[0069] refer to Figures 2 to 4In some embodiments, the first doping region 24 and the second doping region 25 of the first diode Dd1 of the electrostatic discharge protection device 202 can be used as the anode and cathode of the first diode Dd1, respectively; the third doping region 26 and the fourth doping region 27 of the second diode Dd2 can be used as the anode and cathode of the second diode Dd2, respectively. In some embodiments, the connection circuit between the electrostatic discharge protection device 202 and the integrated circuit module 11 may include the second interconnection portion 32 in the bridge chip and a portion of the redistribution layer in the first redistribution structure. The connection circuit IS between the first chip and the second chip may include the first interconnection portion 31 in the bridge chip, the first redistribution structure, a portion of the redistribution layer in the second redistribution structure, and the conductive pillar 212.

[0070] refer to Figure 2 In some embodiments, the encapsulation layer 211 encapsulates the sidewalls of the bridge chip 210 and the sidewalls of the plurality of conductive pillars 212. The encapsulation layer 211 may include a molding compound, which may include, for example, an epoxy molding compound (EMC), and may be formed by a molding process. The encapsulation layer 211 may include a main material and a filler; the main material may include an organic material such as epoxy resin; the filler is dispersed in the organic material and may include a semiconductor material, an inorganic insulating material, and the like, such as silicon, aluminum oxide, and the like. The conductive pillars 212 may include a metal material such as copper.

[0071] For example, the first redistribution structure 220 includes a first organic dielectric layer 221 and a first redistribution layer 222; at least a portion of the first redistribution layer 222 is embedded in the first organic dielectric layer 221 and is electrically connected to the chip module 100, the bridge chip 210 and the conductive pillar 212. The second redistribution structure 230 includes a second organic dielectric layer 231 and a second redistribution layer 232; at least a portion of the second redistribution layer 232 is embedded in the second organic dielectric layer 231 and is electrically connected to the conductive pillar 212. That is, the conductive pillar 212 extends through the encapsulation layer 211 and is used to electrically connect the first redistribution layer 222 and the second redistribution layer 232.

[0072] The first organic dielectric layer 221 and the second organic dielectric layer 231 may each include a suitable organic dielectric material, such as a polymer material such as polyimide. The first redistribution layer 222 and the second redistribution layer 232 may include a conductive material, such as a metal material such as copper, and may each include one or more layers of conductive traces and / or conductive vias, and the conductive vias are used to provide electrical connections between conductive lines of different layers, electrical connections between conductive lines and other conductive components, etc. It should be understood that for the sake of simplicity of the drawings, only the conductive traces of each redistribution layer are schematically shown in the figure, and the conductive vias are not shown. The number of layers of the conductive traces shown in the figure is also only for illustrative purposes, and the present disclosure is not limited thereto.

[0073] For example, the first redistribution layer 222 includes a portion for connecting the electrostatic discharge protection device 202 in the bridge chip 210 with the first chip 101, and the portion of the redistribution layer can be electrically connected to the second interconnection portion 32 of the bridge chip; the first redistribution layer 222 also includes a portion for providing interconnection between the first chip 101 and the second chip 102, and the portion of the redistribution layer can be electrically connected to the first interconnection portion 31 of the bridge chip. In some embodiments, the second redistribution layer 232 is used to provide electrical connection between the conductive terminal 300 and the upper component (for example, the chip module 100 and / or the bridge chip 210). In some embodiments, the second redistribution layer 232 can also provide partial interconnection between the first chip 101 and the second chip 102; for example, partial interconnection between the first chip 101 and the second chip 102 can also be achieved through the first redistribution layer 222, the conductive pillar 212 and the second redistribution layer 232.

[0074] Continue to refer Figure 2 In some embodiments, the line width / line spacing of the conductive traces in the redistribution layer is greater than the line width / line spacing of the conductive traces in the bridge chip, that is, the bridge chip has finer wiring. The wiring density in the bridge chip may be greater than the wiring density in the redistribution layer. By using a combination of redistribution layers and bridge chips with different line widths / line spacings, various interconnection requirements between chips can be met. For example, the bridge chip uses fine wiring to meet the high-density interconnection requirements between chips, and the redistribution layer uses conductive traces with larger line widths to improve signal transmission efficiency and reduce signal loss during transmission. In this article, line width refers to the width of the conductive trace in the width direction perpendicular to its extension direction, and line spacing refers to the spacing between adjacent conductive traces in the width direction.

[0075] In some embodiments, the bridge chip 210 and the chip connected thereto in the chip module 100 partially overlap in a direction perpendicular to the main surface of the chip module 100. For example, the orthographic projection of the bridge chip 210 on a reference plane parallel to the main surface of the interposer partially overlaps with the orthographic projection of the first chip 101 on the reference plane, and partially overlaps with the orthographic projection of the second chip 102 on the reference plane. The orthographic projection of the bridge chip 210 on the reference plane is located within the orthographic projection of the first or second rewiring structure on the reference plane, and the area of ​​the orthographic projection of the bridge chip 210 is smaller than the area of ​​the orthographic projection of the first or second rewiring structure. The area of ​​the orthographic projection of the first or second rewiring structure is roughly equivalent to the area of ​​the orthographic projection of the interposer 200 as a whole on the reference plane.

[0076] Figure 5 Schematic cross-sectional views of package structures according to other embodiments of the present disclosure are shown. The package structure of this embodiment is similar to that of the aforementioned embodiment, except that: in the package structure of this embodiment, the interposer is a silicon-based interposer.

[0077] In some embodiments, the interposer includes a silicon substrate; a substrate through-hole extending through the silicon substrate; an electrostatic discharge protection device at least partially embedded in the silicon substrate; and a second interconnect structure located on a side of the silicon substrate close to the chip module and electrically connected to the chip module, the substrate through-hole and the electrostatic discharge protection device, the second interconnect structure serving as the connection structure.

[0078] refer to Figure 5 For example, the interposer 200 includes a substrate 260, a substrate through-hole 261, an electrostatic discharge protection device 202, a second dielectric structure 262, and a second interconnect structure 263. The substrate 260 may be a semiconductor substrate, such as a silicon substrate. The substrate through-hole 261 includes a conductive material, such as a metal material such as copper. The substrate through-hole 261 extends through the substrate 260 and is used to connect the second interconnect structure 263 and the conductive terminal 300.

[0079] The electrostatic discharge protection device 202 is embedded in the substrate 260 and has a structure similar to that of the electrostatic discharge protection device in the aforementioned bridge chip. For example, the electrostatic discharge protection device includes a diode, and the diode includes a PN junction composed of a P-type doping region and an N-type doping region located in the substrate 260. For example, the electrostatic discharge protection device 202 includes a first diode and a second diode, and the first diode and the second diode include PN junctions respectively arranged in different well regions of the substrate 260. The structure of the electrostatic discharge protection device 202 in the substrate 260 is similar to that of the electrostatic discharge protection device 202 in the substrate 260. Figure 3 The above are roughly the same as shown and will not be described again here.

[0080] The second dielectric structure 262 and the second interconnect structure 263 are located on one side of the substrate 260, for example, on the side of the substrate 260 close to the chip module 100. The second dielectric structure 262 may include a plurality of stacked dielectric layers, and include inorganic dielectric materials such as silicon oxide, silicon nitride, and silicon oxynitride. That is, the second dielectric structure 262 may include an inorganic dielectric structure. The second interconnect structure 263 is embedded in the second dielectric structure 262 and is electrically connected to the electrostatic discharge protection device 202 and a plurality of substrate through-holes 261. The second interconnect structure 263 includes a conductive material, for example, a metal material such as copper and titanium. At least a portion of the second interconnect structure 263 is embedded in the second dielectric structure 262, and may include conductive contacts, multi-layer conductive lines, conductive vias, conductive pads, etc. The second interconnect structure 263 and Figure 3 The first interconnect structure 30 of the bridge chip shown has a similar structure, except that the overall size of the substrate 260 and the second interconnect structure 263 in this embodiment is larger. In this embodiment, the second interconnect structure 263 is used as a connecting structure, for example, Figure 1 The connection structure 201 shown realizes the interconnection between multiple chips in the chip module and the electrical connection between the first chip 101 and the electrostatic discharge protection device 202.

[0081] In some embodiments, the second interconnect structure 263 includes a first interconnect portion and a second interconnect portion, the first interconnect portion provides interconnection between the first chip 101 and the second chip 102, and the second interconnect portion provides electrical connection between the electrostatic discharge protection device 202 and the first chip 101. The first interconnect portion and the second interconnect portion may be isolated from each other.

[0082] In this embodiment, the connection circuits of the first chip 101 and the second chip 102 in the chip module 100 and the interposer 200 are Figure 4 For example, Figure 4 The connection circuit IS shown includes Figure 5 The connection circuit between the first chip 101 and the electrostatic discharge protection device 202 may include the second interconnection portion of the second interconnection structure 263 .

[0083] refer to Figures 1 to 5 In some embodiments, the chip module 100 is electrically connected to the interposer 200 through the conductive bump 120. For example, the conductive bump 120 is disposed between the chip module 100 and the interposer 200 to provide electrical connection between each chip of the chip module 100 and the interposer 200. The conductive bump 120 may include a conductive material such as solder, for example, a micro-bump.

[0084] In some embodiments, the conductive terminal 300 is disposed on a side of the interposer 200 away from the chip module 100, and is electrically connected to the interposer 200, and can be electrically connected to the chip module 100 through the interposer 200. The conductive terminal 300 may include a solder ball, for example, or may include a controlled collapsed chip connection (C4) bump. The package structure 500 may be further connected to other package components through the conductive terminal 300.

[0085] In some embodiments, the package structure 500 may further include an additional encapsulation layer 121. The additional encapsulation layer 121 is disposed on a side of the interposer 200 away from the conductive terminal 300, and encapsulates multiple chips of the chip module 100, and may fill the space between the chip module 100 and the interposer 200. For example, multiple chips of the chip module 100 are arranged side by side, and the additional encapsulation layer 121 may at least encapsulate the sidewalls of the multiple chips. Alternatively, the additional encapsulation layer 121 may also encapsulate the surface of the multiple chips away from the side of the interposer. The additional encapsulation layer 121 may be or include a molding compound, such as an epoxy resin molding compound. In some embodiments, the package structure 500 may further include an underfill layer; the underfill layer fills the space between the chip module 100 and the interposer 200 to surround and protect the conductive bumps 120, and may be encapsulated by the molding compound.

[0086] In some embodiments, the number and type of multiple chips of the chip module 100 can be selected according to product requirements; for example, the multiple chips may include a system on chip (SoC), a digital signal processor (DSP) chip, a graphic processing unit (GPU), an application specific integrated circuit (ASIC) chip, a high bandwidth memory chip (HBM) and other memory chips, a central processing unit (CPU), a tensor processing unit (TPU), a neural network processor (NPU), a deep learning processor (DPU), an accelerated processing unit (APU), and a general-purpose graphics processing unit (GPGPU). One or more.

[0087] In some examples, such as Figure 2 and Figure 5 As shown, the chip module 100 includes a first chip and two second chips, and includes two ESD protection devices; for example, Figure 2 In the illustrated embodiment, each bridge chip includes an ESD protection device. However, the present disclosure is not limited thereto. The number of chips in the chip module and the number of ESD protection devices in the interposer can be designed and adjusted according to product requirements, so that the interposer can provide both interconnection and ESD protection functions, and the ESD protection module can provide effective ESD protection for the chip.

[0088] In some embodiments, the first chip is a logic chip, and the second chip is a memory chip. For example, in the chip module 100, the first chip 101 may be a SoC chip, and the second chip 102 may be an HBM chip, and include a plurality of sub-chips stacked on each other. In some embodiments, at least part of the ESD protection module of the SoC chip is moved to the interposer, and the ESD protection module of the HBM chip may be set in its chip stacking structure.

[0089] Figure 6 A schematic enlarged cross-sectional view of a second chip according to some embodiments of the present disclosure is shown.

[0090] refer to Figure 6 In some embodiments, the second chip 102 may be an HBM chip and include a plurality of sub-chips 12 stacked in a direction perpendicular to the main surface of the chip. The plurality of sub-chips may include memory chips, and some of the sub-chips may include electrostatic discharge protection devices to provide ESD protection for functional circuit devices in the second chip. Since the HBM chip is a chip stacking structure, the electrostatic discharge protection device is disposed in the chip stacking structure without substantially increasing the area of ​​the HBM chip in a direction parallel to the main surface of the chip.

[0091] Figures 7 to 11 A schematic cross-sectional view showing a method for manufacturing a bridge chip according to some embodiments of the present disclosure.

[0092] refer to Figure 7 In some embodiments, a semiconductor substrate 20 is provided, and then corresponding well regions and doping regions can be formed in the semiconductor substrate through a doping process such as a diffusion process and an ion implantation process. Before the doping process is performed, a patterned mask layer can be formed on the semiconductor substrate 20 through a photolithography process, so that the doping process can be performed in a specific area of ​​the semiconductor substrate. Afterwards, an isolation structure 23 is formed in the semiconductor substrate; for example, the isolation structure 23 can be a shallow trench isolation (STI) structure, and includes an insulating structure located in a trench of the semiconductor substrate.

[0093] refer to Figure 8 and Fig. 9 , a dielectric layer 18 is formed on a semiconductor substrate 20, and a conductive contact 19 is formed in the dielectric layer 18, wherein the conductive contact 19 is connected to a doped region of a corresponding diode.

[0094] refer to Fig. 9 and Fig.10, and then repeat the process of forming the dielectric layer and forming the conductive structure (conductive wire / conductive via) to complete the process of forming the first dielectric structure 28 and the first interconnection structure 30. The first dielectric structure 28 includes a dielectric layer 18 and other dielectric layers located on the dielectric layer 18; the first interconnection structure 30 includes a conductive contact 19 and other conductive wires / conductive vias, conductive pads and other conductive components located above the conductive contact 19. In some embodiments, the conductive components in the first interconnection structure 30 can be formed by a damascene process; for example, the conductive wires and conductive vias can be formed by a dual-damascene process. In the process of forming the first interconnection structure 30, the first interconnection part 31 and the second interconnection part 32 located in the same layer can be formed by the same patterning process. The embodiment of the present disclosure integrates the ESD protection device and the connection circuit of the ESD protection module and the interconnection circuit between the chips of the chip module, for example, all of which are integrated in a bridge chip. For example, the bridge chip of the embodiment of the present disclosure can be called a hybrid embedded bridge chip. The bridge chip can not only realize the interconnection between chips in the chip module, but also provide ESD protection for the chips in the chip module.

[0095] In some embodiments, Figure 5 The formation process of the silicon-based interposer shown in FIG. Figures 7 to 10 Similar to that shown.

[0096] In the manufacturing process of the embodiment of the present disclosure, the electrostatic discharge protection device and the corresponding interconnection part in the electrostatic discharge protection module are arranged in the bridge chip of the interposer or in the silicon-based interposer, so that the manufacturing process of the part of the electrostatic discharge protection module located in the interposer is independent of the manufacturing process of the functional chip. Therefore, the manufacture of this part of the electrostatic discharge protection module is not subject to the restrictions of the process nodes and design rules of the functional chip (for example, the first chip), thereby having higher design and manufacturing flexibility and reducing design and manufacturing costs.

[0097] Fig.11 Schematic cross-sectional views of package structures according to other embodiments of the present disclosure are shown.

[0098] In some embodiments, the packaging structure further includes: a packaging substrate, which is disposed on a side of the interposer away from the chip module and is electrically connected to the interposer through a conductive terminal.

[0099] refer to Fig.11For example, the package structure 500 further includes a package substrate 320, which is disposed on a side of the interposer 200 away from the chip module 100 and is electrically connected to the interposer 200 through the conductive terminal 300, and further electrically connected to the chip module 100 through the interposer 200. For example, the package substrate 320 may be a printed circuit board (PCB). Fig.11 The intermediate layer in Figure 2 The organic interposer shown may be Figure 5 The silicon-based interposer shown.

[0100] In various embodiments of the present disclosure, by disposing at least part of the electrostatic discharge protection module of the functional chip in the chip module in the interposer, the size of the functional chip can be reduced while effectively protecting the functional chip from ESD, and the footprint of the functional chip in the package structure can be reduced, thereby reducing the package size. Moreover, the design and manufacturing costs of the chip can be reduced.

[0101] There are a few points to note:

[0102] (1) In the drawings of the embodiments of the present disclosure, only the structures related to the embodiments of the present disclosure are involved, and other structures can refer to the general design.

[0103] (2) Unless there is a conflict, the features of the same embodiment or different embodiments of the present disclosure may be combined with each other.

[0104] The above are only specific embodiments of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present disclosure, which should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Claims

1. A packaging structure, characterized in that: include: an interposer including a connection structure and an electrostatic discharge protection device; A chip module, comprising a first chip and a second chip, which are arranged on one side of the interposer and interconnected with each other through the connection structure; The electrostatic discharge protection device is electrically connected to the first chip through the connection structure, and is configured to perform electrostatic discharge protection on the first chip.

2. The packaging structure according to claim 1, characterized in that: The connection structure includes a first interconnection portion and a second interconnection portion; The first interconnect portion provides at least a portion of interconnection between the first chip and the second chip; and The second interconnection portion provides an electrical connection between the electrostatic discharge protection device and the integrated circuit module of the first chip.

3. The packaging structure according to claim 2, characterized in that: The first interconnect portion and the second interconnect portion are electrically isolated from each other.

4. The packaging structure according to claim 2, characterized in that: The interposer further includes a semiconductor substrate, the first interconnection portion and the second interconnection portion are located on one side of the semiconductor substrate, and at least a portion of the electrostatic discharge protection device is embedded in the semiconductor substrate.

5. The packaging structure according to claim 4, characterized in that: The electrostatic discharge protection device comprises a diode, and the diode comprises a PN junction formed by a P-type doping region and an N-type doping region embedded in the semiconductor substrate.

6. The packaging structure according to claim 4, characterized in that: The orthographic projection of the second interconnection portion on the semiconductor substrate overlaps with the orthographic projection of the electrostatic discharge protection device on the semiconductor substrate; as well as An orthographic projection of the first interconnection portion on the semiconductor substrate and an orthographic projection of the second interconnection portion on the semiconductor substrate are offset from or partially overlapped with each other.

7. The packaging structure according to claim 1, characterized in that: The first chip does not include an electrostatic discharge protection device; or The first chip includes an additional electrostatic discharge protection device, and the electrostatic discharge protection device and the additional electrostatic discharge protection device together constitute an electrostatic discharge protection module of the first chip.

8. The packaging structure according to claim 1, characterized in that: The interposer is an organic interposer and includes: Organic hosts, including organic dielectric and conductive structures; and A bridge chip, embedded in the organic dielectric structure, comprising a semiconductor substrate, a first interconnect structure and the electrostatic discharge protection device, wherein the first interconnect structure is located on one side of the semiconductor substrate, and at least a portion of the electrostatic discharge protection device is embedded in the semiconductor substrate; The first interconnect structure of the bridge chip and the conductive structure of the organic body together constitute the connection structure of the intermediate layer.

9. The packaging structure according to claim 8, characterized in that: The organic dielectric structure comprises: An encapsulation layer, encapsulating at least the side wall of the bridge chip; A first organic dielectric layer is located on a side of the encapsulation layer and the bridge chip close to the chip module; and A second organic dielectric layer is located on a side of the encapsulation layer and the bridge chip away from the chip module; The conductive structure comprises: A conductive column, located at a side of the bridge chip and encapsulated by the encapsulation layer; a first redistribution layer, embedded in the first organic dielectric layer and electrically connected to the chip module, the conductive pillars and the bridge chip; and The second redistribution layer is embedded in the second organic dielectric layer and electrically connected to the conductive column.

10. The packaging structure according to claim 1, characterized in that: The interposer is a silicon-based interposer and includes: Silicon substrate; a substrate through-hole extending through the silicon substrate; The electrostatic discharge protection device is at least partially embedded in the silicon substrate; and The second interconnect structure is located on a side of the silicon substrate close to the chip module and is electrically connected to the chip module, the substrate through hole and the electrostatic discharge protection device. The second interconnect structure is used as the connection structure.

11. The packaging structure according to any one of claims 1 to 10, characterized in that: The first chip is a logic chip, and the second chip is a memory chip.

12. The packaging structure according to any one of claims 1 to 10, characterized in that: Also includes: A conductive bump is disposed between the chip module and the interposer to provide an electrical connection between the chip module and the interposer; as well as The conductive terminal is located on a side of the intermediary layer away from the chip module and is electrically connected to the intermediary layer and the chip module.

13. The packaging structure according to claim 12, characterized in that: Also includes: The packaging substrate is arranged on a side of the intermediary layer away from the chip module and is electrically connected to the intermediary layer through the conductive terminals.

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