Satellite-borne phased-array antenna beam control system

Abstract

The utility model provides a satellite-borne phased-array antenna beam control system, which is characterized in that a beam controller is respectively connected with a plurality of T / R assemblies through a plurality of control links, and each T / R assembly is correspondingly connected with an antenna; each control link is provided with a phased array radar chip and a plurality of control chips, the beam controller transmits signals to the control chips, the control chips output differential signals to the phased array radar chips, and after beam modulation is carried out by the phased array radar chips, the modulated beam signals are sent to the T / R assembly; the T / R assembly receives echo signals of the antenna and sends the echo signals to the phased array radar chip through the control chip, and the phased array radar chip carries out data demodulation on the received signals and transmits the demodulated data back to the beam controller. According to the utility model, a single T / R assembly and a plurality of T / R assemblies of the control system can be selectively controlled by means of the beam controller, so that a more flexible control mode is achieved.

Description

Technical Field

[0001] The utility model belongs to the technical field of phased array antenna systems, and in particular relates to a satellite-borne phased array antenna beam control system. Background Art

[0002] The active phased array antenna system mainly includes radiation units, beam controllers, and T / R components. The working principle of the phased array radar is to control the phase shifter through an electronic computer to change the phase relationship between the currents of each radiation unit on the antenna aperture to achieve beam scanning in space, that is, electronic scanning. This technology allows the scanning of the beam (including the amplitude and phase of the power radiation) to be controlled by the T / R component, thereby achieving fast and precise pointing of the beam.

[0003] The working principle of the beam control system is to generate different codes according to different modes to achieve beam control. Its main task is to quickly calculate the phase shift value of each antenna unit, calculate it according to the requirements of beam pointing, and then send it to the T / R component to complete the beam change.

[0004] The design of traditional beam control systems has certain defects. When faced with multiple or even more complex antenna systems, the clock signals that control the T / R components often have asynchrony problems, which will cause the generated beams to be asynchronous and ultimately fail to achieve the expected functions. In addition, other designs will also use a unified chip select control signal to control the T / R components to start working at the same time to achieve consistent beam generation. However, such a design has certain defects. In a complex phased array antenna system, a large number of wire harnesses will be used in this way, and when there are M T / R components, M chip select signals are required. Such a design is very resource-intensive. Utility Model Content

[0005] In view of this, the present invention aims to provide a satellite-borne phased array antenna beam control system to solve at least one of the above problems.

[0006] In order to achieve the above object, the technical solution of the utility model is implemented as follows:

[0007] The utility model provides a satellite-borne phased array antenna beam control system, comprising a beam controller FPGA, a plurality of T / R components and an antenna, wherein the beam controller FPGA is respectively connected to the plurality of T / R components through a plurality of control links, and each of the T / R components is correspondingly connected to the antenna;

[0008] Each control link is equipped with a phased array radar chip and multiple control chips.

[0009] The beam controller FPGA transmits a signal to the control chip, and the control chip outputs a differential signal to the phased array radar chip. After the phased array radar chip performs beam modulation, the modulated beam signal is sent to the T / R component;

[0010] The T / R component receives the echo signal of the antenna, and sends the echo signal to the phased array radar chip through the control chip. The phased array radar chip demodulates the received signal and transmits the demodulated data back to the beam controller FPGA.

[0011] Furthermore, a control circuit is formed by connecting the control chip, wherein the beam controller FPGA is connected to the phased array radar chip through two connected control circuits, and the phased array radar chip is connected to the T / R component through one control circuit.

[0012] Furthermore, the control circuit comprises:

[0013] The first pin of the control chip is connected to a first resistor, the first resistor is connected to the beam controller FPGA or the phased array radar chip, and the second pin, the third pin and the fourth pin of the control chip are connected to the beam controller FPGA or the phased array radar chip through a transistor switch circuit;

[0014] The fifth pin of the control chip is grounded, the sixth pin and the seventh pin thereof are connected to the T / R component or to a diode element of another control circuit provided on the phased array radar chip through a diode element, the sixth pin thereof is connected to a 3.3V power supply through a fifth resistor, the seventh pin thereof is grounded through a fourth resistor, and the eighth pin thereof is connected to a 3.3V power supply through a first capacitor.

[0015] Furthermore, the control chip adopts the SSP485 model chip, and the phased array radar chip adopts the ADAR1000 model chip.

[0016] Furthermore, the transistor is an NPN transistor.

[0017] Furthermore, the diode element adopts an electrostatic protection diode.

[0018] Compared with the prior art, the satellite-borne phased array antenna beam control system described in the utility model has the following beneficial effects:

[0019] The satellite-borne phased array antenna beam control system described in the utility model can selectively control a single T / R component or multiple T / R components of the control system with the help of a beam controller FPGA, thereby achieving a more flexible control method. Even if individual units in the antenna system are damaged, other components can still work normally. At the same time, the system has fewer wiring harnesses, is simple as a whole, and occupies fewer resources. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] The accompanying drawings constituting a part of the present invention are used to provide a further understanding of the present invention. The illustrative embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation on the present invention. In the accompanying drawings:

[0021] Figure 1 A link relationship diagram of a satellite-borne phased array antenna beam control system according to an embodiment of the utility model;

[0022] Figure 2 A specific circuit connection diagram of a satellite-borne phased array antenna beam control system according to an embodiment of the utility model;

[0023] Figure 3 The signal control logic diagram described in the embodiment of the utility model;

[0024] Figure 4 This is a functional block diagram of the SSP485 chip described in an embodiment of the present utility model. DETAILED DESCRIPTION

[0025] It should be noted that, in the absence of conflict, the embodiments of the present invention and the features in the embodiments can be combined with each other.

[0026] The present invention will be described in detail below with reference to the accompanying drawings and in combination with embodiments.

[0027] See also Figure 1 and Figure 2 As shown, this embodiment provides a satellite-borne phased array antenna beam control system, including a beam controller FPGA, a plurality of T / R components and an antenna, wherein the beam controller FPGA is connected to the plurality of T / R components through a plurality of control links, and each T / R component is connected to an antenna correspondingly;

[0028] Each control link is equipped with a phased array radar chip and multiple control chips.

[0029] The beam controller FPGA transmits a signal to the control chip, and the control chip outputs a differential signal to the phased array radar chip. After the phased array radar chip performs beam modulation, the modulated beam signal is sent to the T / R component.

[0030] The T / R component receives the echo signal from the antenna and sends the echo signal to the phased array radar chip through the control chip. The phased array radar chip demodulates the received signal and transmits the demodulated data back to the beam controller FPGA.

[0031] Specifically, in this embodiment, all control signals are independently designed and connected to a number of T / R components through multiple control links composed of a phased array radar chip and a control chip, and each T / R component is connected to an antenna; when one group of signals fails, only one T / R component is affected, and other subsystems are not affected.

[0032] The FPGA chip transmits a signal to the control chip, and the control chip outputs a differential signal after receiving the signal. Therefore, the signal link of the entire system has high reliability and independence.

[0033] like Figure 3 As shown, the beam controller FPGA sends and receives data to the phased array radar chip according to the asynchronous serial port protocol. After receiving the data from the beam controller FPGA, the phased array radar chip performs beam modulation and sends the adjusted beam signal to the T / R component.

[0034] After the T / R component receives the feedback signal from the antenna, it sends the signal to the phased array radar chip through the control chip. After receiving the signal, the phased array radar chip performs I and Q demodulation operations and finally sends the data to the beam controller FPGA.

[0035] In addition, the beam controller in the control system is connected to the satellite platform via the CAN bus. Each T / R component is independently controlled by the control chip, and communication is transmitted through asynchronous serial port communication. Compared with traditional SPI communication, asynchronous serial port is more flexible.

[0036] The control system described in this embodiment can selectively control a single T / R component or multiple T / R components of the control system with the help of the beam controller FPGA, thereby achieving a more flexible control method. Even if individual units in the antenna system are damaged, other components can still work normally. At the same time, the system has fewer wiring harnesses, is simple as a whole, and occupies fewer resources.

[0037] In some embodiments, a control circuit is formed by connecting the control chip, wherein the beam controller FPGA is connected to the phased array radar chip through two connected control circuits, and the phased array radar chip is connected to the T / R component through a control circuit. The control circuit includes:

[0038] The first pin of the control chip is connected to the first resistor, the first resistor is connected to the beam controller FPGA or the phased array radar chip, and the second pin, the third pin and the fourth pin of the control chip are connected to the beam controller FPGA or the phased array radar chip through a transistor switch circuit;

[0039] The fifth pin of the control chip is grounded, the sixth pin and the seventh pin thereof are connected to the T / R component or the diode element of another control circuit provided on the phased array radar chip through a diode element, the sixth pin thereof is connected to the 3.3V power supply through a fifth resistor, the seventh pin thereof is grounded through a fourth resistor, and the eighth pin thereof is connected to the 3.3V power supply through a first capacitor.

[0040] Specifically, in this embodiment, Figure 4 As shown, the control chip model is SSP485 chip, which supports RS-485 / RS-422 communication and is a high-speed transceiver for half-duplex communication. It has a fail-safe circuit and a low slew rate characteristic, which can reduce EMI and reflection interference caused by inappropriate terminal matching impedance.

[0041] R0 is the output terminal: if AB≥0.05V, R0 is high level; if AB≤0.2V, R0 is low level; if A and B are floating or short-circuited, R0 is high level.

[0042] To enable the output: When it is low, RO is enabled. When it is high level, R0 is in high impedance state.

[0043] DE is the driver output enable: by pulling DE high, the driver's output terminals A and B are enabled, and when DE is low, they are in a high-impedance state.

[0044] DI is the input terminal: DI is low level, A is low level, and B is high level; DI is high level, A is high level, and B is low level.

[0045] A is the output signal port.

[0046] B is the output signal port.

[0047] R is a logic circuit that converts differential signals into single-ended signals.

[0048] D is a logic circuit for converting single-ended signals into differential signals.

[0049] Temper is the internal temperature monitoring part. When the chip reaches high temperature, it has a thermal shutdown function.

[0050] The control logic and implementation are as follows:

[0051] Self-transmitting and receiving logic: When data comes in, FPGA automatically receives the data according to the RS485 protocol, and when it needs to be sent, it automatically sends the data through the TX signal.

[0052] Data transmission process: To transmit data, the TX pin of FPGA is used, that is, the data is displayed on the TX pin. To send data AA, written in binary is 0x10101010, and the TXD pin will use high and low levels to represent 1 and 0 in turn. When TX sends 0, the transistor is not turned on, DE is connected to a high level, and the transmission mode is entered. The SSP485 chip will reflect the level on DI to the AB pin for output. Because DI is grounded, the AB pin will transmit 0. Therefore, when TXD sends 0, the AB pin sends 0.

[0053] When TX sends 1, the transistor is turned on. Connect low level, enter receiving mode, the AB pin of SSP485 chip enters high impedance state, because R3 pulls A high and R2 pulls B low, so AB transmits 1. Therefore, when TXD sends 1, AB pin sends 1.

[0054] Data receiving process: FPGA pin RX is used to receive data. During the data receiving process, the TX pin is always kept at a high level. When TXD is at a high level, It is a low level, which just turns into the receiving state, and then the RO pin of the SSP485 chip (that is, the pin connected to RX) will receive the data transmitted by AB.

[0055] For the specific control circuit, the role of resistor R1 is: RXD connects resistor R1 to RO of SSP485 chip, where R1 is used to limit current and protect the pin. The size of R1 can be 330 ohms, 470 ohms, 560 ohms, or 1K.

[0056] Resistors R2, R3 and transistor Q1: Resistors R2, R3 and NPN transistor Q1 form a transistor switch circuit, R3 is a current limiting resistor, preferably 4.7K, 10K can also be selected. R2 is a pull-up resistor, 4.7K or 10K can be selected.

[0057] NPN transistor, when TXD is high, the transistor is turned on. The DE pin is grounded and enters the receiving mode; when the TXD level is low, the transistor is cut off. The DE pin is connected to a high level to enter the sending mode.

[0058] Capacitor C1: C1 is a power bypass capacitor, which is used to provide a clean power supply to the SSP485 chip to enable it to work stably.

[0059] SSP485 receiving characteristics: The receiver input thresholds are set to -50mv and 200mv respectively. If the differential receiver input voltage AB is greater than or equal to -50mv, RO is high; if the voltage AB is less than or equal to -200mv, RO is low.

[0060] When all transmitters on a terminated bus are disabled, the receiver differential input voltage is pulled to 0V by the termination resistors; a logic high level with a minimum noise margin of 50mV is achieved according to the receiver threshold. Unlike previous fail-safe devices, the -50mv to -200mv threshold voltage complies with the ±200mv EIA / TIA-485 standard.

[0061] SSP485 driver features:

[0062] When DE is high, SSP485 enters driver mode. The function truth table is as follows:

[0063]

[0064] The output of the SSP485 chip can be set to three-state output through the high-level effective DE input pin.

[0065] The IC device used is ADAR1000, which is a 4-channel device covering the frequency band of 8GHz to 16GHz and operating in time division duplex mode. Its transmitter and receiver are integrated into one IC, which can be configured to operate in transceiver mode only or receiver mode only.

[0066] The device uses a 7mm×7mmQFN surface mount package and can be easily integrated into a flat panel array. It consumes only 240mW / channel in transmit mode and 160mW / channel in receive mode. The transceiver and receiver channels are directly available and are used in conjunction with the antenna RF front-end module in the external design. A phase step of less than 2.8° and a gain control better than 31dB can be achieved.

[0067] ADAR1000 integrates on-chip memory to store up to 121 beam states, one of which contains all phase and gain settings for the entire IC. The transmitter provides approximately 19dB gain and 15dBm saturation power, of which the receive gain is approximately 14dB. Another key indicator is the phase change of the gain control, which is approximately 3° within a 20dB range. Similarly, within the entire 360° phase coverage range, the gain change of the phase control is approximately 0.25dB, alleviating the calibration challenge.

[0068] In addition, the control method implemented by the antenna RF front end is a conventional technical means well known to those skilled in the art, and is only briefly described here:

[0069] Receiving Mode:

[0070] The beam controller FPGA sends a receive command to the phased array radar chip ADAR1000, which then passes through the attenuator and phase controller in sequence. At this time, the switch controller will switch to the power amplifier path and open the receiving switch channel of the T / R component to realize the reception of the antenna echo signal.

[0071] Transmit Mode:

[0072] The beam controller sends a transmit command to the phased array radar chip ADAR1000, which passes through the attenuator and phase controller in sequence. At this time, the switch controller will switch to the filter path, and then pass through the low-noise amplifier and open the transmit switch channel of the T / R component to realize the transmission of the antenna signal.

[0073] Finally, it should be noted that the above embodiments are only used to illustrate the technical solution of the utility model, rather than to limit it. Although the utility model has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein by equivalents. These modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the utility model, and they should all be included in the scope of the claims and specification of the utility model.

[0074] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A satellite-borne phased array antenna beam control system, comprising a beam controller FPGA, a plurality of T / R components and an antenna, characterized in that: The beam controller FPGA is connected to a plurality of the T / R components respectively through a plurality of control links, and each of the T / R components is connected to the antenna correspondingly; Each control link is equipped with a phased array radar chip and multiple control chips. The beam controller FPGA transmits a signal to the control chip, and the control chip outputs a differential signal to the phased array radar chip. After the phased array radar chip performs beam modulation, the modulated beam signal is sent to the T / R component; The T / R component receives the echo signal of the antenna, and sends the echo signal to the phased array radar chip through the control chip. The phased array radar chip demodulates the received signal and transmits the demodulated data back to the beam controller FPGA.

2. The satellite-borne phased array antenna beam control system according to claim 1, characterized in that: The control chip is connected to form a control circuit, wherein the beam controller FPGA is connected to the phased array radar chip through two connected control circuits, and the phased array radar chip is connected to the T / R component through one control circuit.

3. The satellite-borne phased array antenna beam control system according to claim 2, characterized in that: The control circuit comprises: The first pin of the control chip is connected to a first resistor, the first resistor is connected to the beam controller FPGA or the phased array radar chip, and the second pin, the third pin and the fourth pin of the control chip are connected to the beam controller FPGA or the phased array radar chip through a transistor switch circuit; The fifth pin of the control chip is grounded, the sixth pin and the seventh pin thereof are connected to the T / R component or to a diode element of another control circuit provided on the phased array radar chip through a diode element, the sixth pin thereof is connected to a 3.3V power supply through a fifth resistor, the seventh pin thereof is grounded through a fourth resistor, and the eighth pin thereof is connected to a 3.3V power supply through a first capacitor.

4. The satellite-borne phased array antenna beam control system according to claim 3, characterized in that: The control chip adopts the SSP485 chip, and the phased array radar chip adopts the ADAR1000 chip.

5. The satellite-borne phased array antenna beam control system according to claim 3, characterized in that: The transistor is an NPN transistor.

6. The satellite-borne phased array antenna beam control system according to claim 3, characterized in that: The diode element adopts an electrostatic protection diode.

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