Low-noise amplifier with measurable bias voltage, chip and amplifying circuit

Abstract

The utility model relates to the technical field of low noise amplifiers, and discloses a bias voltage measurable low noise amplifier, a chip and an amplification circuit, the low noise amplifier comprises a voltage detection unit, a bias voltage generation unit, a first switch, a second switch, an MOS tube N1, an MOS tube N2, an inductor Lc, an inductor Ls, a capacitor Cin, a capacitor Cout, a buffer unit, a resistor R1 and a resistor R2; when the circuit is used, the circuit enters a debugging mode by setting the amplitude of the external voltage, after the circuit enters the debugging mode, the bias voltage test of the MOS tube can be carried out by setting the debugging voltage VG and adjusting the voltage at one end of the capacitor Cout, and after the test is completed, the bias voltage of the MOS tube can be tested by adjusting the magnitude of the external voltage even if the external voltage is greater than a first threshold value. The circuit may be brought into an amplification mode. Therefore, the circuit provided by the utility model can meet the requirements of bias voltage test and signal amplification at the same time, and is simple and convenient to operate, short in time and high in efficiency because a plurality of test circuits are not required to be manufactured for bias voltage test.

Description

Technical Field

[0001] The utility model relates to the technical field of low-noise amplifiers, in particular to a low-noise amplifier, a chip and an amplifier circuit with measurable bias voltage. Background Art

[0002] Low Noise Amplifier (LNA) is an important part of the RF receiver system. Its main function is to amplify the weak signal received by the receiver antenna and then output the signal required for normal operation to the subsequent circuit. In actual use, since LNA is often located in the first stage of the RF circuit system, its performance parameters such as noise, gain and linearity directly affect the entire circuit system.

[0003] In order to consider the integration of bias circuits and product cost, existing low noise amplifiers are generally manufactured using RFCMOS or SOI processes, and finally a wafer is packaged into a single chip to produce a product. Usually, the main active circuit of the low noise amplifier RF structure adopts a common source and common gate structure, plus a passive input source degeneration inductor and output choke inductor. The relevant circuit diagram is as follows Figure 1 shown.

[0004] from Figure 1 It can be seen that the gate voltage bias Vcs / Vcg of the two cascode NMOS tubes of the low noise amplifier is provided by the bias voltage generation unit. The DC operating point setting of the active device will be related to the overall LNA operating current; at the same time, the DC operating voltage of the active device determines the working area of ​​the NMOS tube, thereby determining the size of the parasitic capacitance Cgs / Cgd, and the parasitic capacitance will affect the overall RF performance of the low noise amplifier by participating in the RF matching of the input and output. It can be seen that the voltage bias of the active device will affect the performance of the entire low noise amplifier.

[0005] At present, in order to meet the low noise requirement, the design of low noise amplifier selects NMOS tube N1 as an advanced process device with short channel size, such as 1.2V RF NMOS tube, so that the characteristic frequency ft becomes higher, which is conducive to noise matching and can effectively reduce the noise introduced by the LNA circuit to the overall RF link. However, as the tube size of the short channel size NMOS tube becomes smaller, the performance deviation range of circuit parameters such as working current and working area is large; in addition, as the process size becomes smaller, the influence of layout LPE becomes increasingly serious, resulting in a unidirectional shift of DC current towards a larger value, which is difficult to predict through simulation results due to model accuracy.

[0006] To address the above issues, the engineering chip is generally taped out to make more test versions of the circuit for comparative testing, so as to iteratively set the voltage convergence to optimize the RF performance; at the same time, more test versions are made for permutations and combinations. However, this operation has the following shortcomings in actual use:

[0007] On the one hand, exhaustive comparison of RF performance tests is not complete; on the other hand, the feedback loop of results in engineering development is too long, which seriously delays the progress of engineering development. Utility Model Content

[0008] In view of the shortcomings of the background technology, the utility model provides a low-noise amplifier, a chip and an amplifier circuit with a measurable bias voltage. The technical problem to be solved is that the bias voltage of the MOS tube of the low-noise amplifier is currently determined by using engineering chip tape-out to perform more test version circuits for comparative testing, which has the problems of complex operation, high workload and long feedback time.

[0009] In order to solve the above technical problems, in the first aspect, the utility model provides the following technical solutions: a low noise amplifier with measurable bias voltage, comprising a voltage detection unit, a bias voltage generating unit, a first switch, a second switch, a MOS tube N1, a MOS tube N2, an inductor Lc, an inductor Ls, a capacitor Cin, a capacitor Cout, a buffer unit, a resistor R1 and a resistor R2;

[0010] The voltage detection unit is used to receive an external voltage, and input a first selection signal En_sel to the bias voltage generation unit when the amplitude of the external voltage is greater than a first threshold, and input a second selection signal Bias_sel to the first switch and the second switch respectively when the amplitude of the external voltage is less than a second threshold;

[0011] The bias voltage generating unit outputs a bias voltage Vcg and a bias voltage Vcs in response to the first selection signal En_sel;

[0012] The first switch and the second switch each include two input terminals and a common terminal, and the input terminal of each switch is electrically connected to the common terminal to form a switch channel;

[0013] One input end of the first switch is used to input a bias voltage Vcs, the other input end of the first switch is electrically connected to the output end of the buffer unit, the input end of the buffer unit is electrically connected to one end of the capacitor Cout, the common end of the first switch is electrically connected to one end of the capacitor Cin and the gate of the MOS transistor N1 through the resistor R1, the source of the MOS transistor N1 is grounded through the inductor Ls; the drain of the MOS transistor N1 is electrically connected to the source of the MOS transistor N2;

[0014] The first switch selects an input terminal to be electrically connected to the common terminal in response to the second selection signal Bias_sel;

[0015] One input end of the second switch is used to input a bias voltage Vcg, and the other input end of the second switch is used to input a debugging voltage VG or to be grounded. The common end of the second switch is electrically connected to the gate of the MOS tube N2 through the resistor R2, and the drain of the MOS tube N2 is electrically connected to one end of the inductor Lc and the other end of the capacitor Cout respectively; the other end of the inductor LC is used to connect to the power supply V DD ;

[0016] The second switch selects an input terminal to be electrically connected to the common terminal in response to the second selection signal Bias_sel.

[0017] In a certain implementation of the first aspect, the MOS transistor N1 is an NMOS transistor.

[0018] In a certain implementation of the first aspect, the MOS transistor N2 is an NMOS transistor.

[0019] In a certain implementation manner of the first aspect, the voltage detection unit includes a MOS transistor P10, a MOS transistor P11, a MOS transistor P12, a MOS transistor N10, a MOS transistor N11, a MOS transistor N12, a current source I1, a current source I2, a buffer BUF1, a buffer BUF2, an AND gate AND, and a NOR gate NOR;

[0020] The source of MOS tube P10 is electrically connected to the source of MOS tube P11 for connecting to the power supply V DD , the gate of the MOS transistor P10 is electrically connected to the gate of the MOS transistor P11, the drain of the MOS transistor P10 and the drain of the MOS transistor N10 respectively, the gate of the MOS transistor N10 is grounded, the drain of the MOS transistor P11 is grounded through the current source I1 and is electrically connected to the input end of the buffer BUF1, and the output end of the buffer BUF1 is electrically connected to one input end of the AND gate AND and one input end of the NOR gate NOR respectively;

[0021] The source of the MOS transistor N10 is electrically connected to the source of the MOS transistor P12 and is used to input an external voltage. The gate of the MOS transistor P12 is grounded. The drain of the MOS transistor P12 is electrically connected to the drain of the MOS transistor N11, the gate of the MOS transistor N11 and the gate of the MOS transistor N12 respectively. The source of the MOS transistor N11 and the source of the MOS transistor N12 are both grounded.

[0022] Power Supply V DDThe current source I2 is electrically connected to the drain of the MOS tube N12, the drain of the MOS tube N12 is electrically connected to the input end of the buffer BUF2, the output end of the buffer BUF2 is electrically connected to the other input end of the AND gate AND and the other input end of the NOR gate NOR respectively, the output end of the AND gate AND is used to output the second selection signal Bias_sel, and the output end of the XOR gate NOR is used to output the first selection signal En_sel.

[0023] In a certain implementation of the first aspect, the buffer unit includes a buffer, a positive input terminal of the buffer is electrically connected to one end of the capacitor Cout, and a negative input terminal of the buffer is electrically connected to an output terminal of the buffer.

[0024] In a second aspect, the utility model provides a chip, including a chip body, on which the above-mentioned low-noise amplifier with measurable bias voltage is provided; the chip body is provided with a first pin, a second pin, a third pin, a fourth pin, a fifth pin and a sixth pin;

[0025] The pin No. 1 is connected to the other input end of the second switch; the pin No. 2 is used for grounding; the pin No. 3 is used for electrically connecting to the other end of the capacitor Cin; the pin No. 4 is electrically connected to the other end of the inductor Lc; the pin No. 5 is electrically connected to the voltage detection unit for inputting the external voltage; the pin No. 6 is electrically connected to one end of the capacitor Cout.

[0026] In a certain implementation of the second aspect, the pin No. 1, pin No. 2 and pin No. 3 are arranged on the left side of the chip body, and the pin No. 4, pin No. 5 and pin No. 6 are arranged on the right side of the chip body.

[0027] In a certain implementation manner of the second aspect, the pin No. 1, pin No. 2, pin No. 3, pin No. 4, pin No. 5 and pin No. 6 are symmetrically arranged on the chip body.

[0028] In a third aspect, the utility model provides an amplifier circuit, including the above-mentioned chip, wherein the second pin is grounded, the third pin is electrically connected to one end of the inductor L1, the fourth pin is grounded through the capacitor C1, and the sixth pin is electrically connected to one end of the resistor R3.

[0029] In a certain implementation of the third aspect, when confirming the bias voltage, the pin No. 1 is used to connect to the debugging voltage VG, and the other end of the resistor R3 is used to input the debugging voltage VC; when amplifying the signal, the pin No. 1 is grounded, and the other end of the resistor R3 is left floating.

[0030] Compared with the prior art, the utility model has the following beneficial effects: in actual use, the utility model can make the circuit enter the debugging mode by setting the amplitude of the external voltage, even if the amplitude of the external voltage is less than the second threshold value, after entering the debugging mode, the bias voltage test of the MOS tube can be performed by setting the debugging voltage VG and adjusting the voltage at one end of the capacitor Cout, and after the test is completed, the circuit can enter the amplification mode by adjusting the amplitude of the external voltage, even if the external voltage is greater than the first threshold value. Therefore, the circuit of the utility model can meet the requirements of bias voltage testing and signal amplification at the same time, and because there is no need to make multiple test circuits for bias voltage testing, the operation is simple, the time is short and the efficiency is high. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 is a circuit diagram of an existing low noise amplifier;

[0032] Figure 2 is a circuit diagram of the low noise amplifier in the first embodiment;

[0033] Figure 3 is a circuit diagram of a voltage detection unit in Embodiment 1;

[0034] Figure 4 is a schematic diagram of the structure of the chip in the second embodiment;

[0035] Figure 5 It is a schematic diagram of the amplifier circuit in the third embodiment. DETAILED DESCRIPTION

[0036] Now the utility model is further described in detail with reference to the accompanying drawings. These drawings are simplified schematic diagrams, which only illustrate the basic structure of the utility model in a schematic manner, and therefore only show the components related to the utility model.

[0037] Embodiment 1

[0038] like Figure 2 As shown, a low noise amplifier with measurable bias voltage includes a voltage detection unit 1, a bias voltage generating unit 2, a first switch 3, a second switch 4, a MOS tube N1, a MOS tube N2, an inductor Lc, an inductor Ls, a capacitor Cin, a capacitor Cout, a buffer unit 5, a resistor R1 and a resistor R2;

[0039] The voltage detection unit 1 is used to receive the external voltage EN, and input the first selection signal En_sel to the bias voltage generation unit 2 when the amplitude of the external voltage EN is greater than the first threshold, and input the second selection signal Bias_sel to the first switch 3 and the second switch 4 respectively when the amplitude of the external voltage EN is less than the second threshold;

[0040] The bias voltage generating unit 2 outputs a bias voltage Vcg and a bias voltage Vcs in response to a first selection signal En_sel;

[0041] The first switch 3 and the second switch 4 each include two input terminals and a common terminal, and the input terminal of each switch is electrically connected to the common terminal to form a switch channel;

[0042] One input end of the first switch 3 is used to input the bias voltage Vcs, the other input end of the first switch 3 is electrically connected to the output end of the buffer unit 5, the input end of the buffer unit 5 is electrically connected to one end of the capacitor Cout, the common end of the first switch 3 is electrically connected to one end of the capacitor Cin and the gate of the MOS transistor N1 through the resistor R1, the source of the MOS transistor N1 is grounded through the inductor Ls; the drain of the MOS transistor N1 is electrically connected to the source of the MOS transistor N2;

[0043] The first switch 3 selects an input terminal to be electrically connected to the common terminal in response to the second selection signal Bias_sel;

[0044] One input end of the second switch 4 is used to input the bias voltage Vcg, and the other input end of the second switch 4 is used to input the debugging voltage VG or ground. The common end of the second switch 4 is electrically connected to the gate of the MOS tube N2 through the resistor R2, and the drain of the MOS tube N2 is electrically connected to one end of the inductor Lc and the other end of the capacitor Cout respectively; the other end of the inductor LC is used to connect to the power supply V DD ;

[0045] The second switch selects an input terminal to be electrically connected to the common terminal in response to a second selection signal Bias_sel.

[0046] Specifically, in this embodiment, the MOS transistor N1 is an NMOS transistor.

[0047] Specifically, in this embodiment, the MOS transistor N2 is an NMOS transistor.

[0048] like Figure 3 As shown, in this embodiment, the voltage detection unit 1 includes MOS transistor P10, MOS transistor P11, MOS transistor P12, MOS transistor N10, MOS transistor N11, MOS transistor N12, current source I1, current source I2, buffer BUF1, buffer BUF2, AND gate AND and NOR gate NOR;

[0049] The source of MOS tube P10 is electrically connected to the source of MOS tube P11 for connecting to the power supply V DD, the gate of the MOS transistor P10 is electrically connected to the gate of the MOS transistor P11, the drain of the MOS transistor P10 and the drain of the MOS transistor N10 respectively, the gate of the MOS transistor N10 is grounded, the drain of the MOS transistor P11 is grounded through the current source I1 and is electrically connected to the input end of the buffer BUF1, and the output end of the buffer BUF1 is electrically connected to one input end of the AND gate AND and one input end of the NOR gate NOR respectively;

[0050] The source of the MOS transistor N10 is electrically connected to the source of the MOS transistor P12 and is used to input an external voltage. The gate of the MOS transistor P12 is grounded. The drain of the MOS transistor P12 is electrically connected to the drain of the MOS transistor N11, the gate of the MOS transistor N11 and the gate of the MOS transistor N12 respectively. The source of the MOS transistor N11 and the source of the MOS transistor N12 are both grounded.

[0051] Power Supply V DD The current source I2 is electrically connected to the drain of the MOS tube N12, the drain of the MOS tube N12 is electrically connected to the input end of the buffer BUF2, the output end of the buffer BUF2 is electrically connected to the other input end of the AND gate AND and the other input end of the NOR gate NOR respectively, the output end of the AND gate AND is used to output the second selection signal Bias_sel, and the output end of the XOR gate NOR is used to output the first selection signal En_sel.

[0052] In actual use, the voltage detection unit 1 inputs a high-level first selection signal En_sel to the bias voltage generating unit 2 when the amplitude of the external voltage EN is greater than the first threshold, and inputs a high-level second selection signal Bias_sel to the first switch 3 and the second switch 4 respectively when the amplitude of the external voltage EN is less than the second threshold.

[0053] When receiving the high-level second selection signal Bias_sel, the first switch 3 and the second switch 4 respectively select another input terminal to be connected to the common terminal, thereby causing the circuit to enter the bias voltage test mode; when not receiving the high-level second selection signal Bias_sel, the first switch 3 and the second switch 4 respectively select one input terminal to be connected to the common terminal, thereby causing the circuit to enter the signal amplification mode.

[0054] Specifically, in this embodiment, the first threshold is greater than the second threshold, wherein the magnitudes of the first threshold and the second threshold can be selected according to actual needs. Exemplarily, the first threshold is +1V and the second threshold is -1V.

[0055] for Figure 3 In the circuit shown, the levels of node A, node B, the first selection signal En_sel and the second selection signal Bias_sel when the external voltage EN is -1.2V, 0V and 1.8V are shown in the following table:

[0056] EN A B En_sel Bias_sel -1.2 High level High level Low level High level 0 Low level High level Low level Low level 1.8 Low level Low level High level Low level

[0057] Specifically, in this embodiment, the buffer unit 5 includes a buffer BUFFER, a positive input terminal of the buffer BUFFER is electrically connected to one end of the capacitor Cout, and a negative input terminal of the buffer BUFFER is electrically connected to an output terminal of the buffer BUFFER.

[0058] In actual use, when the circuit enters the bias voltage test mode, by adjusting the voltage at the input end of the buffer BUFFER, the voltage at the other input end of the first switch 3 can be adjusted, thereby adjusting the gate voltage of the MOS tube N1, realizing the bias voltage adjustment test, and finding the optimal bias voltage values ​​of the MOS tube N1 and the MOS tube N2.

[0059] for Figure 2 In the circuit shown, when the first selection signal EN_sel is at a high level, the bias voltage generating unit 2 outputs the bias voltage Vcs and the bias voltage Vcg; when the first selection signal EN_sel is at a low level, the bias voltage generating unit 2 is turned off, and the bias voltage Vcs and the bias voltage Vcg are outputted as zero, thus saving current;

[0060] When the second selection signal Bias_sel is at a high level, the node Vcg_int is connected to GND / VG through the second switch 4, and the node Vcs_int is connected to the output end of the buffer unit 5. This is the engineering modulation mode; when the second selection signal Bias_sel is at a low level, the node Vcg_int is connected to the bias voltage Vcg through the second switch 4, and the node Vcs_int is connected to the bias voltage Vcs through the first switch 3. This is the normal working mode.

[0061] In summary, in this embodiment, by setting the amplitude of the external voltage EN, the circuit can enter the debugging mode. Even if the amplitude of the external voltage EN is less than the second threshold, after entering the debugging mode, the bias voltage test of the MOS tube can be performed by setting the debugging voltage VG and adjusting the voltage at one end of the capacitor Cout. After the test is completed, by adjusting the amplitude of the external voltage EN, the circuit can enter the amplification mode. Therefore, the circuit of the utility model can meet the requirements of bias voltage testing and signal amplification at the same time, and since there is no need to make multiple test circuits for bias voltage testing, the operation is simple, the time is short and the efficiency is high.

[0062] Embodiment 2

[0063] like Figure 4As shown, this embodiment provides a chip, including a chip body 7, on which a low-noise amplifier with measurable bias voltage according to the first embodiment is provided; the chip body 7 is provided with a first pin, a second pin, a third pin, a fourth pin, a fifth pin and a sixth pin;

[0064] Pin No. 1 is connected to the other input end of the second switch 4; Pin No. 2 is used for grounding; Pin No. 3 is used for electrically connecting to the other end of the capacitor Cin; Pin No. 4 is electrically connected to the other end of the inductor Lc; Pin No. 5 is electrically connected to the voltage detection unit for inputting an external voltage; Pin No. 6 is electrically connected to one end of the capacitor Cout.

[0065] Specifically, in this embodiment, pin No. 1, pin No. 2 and pin No. 3 are arranged on the left side of the chip body, and pin No. 4, pin No. 5 and pin No. 6 are arranged on the right side of the chip body.

[0066] Specifically, in this embodiment, pin No. 1, pin No. 2, pin No. 3, pin No. 4, pin No. 5 and pin No. 6 are symmetrically arranged on the chip body.

[0067] Embodiment 3

[0068] like Figure 5 As shown, this embodiment provides an amplifier circuit, including a chip in Embodiment 2, wherein pin No. 2 is grounded, pin No. 3 is electrically connected to one end of inductor L1, pin No. 4 is grounded through capacitor C1, and pin No. 6 is electrically connected to one end of resistor R3.

[0069] In addition, in this embodiment, when confirming the bias voltage, pin No. 1 is used to access the debugging voltage VG, and the other end of the resistor R3 is used to input the debugging voltage VC; when amplifying the signal, pin No. 1 is grounded, and the other end of the resistor R3 is left floating.

[0070] The above is based on the disclosure of the utility model. Through the above description, relevant staff can make various changes and modifications without deviating from the technical concept of the utility model. The technical scope of the utility model is not limited to the content in the specification, and its technical scope must be determined according to the scope of the claims.

Claims

1. A low noise amplifier with measurable bias voltage, characterized in that: It includes a voltage detection unit, a bias voltage generating unit, a first switch, a second switch, a MOS tube N1, a MOS tube N2, an inductor Lc, an inductor Ls, a capacitor Cin, a capacitor Cout, a buffer unit, a resistor R1 and a resistor R2; The voltage detection unit is used to receive an external voltage, and input a first selection signal En_sel to the bias voltage generation unit when the amplitude of the external voltage is greater than a first threshold, and input a second selection signal Bias_sel to the first switch and the second switch respectively when the amplitude of the external voltage is less than a second threshold; The bias voltage generating unit outputs a bias voltage Vcg and a bias voltage Vcs in response to the first selection signal En_sel; The first switch and the second switch each include two input terminals and a common terminal, and the input terminal of each switch is electrically connected to the common terminal to form a switch channel; One input end of the first switch is used to input a bias voltage Vcs, the other input end of the first switch is electrically connected to the output end of the buffer unit, the input end of the buffer unit is electrically connected to one end of the capacitor Cout, the common end of the first switch is electrically connected to one end of the capacitor Cin and the gate of the MOS transistor N1 through the resistor R1, the source of the MOS transistor N1 is grounded through the inductor Ls; the drain of the MOS transistor N1 is electrically connected to the source of the MOS transistor N2; The first switch selects an input terminal to be electrically connected to the common terminal in response to the second selection signal Bias_sel; One input end of the second switch is used to input a bias voltage Vcg, and the other input end of the second switch is used to input a debugging voltage VG or to be grounded. The common end of the second switch is electrically connected to the gate of the MOS tube N2 through the resistor R2, and the drain of the MOS tube N2 is electrically connected to one end of the inductor Lc and the other end of the capacitor Cout respectively; the other end of the inductor LC is used to connect to the power supply V DD ; The second switch selects an input terminal to be electrically connected to the common terminal in response to the second selection signal Bias_sel.

2. A low noise amplifier with measurable bias voltage according to claim 1, characterized in that: The MOS tube N1 is an NMOS tube.

3. A low noise amplifier with measurable bias voltage according to claim 1, characterized in that: The MOS tube N2 is an NMOS tube.

4. The low noise amplifier with measurable bias voltage according to claim 1, characterized in that: The voltage detection unit includes MOS transistor P10, MOS transistor P11, MOS transistor P12, MOS transistor N10, MOS transistor N11, MOS transistor N12, current source I1, current source I2, buffer BUF1, buffer BUF2, AND gate AND and NOR gate NOR; The source of MOS tube P10 is electrically connected to the source of MOS tube P11 for connecting to the power supply V DD , the gate of the MOS transistor P10 is electrically connected to the gate of the MOS transistor P11, the drain of the MOS transistor P10 and the drain of the MOS transistor N10 respectively, the gate of the MOS transistor N10 is grounded, the drain of the MOS transistor P11 is grounded through the current source I1 and is electrically connected to the input end of the buffer BUF1, and the output end of the buffer BUF1 is electrically connected to one input end of the AND gate AND and one input end of the NOR gate NOR respectively; The source of the MOS transistor N10 is electrically connected to the source of the MOS transistor P12 and is used to input an external voltage. The gate of the MOS transistor P12 is grounded. The drain of the MOS transistor P12 is electrically connected to the drain of the MOS transistor N11, the gate of the MOS transistor N11 and the gate of the MOS transistor N12 respectively. The source of the MOS transistor N11 and the source of the MOS transistor N12 are both grounded. Power Supply V DD The current source I2 is electrically connected to the drain of the MOS tube N12, the drain of the MOS tube N12 is electrically connected to the input end of the buffer BUF2, the output end of the buffer BUF2 is electrically connected to the other input end of the AND gate AND and the other input end of the NOR gate NOR respectively, the output end of the AND gate AND is used to output the second selection signal Bias_sel, and the output end of the XOR gate NOR is used to output the first selection signal En_sel.

5. The low noise amplifier with measurable bias voltage according to claim 1, characterized in that: The buffer unit includes a buffer, a positive input terminal of the buffer is electrically connected to one end of the capacitor Cout, and a negative input terminal of the buffer is electrically connected to an output terminal of the buffer.

6. A chip, characterized in that: A chip body is provided on which a low-noise amplifier with measurable bias voltage as claimed in any one of claims 1 to 5 is provided; a first pin, a second pin, a third pin, a fourth pin, a fifth pin and a sixth pin are provided on the chip body; The pin No. 1 is connected to the other input end of the second switch; the pin No. 2 is used for grounding; the pin No. 3 is used for electrically connecting to the other end of the capacitor Cin; the pin No. 4 is electrically connected to the other end of the inductor Lc; the pin No. 5 is electrically connected to the voltage detection unit for inputting the external voltage; the pin No. 6 is electrically connected to one end of the capacitor Cout.

7. A chip according to claim 6, characterized in that: The pin No. 1, pin No. 2 and pin No. 3 are arranged on the left side of the chip body, and the pin No. 4, pin No. 5 and pin No. 6 are arranged on the right side of the chip body.

8. A chip according to claim 7, characterized in that: The pin No. 1, pin No. 2, pin No. 3, pin No. 4, pin No. 5 and pin No. 6 are symmetrically arranged on the chip body.

9. An amplifier circuit, characterized in that: A chip comprising any one of claims 6 to 8, wherein the second pin is grounded, the third pin is electrically connected to one end of an inductor L1, the fourth pin is grounded via a capacitor C1, and the sixth pin is electrically connected to one end of a resistor R3.

10. The amplifier circuit according to claim 9, characterized in that: When confirming the bias voltage, the pin No. 1 is used to access the debugging voltage VG, and the other end of the resistor R3 is used to input the debugging voltage VC; when amplifying the signal, the pin No. 1 is grounded, and the other end of the resistor R3 is left floating.

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