Semiconductor package

Abstract

The embodiment of the utility model relates to a semiconductor package. A semiconductor package for embedded electromagnetic field (EMF) shielding protection using wire bonding is provided. The semiconductor may include a plurality of shield leads and signal leads. Shield leads may surround all of a portion of the die to shield the die from the EMF. The shield lead and the signal lead may be formed from wire bonded portions. In manufacturing the semiconductor package, these wire bonds may be created, connected to the base and / or die. The wire bond may then be broken to form a shielded wire and a signal wire. The leads may be connected to a ground plane and / or a signal pad, which are separated by a dielectric material.

Description

Technical Field

[0001] Example embodiments of the present disclosure generally relate to semiconductor packages using wire bonding for embedded electromagnetic field (EMF) shielding protection. Background Art

[0002] Semiconductor packages for electronic devices are constantly shrinking in size and being placed closer together. These semiconductor packages and other components in the electronic devices generate electromagnetic fields. Therefore, semiconductor packages are increasingly exposed to larger amounts of electromagnetic fields. Semiconductor packages may also need to download and / or process data at increasingly faster speeds. EMF exposure may cause semiconductor packages to malfunction and / or generate errors, including malfunctions and / or errors in the downloaded and / or processed data.

[0003] There is a need for new systems, apparatus, and methods for semiconductor packaging. The inventors have identified many areas of improvement in the prior art and processes that are the subject of the embodiments described herein. Through applied effort, ingenuity, and innovation, many of these deficiencies, challenges, and problems have been addressed by developing solutions included in the embodiments of the present disclosure, some examples of which are described in detail herein. Utility Model Content

[0004] The present disclosure is directed to one or more embodiments to overcome one or more deficiencies existing in existing semiconductor packages.

[0005] Various embodiments described herein relate to semiconductor packages, and more particularly, to semiconductor packages with embedded EMF shielding protection using wire bonding.

[0006] According to some embodiments of the present disclosure, an example method is provided. The example method is to manufacture a semiconductor package and may include: connecting a die to a base; creating a plurality of wire bonds, each of the plurality of wire bonds having a first end and a second end, wherein the first end of the first wire bond is connected to the die, and the second end of the first wire bond is connected to the base, and wherein the first end of the second wire bond and the second end of the second wire bond are each connected to the base; applying a molding to encapsulate the die and the plurality of wire bonds; removing the top side of the molding, the removal of the top side of the molding including: breaking the plurality of wire bonds into a plurality of leads, wherein each of the plurality of leads has a first end and a second end. The molded part is a shielded lead or a signal lead, the shielded lead is connected to the base at the first end of the shielded lead, and the signal lead is connected to the tube core at the first end of the signal lead; one or more redistribution layers are formed on the first side of the molding, wherein the one or more redistribution layers include one or more signal pads and one or more ground planes, wherein each of the one or more signal pads is connected to at least one signal lead, at least one signal lead is connected to at least one signal lead of the tube core, wherein at least one shielded lead of the one or more shielded leads connected to the base is connected to the ground plane; one or more solder bumps are applied to the one or more signal pads.

[0007] In some embodiments, a plurality of wire bonds surround the die.

[0008] In some embodiments, a plurality of wire bonds surround a portion of the die.

[0009] In some embodiments, the semiconductor package is one semiconductor package among a plurality of semiconductor packages on a panel.

[0010] In some embodiments, the method further includes separating the semiconductor package from another semiconductor package of the plurality of semiconductor packages on the panel via singulation.

[0011] In some embodiments, the method further includes adjusting alignment of one or more of the plurality of wire bonds in the first direction before applying the molding.

[0012] In some embodiments, the method further includes creating one or more cavities in the molding before forming the one or more redistribution layers on the first side of the molding, wherein each of the cavities is associated with a signal lead connected to the die.

[0013] In some embodiments, creating the one or more cavities utilizes laser ablation.

[0014] In some embodiments, forming one or more redistribution layers on the first side of the molding fills the one or more cavities with a conductive material.

[0015] In some embodiments, one or more ground planes are separated from one or more signal pads by one or more dielectric layers.

[0016] According to some embodiments of the present disclosure, a semiconductor package is provided. The semiconductor package includes: a tube core, the tube core has an active side; a base, the base is connected to the side of the tube core, the side is opposite to the active side; a plurality of shielding leads, wherein the plurality of shielding leads are connected to the base and connected to one or more ground planes; a plurality of signal leads, the plurality of signal leads are connected to the active side of the tube core and connected to one or more signal pads; wherein the plurality of shielding leads and the plurality of signal leads are formed by a plurality of wire bonding parts; a molding, the molding encapsulates the tube core, the shielding leads and the signal leads; a redistribution layer, the redistribution layer is on top of the molding, wherein the redistribution layer includes one or more ground planes and one or more signal pads; and a plurality of solder balls, wherein one or more of the plurality of solder balls are applied to the one or more signal pads.

[0017] In some embodiments, a plurality of shielding leads surround the die.

[0018] In some embodiments, a plurality of shielding leads surround portions of the die.

[0019] In some embodiments, the die is connected to the base using glue.

[0020] In some embodiments, the semiconductor package further includes under bump metallization under each solder ball.

[0021] In some embodiments, the under bump metallization includes nickel gold, titanium gold, or nickel palladium.

[0022] In some embodiments, the connection between at least one signal lead and the redistribution layer includes a cavity filled with a conductive material.

[0023] In some embodiments, the cavity is formed using laser ablation.

[0024] In some embodiments, at least one signal pad includes multiple copper layers, the multiple copper layers include a first copper layer and a second copper layer, the first copper layer is connected to the first signal lead, the second copper layer is connected to the first copper layer, wherein the first copper layer has a first width, wherein the second copper layer has a second width, the second width is greater than the first width and includes a portion of the second copper layer extending beyond the width of the first copper layer, and wherein the second copper layer extending beyond the width of the first copper layer is connected to an under bump metallization, the under bump metallization being associated with one of the plurality of solder balls.

[0025] In some embodiments, one or more ground planes are separated from one or more signal pads by one or more dielectric layers.

[0026] The above-described embodiments of the present disclosure can realize a semiconductor package with improved performance.

[0027] The above utility model content is provided only for the purpose of summarizing some example embodiments, in order to provide a basic understanding of some aspects of the present disclosure. Therefore, it is understood that the above embodiments are only examples and should not be interpreted as narrowing the scope or spirit of the present disclosure in any way. It should also be understood that in addition to the embodiments summarized here, the scope of the present disclosure also covers many potential embodiments, some of which will be further described below. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Having therefore generally described certain example embodiments of the present disclosure, reference will now be made to the accompanying drawings, which are not necessarily drawn to scale, in which:

[0029] Figure 1 illustrates an exemplary top view of a semiconductor package according to one or more embodiments of the present disclosure;

[0030] Figure 2 The present invention illustrates one or more embodiments of the present invention. Figure 1 An exemplary cross-sectional view of a semiconductor package at section AA;

[0031] Figure 3 The present invention illustrates one or more embodiments of the present invention. Figure 1 An exemplary cross-sectional view of a semiconductor package at a BB section;

[0032] Figure 4 illustrates an exemplary panel of a semiconductor package according to one or more embodiments of the present disclosure;

[0033] Figure 5 An example block diagram illustrating a flow chart of operations for manufacturing a semiconductor package according to one or more embodiments of the present disclosure;

[0034] FIG. 6A to FIG. 6GThe present invention illustrates a method for Figure 5 illustrative views of semiconductor packages associated with operations of;

[0035] 7A to 7C illustrates an exemplary portion of a cross-sectional view associated with adjustments according to one or more embodiments of the present disclosure; and

[0036] Fig. 8A and Figure 8B An exemplary portion of a cross-sectional view associated with a cavity for a lead in accordance with one or more embodiments of the present disclosure is illustrated. DETAILED DESCRIPTION

[0037] Some embodiments of the present disclosure will be described more fully herein with reference to the accompanying drawings, in which some, but not all, embodiments of the present disclosure are shown. In fact, various embodiments of the present disclosure may be embodied in many different forms and should not be construed as being limited to only the embodiments set forth herein; rather, these embodiments are provided so that the present disclosure satisfies applicable legal requirements. Like reference numerals refer to like elements throughout.

[0038] As used herein, the term "comprising" means including but not limited to and should be interpreted in the manner commonly used in a patent context. The use of broader terms such as including, comprising, and having should be understood to provide support for narrower terms such as consisting of, consisting essentially of, and consisting essentially of.

[0039] Phrases such as "in various embodiments," "in one embodiment," "according to one embodiment," "in some embodiments," etc. generally mean that the particular feature, structure, or characteristic following the phrase may be included in at least one embodiment of the present disclosure, and may be included in more than one embodiment of the present disclosure (importantly, such phrases do not necessarily refer to the same embodiment).

[0040] The words “example” or “exemplary” are used herein to mean “serving as an example, instance, or illustration.” Any implementation described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other implementations.

[0041] If the specification specifies that a component or feature "may", "could", "might", "should", "will", "preferably", "likely", "typically", "optionally", "for example", "usually", or "might" (or other such language) be included or have a characteristic, the particular component or feature need not be included or have the characteristic. Such a component or feature may optionally be included in some embodiments, or it may be excluded.

[0042] The term "circuitry" as used herein with respect to a component of a system or device should be understood to include specific hardware configured to perform the functions associated with the specific circuitry described herein. The term "circuitry" should be broadly understood to include hardware, and in some embodiments, software for configuring the hardware. For example, in some embodiments, "circuitry" may include processing circuitry, communication circuitry, input / output circuitry, etc. In some embodiments, other elements may provide or supplement the functionality of a specific circuitry.

[0043] Overview

[0044] Various embodiments of the present disclosure are directed to improved systems, apparatus, and methods for semiconductor packages with embedded EMF shielding protection using wire bonding.

[0045] Semiconductor packages are constantly shrinking in size and are used in environments with increasing amounts of electromagnetic fields, such as in mobile phones, portable electronic products, etc. The increase in EMF exposure may cause semiconductor packages to generate errors while processing and / or transmitting data. EMF exposure can be minimized or mitigated using semiconductor packages that use wire bonding as described herein to perform EMF shielding protection. This can improve the performance of such semiconductor devices and extend the life of these semiconductor packages.

[0046] According to the present disclosure, a semiconductor package has external wire bonding, which can be disconnected to create two leads. Portions of the disconnected leads can be shielding leads and / or signal leads. Shielding leads can be placed around the external portion of the semiconductor package. These shielding leads can be connected to a ground plane on a first side of the semiconductor package, thereby connecting to a base on a second side of the semiconductor package. Shielding leads can create a cage around all or part of the die of the semiconductor package. The cage can ground the signal generated by the EMF to which the semiconductor package is exposed. The signal lead can be connected to one or more signal pads in a plurality of signal pads to transmit signals between the die and an external device via a plurality of solder balls. An example of a semiconductor package can be a flip chip with solder balls, which connect one or more signal pads of a semiconductor device to one or more other circuit devices of an electronic device.

[0047] The methods described herein relate to making and using semiconductor packages using wire bonding for EMF shielding. Methods for making multiple semiconductor packages using wire bonding for EMF shielding are also described herein. For example, a panel of dies can be used to create multiple semiconductor packages, which can then be separated by cutting.

[0048] Exemplary Systems and Apparatus

[0049] Embodiments of the present disclosure include systems and apparatus for semiconductor packages with embedded EMF shielding protection using wire bonding as described herein and may be implemented in various embodiments.

[0050] Figure 1 An exemplary top view of a semiconductor package according to one or more embodiments of the present disclosure is illustrated. The semiconductor package 100 may include a dielectric layer 110, a ground plane 120, a plurality of signal pads 130, and a plurality of solder balls, such as a ground plane solder ball 122 and a signal pad solder ball 132. The dielectric layer may be a polyimide (PI) and / or a polybenzoxazole (PBO) material. Figure 1 Two lines are illustrated: a first line AA and a second line BB. Each of these lines indicates where a cross-sectional view for other figures is taken.

[0051] It can be easily understood that although only one of the signal pads 130 and the signal pad solder balls 132 is referenced using a reference numeral, the semiconductor package 100 can include multiple signal pads 130 and signal pad solder balls 132. Each of the signal pads 130 is separated from the ground plane 120 by one or more layers and / or portions of dielectric material (e.g., dielectric layer 110). The semiconductor package 100 can be a flip chip, and when it is used in an electronic device, multiple solder balls can connect the semiconductor package to other circuit devices of the electronic device. In various embodiments, the semiconductor package 100 can be generally square in shape. It can be easily understood that the semiconductor package 100 can take other shapes and / or dimensions, particularly as required by the electronic device.

[0052] Figure 2 The present invention illustrates one or more embodiments of the present invention. Figure 1 1 is an exemplary cross-sectional view of a semiconductor package at section AA. The semiconductor package 100 includes a die 160, which is connected to a base 170 using an adhesive 162 or the like (e.g., tape, etc.). The adhesive 162 may be a conductive adhesive or a non-conductive adhesive, and it may connect the die 160 to the base 170. The base 170 may be, for example, a bonding plate or have a bondable surface. In various embodiments, the base 170 may be a metal (e.g., copper, etc.) having a bondable surface. The bondable surface may have a plating layer on the side connected to the die, such as nickel gold, titanium gold, nickel palladium, etc. The signal pad solder balls 132A, 132B are connected to one or more under-bump metallization (UBM) layers, and the one or more UBM layers connect the signal pad solder balls 132 to their corresponding signal pads 130. The ground plane solder ball 122 is illustrated on top of the dielectric layer because it is not connected to the one or more UBM layers at the AA section.

[0053] The semiconductor package 100 includes a plurality of leads 182. As described herein, these leads 182A-182D are created by wire bonding encapsulated in a molding 150, which holds the leads 182A-182D in place. Leads 182A and 182C connect the base 170 to the ground plane 120. Leads 182B and 182D connect the die 160 to respective signal pads 130A, 130B. The leads 182B, 182D are offset from where the signal pad solder balls 132A, 132B are respectively connected to the signal pads 130. In various embodiments, the leads 182B, 182D are not offset and can be aligned with where the signal pad solder balls 132A, 132B are respectively connected to the signal pads 130A, 130B. Each of the signal pads 130 is formed in a redistribution layer (RDL) on top of the molding 150. The RDL includes a dielectric layer 110, a ground plane 120, and the signal pads 130. The signal pads are each connected to a solder ball 132. For example, the signal pad 130A is connected to the signal pad solder ball 132A, and the signal pad 130B is connected to the signal pad solder ball 132B.

[0054] like Figure 2 shown Figure 1 In the AA section of FIG. 1 , leads 182A and 182C connect the ground plane 120 to the base 170. The leads 182A, 182C are examples of shielded leads around the outside of the die 160 that provide EMF shielding.

[0055] Figure 3 The present invention illustrates one or more embodiments of the present invention. Figure 1 The cross-sectional view of the semiconductor package 100 at the cross-sectional view BB is close to the outside of the first outer side of the semiconductor package 100 and has a plurality of shielding leads 182E-182O around the first outer side of the semiconductor package 100, and the shielding leads 182E-182O are connected to the ground plane 120 and the base 170.

[0056] In various embodiments and as further described herein, these shield leads 182 on the outside may be formed by wire bonds connecting the base 170 to the die 160 or connected at both ends of the wire bonds to the base 170. The ground plane solder balls 122 and signal pad solder balls 132A, 132B are illustrated on top of the dielectric layer 110 because they are not connected to one or more UBM layers at the BB cross section.

[0057] like Figure 3 As shown, in Figure 1At the BB section, leads 182A, 182C and 182E-182O are shielded leads that connect the ground plane 120 to the base 170, providing EMF shielding.

[0058] In various embodiments, the leads around the exterior of the semiconductor package 100 may surround a portion of the die 160 or the entirety of the die 160 .

[0059] Figure 4 An exemplary panel of dies according to one or more embodiments of the present disclosure is illustrated. Panel 400 includes a plurality of dies 160A-160I. For example, the panel may have dimensions of 600 mm x 600 mm or a rectangle of dimensions 600 mm x 700 mm, and such a panel would contain a plurality of dies 160. It will be appreciated that the illustration is not drawn to scale and more or less dies 160 may be included on the panel. It will also be appreciated that the illustration of panel 400 may also apply to wafers, etc.

[0060] like Figure 4 As shown, one or more of the semiconductor packages may be misaligned. For example, semiconductor package 160B is misaligned due to rotation, semiconductor package 160E is misaligned due to offset in the Y direction, and semiconductor package 160H is misaligned due to offset in the X direction. It is understood that the illustrated misalignment may be exaggerated.

[0061] Because the small size requires precision, misalignment of the die 160 may cause the leads connecting the die 160 to the RDL 190 to be misaligned. Misalignment may cause the connection to fail or more likely fail under pressure. As described herein, the semiconductor package 100 using wire bonding for EMF shielding can address and / or correct such misalignment. This increases the yield of panels, etc., to which the present disclosure is applied. For example, after the panel 400 completes the multiple operations described herein, one or more cutting operations can be used to separate the individual semiconductor packages 100 from the panel 400.

[0062] It should be readily appreciated that the embodiments of the systems and apparatus described herein may be configured in a variety of additional and alternative ways beyond those expressly described herein.

[0063] Exemplary Methods

[0064] Figure 5 An example block diagram of a flowchart of operations for manufacturing a semiconductor package according to one or more embodiments of the present disclosure is illustrated. In various embodiments, one or more operations in the operations may be omitted or repeated. It will also be understood that other operations not described herein may also occur.

[0065] At operation 502, the die 160 is connected to the base 170. For example, the die 160 can be connected to the bondable surface of the base 170 using a glue 162 or the like. In various embodiments, a plurality of dies 160 can be connected to the base 170 of the panel 400. Fig. 6A is further described.

[0066] At operation 504, wire bonds are created. A plurality of wire bonds 180 are created, including one or more wire bonds 180 connecting the die 160 and the base 170, and one or more wire bonds 180 connecting both sides of the wire bonds 180 to the base 170. The wire bonds 180 may be created around all or part of the exterior of the die 160. This operation is about Figure 6B and Figure 6C is further described.

[0067] At operation 506, the wire bonds may be adjusted. In various embodiments, the wire bonds may be adjusted. Although adjustment of the wire bonds is described herein as a separate operation, it will be understood that the adjustment may be performed during or while creating the wire bonds. It may be determined that one or more wire bonds 180 need to be adjusted. In various embodiments, the RDL 190 may be formed without allowing the position of one or more portions of the RDL 190 to be adjusted. For example, a panel 400 having multiple dies 160 may have the RDL 190 formed at once for all dies 160. If any of the dies 160 are determined to be misaligned, those dies 160 may need to be aligned or the wire bonds 180 may be adjusted to allow for the misalignment. This operation is about 7A to 7C is further described.

[0068] At operation 508, molding 150 is applied. Molding 150 encapsulates the die and wire bonds 180, including being positioned over die 160 and wire bonds 180. Molding 150 holds die 160 and wire bonds 180 in place. This operation is related to Fig.6D is further described.

[0069] At operation 510, the top side of the molding 150 is removed to expose the leads 182. Removing the top side of the molding 150 can be accomplished by grinding down the molding 150 so that the wire bonds 180 are broken, each of the wire bonds 180 creating two separate leads 182 from different portions of the wire bonds 180. Each of these separate leads 180 can have an open end that is now exposed due to the molding 150 being removed, and a connected end that is connected to the die 160 for a signal lead 182 or to the base 170 for a shield lead 182. This operation is about Fig. 6Eis further described.

[0070] At operation 512, one or more cavities 198 may be created for leads 182. For example, and for each of the signal leads 182 connected to die 160, the ends of the signal leads 182 that are not connected to die 160 may have the molding 160 around the end portions of the leads 182 removed to create cavities 198 in molding 160. In various embodiments, cavities 198 may be created by laser, such as using laser ablation. This operation is about Fig. 8A and Figure 8B is further described.

[0071] At operation 514, one or more RDLs 190 may be formed. The formation of the RDLs 190 may generate the dielectric layer 110, the ground plane 120, the signal pads 130, and the UBM 140. Fig. 6F is further described.

[0072] At operation 516, solder bumps (eg, 122, 132) may be applied. Solder bumps may be applied to one or more portions of RDL 190 with UBM 140. This operation is related to Figure 6G is further described.

[0073] FIG. 6A to FIG. 6G The present invention illustrates a method for Figure 5 1 is an exemplary view of a semiconductor package 100 associated with the operation of FIG.

[0074] Fig. 6A An exemplary cross-sectional view of a die 160 attached to a base 170 via a glue 162, such as after performance of operation 502, is illustrated. The die 160 may have an active surface 164 on a first side, opposite the side on which the die 160 is attached to the base 170. In various embodiments, the base 170 may be part of a panel 400, a wafer, or the like.

[0075] Figure 6B An exemplary cross-sectional view of the die 160 and base 170 is illustrated, such as after performance of operation 504, wherein a first wire bond 180A and a second wire bond 180F have been created to bond the die 160 and base 170. The wire bonds 180A, 180F rise above the die 160 a first distance.

[0076] Figure 6CA top view of an exemplary die 160, such as after execution of operation 504, is illustrated, the die 160 being attached to the base 170 using a plurality of wire bonds 180. A first group of the plurality of wire bonds 180 (e.g., 180A, 180F-180K, and 180P-180T) is connected to the die 160 and the base 170. A second group of the plurality of wire bonds 180 (e.g., 180B-180E and 180L-180O) is connected to the base 170 at both ends. As shown, the wire bonds 180 are located around the exterior of the die 160. In various embodiments, an alternative number of wire bonds 180 may be created and / or alternative locations for the wire bonds 180 may be used.

[0077] Fig.6D An exemplary cross-sectional view of an exemplary die 160 , base 170 , and wire bonds 180A, 180B is illustrated after molding 150 has been applied to encapsulate die 160 and wire bonds 180 , such as after performance of operation 508 .

[0078] Fig. 6E Illustrated is an exemplary cross-sectional view after the top side of molding 150 has been removed and leads 182A-182D are exposed, such as after the execution of operation 510. The amount of molding 150 removed can be the amount that molding 150 disconnects wire bonding 180A to create leads 182A, 182B and disconnects wire bonding 180F to create leads 182C, 182D. Therefore, these leads 182A-182D no longer bond two components together. As shown, each lead in leads 182B and 182C is connected to die 160 at a first end and exposed to the top side of molding, wherein molding has an open second end. In addition, each lead in leads 182A and 182D is connected to base 170 at a first end and exposed to the top side of molding, wherein molding has an open second end. In various embodiments, the removal of molding 150 can be by grinding. When exposed, wire bond 180 becomes two leads in the illustrated embodiment: one signal lead (eg, 182B) and one shield lead (182A).

[0079] Fig. 6FAn exemplary cross-sectional view of the die 160, base 170, leads 182A-182D, and RDL 190 is illustrated, such as after the performance of operation 514. The formation of one or more RDLs 190 may include multiple operations that result in the formation of multiple layers, including conductive layer 110, ground plane 120, and signal pads 130. The size and shape of the RDL 190 may result from the performance of these multiple operations, which may include, but are not limited to: depositing copper seeds; depositing resist; resist exposure to remove one or more portions of the resist; electrolytic copper growth; resist stripping; substrate deposition (e.g., PI and / or PBO layer deposition); and UBM 140 deposition (e.g., nickel gold, titanium gold, nickel palladium, etc.). Multiple of these operations may be iterated to form the RDL 190. The UBM 140 may be applied because the copper layer of the RDL 190 may oxidize if the UBM is not applied and the copper is exposed. This oxidation may reduce the efficiency of the semiconductor package or cause failure. As the RDL 190 is formed, the shield leads (eg, 182A, 182D) are connected to the ground plane 120 and the signal leads (eg, 182B, 182C) are each connected to an associated signal pad (eg, 130A, 130B).

[0080] The RDL 190 is separated from the die 160 using leads (e.g., 182B, 182C) that connect the die 160 to the associated signal pads 130A, 130B. Since the RDL 190 and the die 160 have different coefficients of thermal expansion, separation between the RDL 190 and the die 160 by these signal leads 182B, 182D allows improved operation of the semiconductor package. Under thermal expansion, the RDL 190 and the die 160 may expand or contract and cause stress to the other, which may cause die delamination and / or disconnection or degradation of the connection. The signal leads 182 of the present disclosure allow for reduced stress and increased reliability between the RDL 190 and the die 160.

[0081] Figure 6G An exemplary cross-sectional view of the die 160 , base 170 , leads 182A- 182D, RDL 190 , and signal pad solder bumps 132A, 132B is illustrated, such as after performance of operation 516 .

[0082] 7A to 7C An exemplary portion of a cross-sectional view associated with adjustments according to one or more embodiments of the present disclosure is illustrated. Adjustments may allow the shape, spacing, and / or angles of wire bonds 180 and associated signal and shield leads created by breaking wire bonds 180 to be changed.

[0083] Fig. 7AAn exemplary portion of a cross-sectional view associated with adjustment of wire bonds 180 according to one or more embodiments of the present disclosure is illustrated, such as before and after execution of operation 516. For example, wire bonds 180A may be created with a first end connected to die 160 and a second end connected to base 170. When wire bonds 180A are connected according to the present disclosure, wire bonds 180A may be positioned in a first position 180A1 that may be misaligned. The misalignment of wire bonds 180A may be due to misalignment of die 160. Alternatively or additionally, the misalignment of wire bonds 180A may be due to displacement of wire bonds 180A once created. Adjustments may be made to move wire bonds 180A from a position illustrated as 180A1 to a second position illustrated as 180A2. Once wire bonds 180A are broken into signal leads and shield leads, the adjustments may, for example, align the ends of the signal leads. Although adjustment of wire bonds is described herein as a separate operation, it is to be understood that adjustment may be performed during or concurrently with creation of the wire bonds.

[0084] Figure 7B An exemplary portion of a cross-sectional view associated with adjustment of wire bonds 180A according to one or more embodiments of the present disclosure is illustrated, such as before and after performance of operation 516. Wire bonds 180A may be adjusted to move laterally to die 160 to adjust for misalignment.

[0085] Figure 7C An exemplary portion of a cross-sectional view associated with adjustment of wire bonds 180 according to one or more embodiments of the present disclosure is illustrated. Figure 7C The RDL 190 may include a signal pad 130 having a first copper layer 130A1 and a second copper layer 130A2. The first copper layer 130A1 may have a width 130A1-W and the second copper layer 130A2 may have a width 130A2-W. In various embodiments, the width of the lead may be 20 microns and the width of the first copper layer 130A1 may be 50-60 microns, which allows adjustment of the position at which the lead 182B is connected to the first copper layer 130A1 during the formation of the RDL 190. Adjustment of the wire bonding 180 may allow, for example, the signal lead 182B to be moved and connected to the first copper layer 130A1 during the formation of the RDL 190. In contrast, without such alignment, the signal lead 182B may be positioned on its exposed side prior to the operation of forming the RDL 190, which would cause the exposed side of the lead 182B to not be connected to the signal pad 130A.

[0086] The alignment operation may adjust leads 182 to connect to RDL layer 190. In various embodiments where multiple dies 160 are fabricated together in panel 400, one or more adjustments may improve yield of panel 400 because multiple dies 160 have RDLs formed for all dies 160 simultaneously, for example.

[0087] In various embodiments of manufacturing a panel, it may be determined whether one or more dies 160 are misaligned. If any die are misaligned, one or more adjustments to make may be determined. During manufacture of semiconductor package 100, one or more adjustments may be made.

[0088] Fig. 8A and Figure 8B An exemplary portion of a cross-sectional view associated with a cavity for a lead in accordance with one or more embodiments of the present disclosure is illustrated. In various embodiments, one or more cavities 198 can be created in the molding 150 for exposed ends of signal leads (e.g., 182B). The cavity 198 can be created using a laser, such as using laser ablation of the molding 150. The one or more cavities 198 can be created after removing the top side of the molding 150. The cavity 198 can allow the RDL 190 to be formed to include providing additional copper to connect the lead 182B to the RDL 190 by filling the cavity 198 with copper.

[0089] Fig. 8A An exemplary portion of a cross-sectional view associated with cavity 198 according to one or more embodiments of the present disclosure is illustrated, such as after performance of operation 512. Cavity 198 may be created after the top side of the molding has been removed. Cavity 198 may also remove molding 150 in specific areas associated with exposed ends of signal leads 182 or shield leads 182. Fig. 8A As shown, signal lead 182B is specifically connected to die 160 at active side 164 of die 160. Fig. 8A 190, but it is understood that the shielded leads 182 connected to the base 170 may also create cavities on their exposed ends that are not connected to the base 170. In various embodiments, the cavities 198 may also be created to account for misalignment of the die 160 and / or misalignment of the wire bonds 180 and / or leads 182 prior to formation of the RDL 190.

[0090] Figure 8B An exemplary portion of a cross-sectional view associated with cavity 198 in accordance with one or more embodiments of the present disclosure is illustrated, such as after performance of operation 514. During formation of RDL 190, cavity 198 has been filled with copper.

[0091] In various embodiments, using copper to fill cavity 198 can provide improved connection to the leads. It can also provide improved mechanical grip and adhesion of the connection between die 160 and signal pad 130 (or between base 170 and ground plane 120 for leads not shown).

[0092] in conclusion

[0093] The operations and / or functions of the present disclosure have been described herein, such as in a flowchart or accompanying figure associated with the flowchart. Although the operations and / or functions are illustrated in a particular order, this should not be understood as requiring that such operations and / or functions be performed in the particular order shown or in a sequential order, or that all illustrated operations be performed, in order to achieve the desired result. In some cases, alternatively ordered operations and / or functions may be advantageous. In some cases, the actions recited in the claims can be performed in a different order and still achieve the desired result. Therefore, although specific embodiments of the subject matter have been described, other embodiments are within the scope of the appended claims.

[0094] Although this specification includes many specific embodiments and implementation details, these should not be interpreted as limitations on any disclosure scope or content that may be claimed, but should be interpreted as descriptions of features specific to specific disclosed specific embodiments. Certain features described herein in the context of a separate embodiment may also be implemented in combination in a single embodiment. On the contrary, the various features described in the context of a single embodiment may also be implemented individually or in any suitable sub-combination in multiple embodiments. In addition, although the above-mentioned features may be described as working in certain combinations, even initially required to do so, in some cases, one or more features from the claimed combination may be cut out from the combination, and the claimed combination may be directed to a sub-combination or a variation of the sub-combination.

[0095] Although the detailed description has set forth certain embodiments of the invention, the appended claims cover other embodiments of the invention that differ from the described embodiments according to various modifications and improvements.

[0096] In the following claims, unless the specific terms "means for" or "step for" are used in a given claim, it is not intended that the claims be interpreted under 35 USC §112, paragraph 6.

Claims

1. A semiconductor package, characterized in that: include: a die having an active side; a base connected to a side of the die opposite the active side; a plurality of shielded leads, wherein the plurality of shielded leads are connected to the base and to one or more ground planes; a plurality of signal leads connected to the active side of the die and to one or more signal pads; wherein the plurality of shielding leads and the plurality of signal leads are formed by a plurality of wire-bonded portions; A molding, wherein the molding encapsulates the die, the shielding lead, and the signal lead; a redistribution layer on top of the molding, wherein the redistribution layer includes the one or more ground planes and the one or more signal pads; as well as A plurality of solder balls, wherein one or more solder balls of the plurality of solder balls are applied to the one or more signal pads.

2. The semiconductor package according to claim 1, wherein: The plurality of shielding leads surround the die.

3. The semiconductor package according to claim 1, wherein: The plurality of shielding leads surround a portion of the die.

4. The semiconductor package according to claim 1, wherein: The die is connected to the base using glue.

5. The semiconductor package according to claim 1, wherein: Also included is under bump metallization under each solder ball.

6. The semiconductor package according to claim 5, wherein: The under bump metallization includes nickel gold, titanium gold or nickel palladium.

7. The semiconductor package according to claim 1, wherein: The connection between at least one signal lead and the redistribution layer includes a cavity filled with a conductive material.

8. The semiconductor package according to claim 7, wherein: The cavity is formed using laser ablation.

9. The semiconductor package according to claim 1, wherein: At least one signal pad includes a plurality of copper layers, the plurality of copper layers including a first copper layer and a second copper layer, the first copper layer being connected to a first signal lead, the second copper layer being connected to the first copper layer, wherein the first copper layer has a first width, wherein the second copper layer has a second width, the second width being greater than the first width and including a portion of the second copper layer extending beyond the width of the first copper layer, and wherein the second copper layer extending beyond the width of the first copper layer is connected to an under bump metallization associated with one of the plurality of solder balls.

10. The semiconductor package according to claim 1, wherein: The one or more ground planes are separated from the one or more signal pads by one or more dielectric layers.

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