Semiconductor device with effect of reducing VDMOS recovery time

Abstract

The utility model relates to the technical field of MOS (Metal Oxide Semiconductor), and discloses a semiconductor device with an effect of reducing VDMOS (Vertical Double-diffused Metal Oxide Semiconductor) recovery time, which comprises a VDMOS structure formed by horizontally arranging a plurality of MOS cells and extending back and forth, and is characterized in that each MOS cell comprises a drain electrode, a metal source electrode, a grid electrode and a semiconductor epitaxial layer; wherein the semiconductor epitaxial layer comprises a substrate layer, a diffusion layer, a P well layer, an N well layer and a drift layer; the P-well layer comprises a heavily doped P-well layer I, a lightly doped P-well layer I, a heavily doped P-well layer II, a lightly doped P-well layer II and a lightly doped P-well layer III; the N-well layer comprises a first N-well layer, a second N-well layer and a first heavily doped N-well layer; the drift layer comprises a first drift layer and a second drift layer. According to the utility model, the variable concentration injection region is added in the drift region, so that charges can be quickly gathered towards a channel under the action of a grid electric field, the diffusion of the charges into other MOS cells is reduced, and the charge flow in each MOS cell in the VDMOS is ensured to be similar.

Description

Technical Field

[0001] The utility model relates to the technical field of MOS semiconductors, in particular to a semiconductor device with the effect of reducing VDMOS recovery time. Background Art

[0002] VDMOS (Vertical Double-diffused MOS) device is a vertical double diffused MOS (metal oxide semiconductor) device, usually referred to as VDMOSFET. This device is known for its structural characteristics and is mainly used in power electronics applications. VDMOS devices have the advantages of low on-resistance, high withstand voltage, and high-speed switching. They are suitable for occasions that require high-performance power switches, such as power management, electric vehicle control, inverters, etc.

[0003] The existing patent discloses a process method for reducing the recovery time of VDMOS and a VDMOS semiconductor device thereof (publication number CN109659236A), which relates to the field of semiconductor device manufacturing technology. The process method for reducing the recovery time of VDMOS includes thinning, backside injection, high-temperature baking and metal sputtering of the silicon wafer after contact hole etching. The VDMOS semiconductor prepared by the patent disclosure technology will have charge offset and cause the charge conduction flow deviation of each MOS cell in the VDMOS device to be too large, because the charge in the diffusion layer will be affected by the gate electric field of the adjacent MOS cell, which will eventually affect the switch response speed of the VDMOS device. Summary of the invention

[0004] The main technical problem solved by the utility model is to provide a semiconductor device with the effect of reducing the VDMOS recovery time, thereby solving the problems in the above-mentioned background technology.

[0005] To solve the above technical problems, according to one aspect of the utility model, more specifically, a semiconductor device having the effect of reducing the VDMOS recovery time includes a VDMOS structure composed of a plurality of MOS cells arranged horizontally and extending forward and backward, wherein the MOS cell includes a drain, a metal source, a gate, and a semiconductor epitaxial layer;

[0006] The semiconductor epitaxial layer includes a substrate layer, a diffusion layer, a P-well layer, an N-well layer and a drift layer;

[0007] The P-well layer includes a heavily doped P-well layer 1, a lightly doped P-well layer 1, a heavily doped P-well layer 2, a lightly doped P-well layer 2 and a lightly doped P-well layer 3;

[0008] The N-well layer includes an N-well layer 1, an N-well layer 2 and a heavily doped N-well layer 1;

[0009] The drift layer includes a drift layer 1 and a drift layer 2;

[0010] When the gate is connected to the gate voltage, the charges inside the lightly doped P-well layer gather to form a charge channel, the N-well layer is connected to the diffusion layer through the charge channel, and the drain and the metal source are in a conducting state.

[0011] Furthermore, a gate oxide layer is deposited between the surface of the gate and the metal source and the inner surface of the semiconductor epitaxial layer.

[0012] Furthermore, the heavily doped P-well layer 1 (10) and the heavily doped P-well layer 2 (12) are ion-implanted with high-concentration boron ions; and the lightly doped P-well layer 1 (11) and the lightly doped P-well layer 2 (13) are ion-implanted with low-concentration boron ions.

[0013] Furthermore, the N-well layer 1 (5), the drift layer 2 (15), the N-well layer 2 (6), the drift layer 1 (14) and the diffusion layer (9) are ion-implanted with low-concentration phosphorus ions;

[0014] The heavily doped N well layer (7) and substrate layer (8) are ion-implanted with high-concentration phosphorus ions.

[0015] Furthermore, the N-well layer 1, the N-well layer 2 and the heavily doped N-well layer 1 in the N-well layer are all ohmically short-circuited with the metal source electrode.

[0016] Furthermore, the heavily doped N-well layer 1 is in an 'L' shape, wherein the other end of the heavily doped N-well layer 1 is in three-ohm contact with the lightly doped P-well layer.

[0017] Furthermore, the lightly doped P-well layers between adjacent MOS cells are integrated into one, wherein the lightly doped P-well layer suppresses the gate electric field from intervening into the interior of the adjacent MOS cells.

[0018] Furthermore, the drift layer 1 is in ohmic contact with the lightly doped P-well layer 2, and the drift layer 2 is in ohmic contact with the lightly doped P-well layer 3.

[0019] Furthermore, the cross-sectional profile thicknesses of the drift layer 2, N well layer 1, N well layer 2, heavily doped N well layer 1, heavily doped P well layer 1, lightly doped P well layer 1, heavily doped P well layer 2 and lightly doped P well layer 3 are the same.

[0020] The beneficial effects of the semiconductor device with the effect of reducing the VDMOS recovery time of the utility model are as follows:

[0021] 1. The utility model increases a variable concentration injection region in the drift region, so that the charges can be quickly gathered in the channel under the action of the gate electric field, reducing the diffusion of charges into other MOS cells, and ensuring that the charge flow in each MOS cell in the VDMOS is similar.

[0022] 2. In the present invention, after the channel is formed, the drift layer has the effect of collecting charges, so the switching response time of the VDMOS can be greatly shortened.

[0023] 3. The utility model reduces the concentration of minority carriers injected into the drift region during the freewheeling period by arranging a lightly doped P- layer in the P+ region, accelerates the speed at which minority carrier holes are swept out of the drift region during the reverse recovery process, improves the minority carrier storage effect of the PN junction, and improves the reverse recovery characteristics of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] The utility model is further described in detail below with reference to the accompanying drawings and specific implementation methods.

[0025] Figure 1 is a schematic diagram of a VDMOS semiconductor device;

[0026] Figure 2 It is a schematic diagram of a single cell structure of the utility model;

[0027] Figure 3 It is a schematic diagram of the parallel arrangement of the cells of the utility model;

[0028] Figure 4 For this utility model Figure 2 Partial enlarged image.

[0029] In the figure: 1. drain; 2. metal source; 3. gate oxide layer; 4. gate; 5. N-well layer 1; 6. N-well layer 2; 7. heavily doped N-well layer 1; 8. substrate layer; 9. diffusion layer; 10. heavily doped P-well layer 1; 11. lightly doped P-well layer 1; 12. heavily doped P-well layer 2; 13. lightly doped P-well layer 2; 14. drift layer 1; 15. drift layer 2; 16. lightly doped P-well layer 3. DETAILED DESCRIPTION

[0030] The present invention will be described in detail below with reference to the accompanying drawings and in combination with embodiments. It should be noted that the embodiments and features in the embodiments of the present application can be combined with each other without conflict.

[0031] like Figure 1-4As shown, according to one aspect of the utility model, a semiconductor device having the effect of reducing the VDMOS recovery time is provided, comprising a VDMOS structure composed of a plurality of MOS cells arranged horizontally and extending forward and backward, the MOS cell comprising a drain 1, a metal source 2, a gate 4 and a semiconductor epitaxial layer, a gate oxide layer 3 is deposited between the surface of the gate 4 and the metal source 2 and the inner surface of the semiconductor epitaxial layer. Among them, the semiconductor epitaxial layer comprises a substrate layer 8, a diffusion layer 9, a P-well layer, an N-well layer and a drift layer, when the gate 4 is connected to the gate voltage state, the internal charges of the lightly doped P-well layer 316 are gathered and a charge channel is formed, the N-well layer is connected to the diffusion layer 9 through the charge channel, and the drain 1 and the metal source 2 are in a conducting state.

[0032] The P-well layer includes a heavily doped P-well layer 10, a lightly doped P-well layer 11, a heavily doped P-well layer 2 12, a lightly doped P-well layer 2 13 and a lightly doped P-well layer 3 16, the N-well layer includes an N-well layer 15, an N-well layer 2 6 and a heavily doped N-well layer 17, and the drift layer includes a drift layer 14 and a drift layer 2 15 (such as Figure 1 As shown in FIG. 1 , the longitudinally distributed N-well layer 1 5 and the N-well layer 2 6 can reduce the influence of the gate electric field on the N-well layer, thereby avoiding the charge parasitic phenomenon in the N-well layer.

[0033] In this embodiment, the heavily doped P well layer 10, the heavily doped P well layer 2 12, the lightly doped P well layer 3 16, the lightly doped P well layer 1 11 and the lightly doped P well layer 2 13 are all implanted with boron elements by ion implantation to form specific layers. This multi-level design formed by different concentrations can reduce the intervention of the gate electric field on the P well layer and avoid the phenomenon of parasitic charges inside the P well layer.

[0034] The doping concentration of the heavily doped P well layer 10 is 3 to 4.2×10 18 mol / cm 3 .

[0035] The doping concentration of the heavily doped P well layer 12 is 5.3-6.8×10 18 mol / cm 3 .

[0036] The doping concentration of the lightly doped P well layer 11 is 2 to 3.1×10 16 mol / cm 3 .

[0037] The doping concentration of the lightly doped P well layer 13 is 3 to 4.7×10 16 mol / cm 3 .

[0038] In this embodiment, the N well layer 1 5 , the drift layer 2 15 , the N well layer 2 6 , the drift layer 1 14 , the diffusion layer 9 , the heavily doped N well layer 1 7 and the substrate layer 8 are all doped with phosphorus by ion implantation.

[0039] The doping concentrations of the N well layer 15 and the drift layer 2 15 are both 7 to 8.9×10 16 mol / cm 3 .

[0040] The doping concentration of the N well layer 26 and the drift layer 14 is 4.3 to 6.7×10 16 mol / cm 3 .

[0041] The doping concentration of the diffusion layer 9 is 3 to 5×10 16 mol / cm 3 .

[0042] The doping concentration of the heavily doped N-well layer 7 and the substrate layer 8 is 4 to 7.8×10 18 mol / cm 3 .

[0043] The data in this embodiment are only the data from one experiment, including but not limited to the data in this embodiment, all are within the scope of protection of this patent.

[0044] In this embodiment, the N-well layer 1 5, the N-well layer 2 6 and the heavily doped N-well layer 1 7 in the N-well layer are all short-circuited with the metal source electrode 2 in ohms, and the heavily doped N-well layer 1 7 is in an 'L' shape, wherein the other end of the heavily doped N-well layer 1 7 is in ohm contact with the lightly doped P-well layer 3 16 (as shown in FIG. Figure 2 As shown), the heavily doped N-well layer 7 can better guide the charges flowing through the charge channel to the inside of the metal source 2, thereby ensuring the conduction between the metal source 2 and the drain 1.

[0045] In this embodiment, the lightly doped P-well layer 11 between adjacent MOS cells is integrated, wherein the lightly doped P-well layer 11 suppresses the gate electric field from intervening in the adjacent MOS cells, the drift layer 14 is in ohmic contact with the lightly doped P-well layer 2 13, the drift layer 2 15 is in ohmic contact with the lightly doped P-well layer 3 16, and the drift layer 2 15 and the lightly doped P-well layer 3 16 are designed with ohmic contact, so that after a charge channel is formed inside the lightly doped P-well layer 3 16, the charge channel directly connects the drift layer 2 15 and the heavily doped N-well layer 1 7, and because the drift layer has the effect of gathering charge, the switching response time of the VDMOS can be shortened.

[0046] In this embodiment, the cross-sectional profile thickness of the drift layer 2 15, the N well layer 1 5, the N well layer 2 6, the heavily doped N well layer 1 7, the heavily doped P well layer 1 10, the lightly doped P well layer 1 11, the heavily doped P well layer 2 12 and the lightly doped P well layer 3 16 are the same. The design with the same thickness can facilitate the injection of equal amounts of ions, ensuring that the doping concentration error is not too large due to the wanton diffusion of ions during the preparation.

[0047] Of course, the above description is not a limitation of the present invention, and the present invention is not limited to the above examples. Changes, modifications, additions or substitutions made by ordinary technicians in this technical field within the essential scope of the present invention also fall within the protection scope of the present invention.

Claims

1. A semiconductor device having the effect of reducing VDMOS recovery time, characterized in that: It comprises a VDMOS structure composed of a plurality of MOS cells arranged horizontally and extending forward and backward, wherein the MOS cell comprises a drain (1), a metal source (2), a gate (4) and a semiconductor epitaxial layer; The semiconductor epitaxial layer includes a substrate layer (8), a diffusion layer (9), a P-well layer, an N-well layer and a drift layer; The P-well layer includes a heavily doped P-well layer 1 (10), a lightly doped P-well layer 1 (11), a heavily doped P-well layer 2 (12), a lightly doped P-well layer 2 (13) and a lightly doped P-well layer 3 (16); The N-well layer includes an N-well layer 1 (5), an N-well layer 2 (6) and a heavily doped N-well layer 1 (7); The drift layer includes a drift layer 1 (14) and a drift layer 2 (15); When the gate (4) is connected to a gate voltage state, charges are gathered inside the lightly doped P-well layer 3 (16) to form a charge channel, the N-well layer is connected to the diffusion layer (9) through the charge channel, and the drain (1) and the metal source (2) are in a conducting state.

2. The semiconductor device having the effect of reducing VDMOS recovery time according to claim 1, characterized in that: A gate oxide layer (3) is deposited between the surface of the gate electrode (4), the metal source electrode (2), and the inner surface of the semiconductor epitaxial layer.

3. The semiconductor device having the effect of reducing VDMOS recovery time according to claim 1, characterized in that: The N well layer 1 (5), the N well layer 2 (6) and the heavily doped N well layer 1 (7) in the N well layer are all ohmically short-circuited with the metal source electrode (2).

4. The semiconductor device having the effect of reducing VDMOS recovery time according to claim 3, characterized in that: The heavily doped N-well layer 1 (7) is in an 'L' shape, wherein the other end of the heavily doped N-well layer 1 (7) is in ohmic contact with the lightly doped P-well layer 3 (16).

5. The semiconductor device having the effect of reducing VDMOS recovery time according to claim 1, characterized in that: The lightly doped P-well layer (11) between adjacent MOS cells is integrated, wherein the lightly doped P-well layer (11) suppresses the gate electric field from intervening into the interior of the adjacent MOS cells.

6. The semiconductor device having the effect of reducing VDMOS recovery time according to claim 1, characterized in that: The drift layer 1 (14) is in ohmic contact with the lightly doped P-well layer 2 (13), and the drift layer 2 (15) is in ohmic contact with the lightly doped P-well layer 3 (16).

7. The semiconductor device having the effect of reducing VDMOS recovery time according to claim 1, characterized in that: The cross-sectional profile thickness of the drift layer 2 (15), the N well layer 1 (5), the N well layer 2 (6), the heavily doped N well layer 1 (7), the heavily doped P well layer 1 (10), the lightly doped P well layer 1 (11), the heavily doped P well layer 2 (12) and the lightly doped P well layer 3 (16) are the same.

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