Circuit for adaptively reducing power consumption of LDO (Low Dropout Regulator) according to input voltage
By designing a circuit adaptive to the input voltage, using the MOS tube Q2 and the switch control circuit, the problem of high power consumption of LDO in the prior art and inability to reduce power consumption at a small current is solved, and low power consumption operation under different voltage conditions is achieved.
Patent Information
- Application Number
- CN202421750220.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-07-23
- Publication Date
- 2025-05-06
- Estimated Expiration
- 2034-07-23
AI Technical Summary
The prior art has problems with high resistance power consumption and serious heating when reducing LDO power consumption, and cannot realize the current expansion function when the load current is small, resulting in the LDO chip that may burn under high temperature conditions.
A circuit is designed to adaptively reduce LDO power consumption according to the input voltage. Through the MOS tube Q2 and the switch control circuit, the conduction and shutdown of the MOS tube Q2 are controlled according to the magnitude of the input voltage, thereby reducing the current value flowing through the LDO circuit and reducing the power consumption of the LDO circuit.
It realizes the reduction of the current value of the LDO circuit when the input voltage is greater than a certain voltage value, thereby reducing the power consumption of the LDO circuit, avoiding the problems of high resistance power consumption and serious heating, and also reducing the power consumption of the LDO chip under the conditions of small current and large voltage difference.
Smart Images
Figure CN222838378U_ABST
Abstract
Description
[Technical field]
[0001] The utility model relates to the technical field of circuit design, in particular to a circuit capable of adaptively reducing LDO power consumption according to input voltage. [Background technology]
[0002] LDO (Low-dropout regulator) is a voltage conversion chip, and its output end supplies power to the next stage. When designing a circuit, an LDO chip that meets the current requirements will be selected according to the load current. Since the output current of the LDO chip increases in a gradient, the larger the output current capacity, the higher the price. The LDO current parameter mainly considers the power consumption of the LDO to prevent the LDO from overheating and seriously burning the LDO. The power consumption of the LDO is mainly considered from two aspects. One is the voltage difference between the input and output ends of the LDO. When the load current is constant, the greater the voltage difference between the input and output ends, the higher the power consumption of the LDO; the second is the load current of the LDO. When the voltage difference between the input and output ends is constant, the greater the load current, the higher the power consumption of the LDO.
[0003] There are currently plans such as Figure 1 As shown, it is a circuit in the prior art that adaptively reduces the power consumption of LDO. It controls the conduction and cutoff of transistor Q1 according to the output current of LDO chip U1, and can realize the solution of LDO output current expansion. When the voltage drop across the input resistor R1 is greater than the voltage drop between the emitter and the base of transistor Q1, transistor Q1 is turned on to achieve the purpose of current expansion. When the voltage drop across the input resistor R1 is less than the voltage drop between the emitter and the base of transistor Q1, transistor Q1 is cut off and current expansion cannot be achieved.
[0004] Figure 1 Problems and disadvantages of the prior art solutions shown:
[0005] 1. The existing technical solution is to control the conduction and cutoff of the transistor Q1 through the voltage drop of the input resistor R1, that is, the output load current value, so as to achieve the solution of current expansion. This method has great requirements on the resistance value and power consumption of the resistor. If the resistance value is selected to be large, the problem of high resistance power consumption and serious heat generation will occur, and the efficiency of the overall LDO circuit will also be affected; if the resistance value is selected to be small, the function of current expansion can only be achieved when the load current is large, and it cannot be achieved when the current is small.
[0006] 2. The current expansion of the existing technical solution is determined by the load current value. According to the working characteristics of LDO, the power consumption of LDO chip U1 is related to the input-output voltage difference and the load current value. If the input-output voltage difference is large, but the load current is small, when the voltage drop across the input resistor R1 is less than the voltage drop between the emitter and the base of the transistor Q1, the transistor Q1 is cut off and the current cannot be expanded. At this time, the power consumption of LDO chip U1 will still be very large, and the LDO chip U1 may be burned when working under high temperature conditions.
[0007] Therefore, it is necessary to propose a new technical solution to solve the above problems. [Utility Model Content]
[0008] One of the purposes of the utility model is to provide a circuit for adaptively reducing the power consumption of an LDO according to an input voltage. When the input voltage is greater than a certain voltage value, the current value flowing through the LDO circuit can be reduced according to design requirements, thereby reducing the power consumption of the LDO circuit.
[0009] According to one aspect of the utility model, the utility model provides a circuit for adaptively reducing LDO power consumption according to input voltage, comprising: an LDO circuit, whose input end is connected to an input power supply end Vin, and whose output end is connected to an output power supply end Vout; a MOS tube Q2, whose first connection end is connected to the input power supply end Vin, whose second connection end is connected to the output power supply end Vout, and whose control end is connected to a node D; a resistor R4, whose one end is connected to the output power supply end Vout, and whose other end is grounded; a switch control circuit, whose input end is connected to the input power supply end Vin, and whose output end is connected to the node D; when the voltage of the input power supply end Vin is greater than a preset voltage value, the switch control circuit controls the MOS tube Q2 to be turned on; when the voltage of the input power supply end Vin is less than the preset voltage value, the switch control circuit controls the MOS tube Q2 to be turned off.
[0010] Further, the switch control circuit includes a transistor Q1, a transistor Q3, a resistor R1, a resistor R2, a resistor R5, a resistor R7, a resistor R8 and a linear voltage stabilization circuit, the linear voltage stabilization circuit includes a transistor Q4, a resistor R6 and a voltage stabilization diode D1, the first connection end of the transistor Q1 is connected to the input power supply end Vin, the second connection end thereof is connected to the node D via the resistor R1, and the control end thereof is connected to the node C; one end of the resistor R2 is connected to the input power supply end Vin, and the other end thereof is connected to the node C; the first connection end of the transistor Q3 is connected to the node C via the resistor R7, and the second connection end thereof is connected to the node D via the resistor R1, and the control end thereof is connected to the node C. The first connection end of the transistor Q4 is connected to the input power supply end Vin, and the second connection end of the transistor Q4 is connected to the node A; the cathode of the voltage stabilizing diode D1 is connected to the control end of the transistor Q4, and the anode of the voltage stabilizing diode D1 is grounded; one end of the resistor R6 is connected to the first connection end of the transistor Q4, and the other end of the resistor R6 is connected to the control end of the transistor Q4; one end of the resistor R8 is connected to the node B, and the other end of the resistor R8 is grounded; one end of the resistor R5 is connected to the node A, and the other end of the resistor R5 is connected to the node B, and the voltage of the node A is the output voltage of the linear voltage stabilizing circuit.
[0011] Furthermore, the linear voltage stabilization circuit also includes a capacitor C6, and the switch control circuit also includes a capacitor C4 and a capacitor C5, one end of the capacitor C4 is connected to the node A, and the other end thereof is grounded; one end of the capacitor C5 is connected to the node B, and the other end thereof is grounded; one end of the capacitor C6 is connected to the cathode of the voltage stabilizing diode D1, and the other end thereof is grounded.
[0012] Further, the MOS transistor Q2 is an NMOS transistor, and the first connection end, the second connection end and the control end of the MOS transistor Q2 are respectively the drain, the source and the gate of the NMOS transistor; the transistor Q1 is a PNP transistor, and the first connection end, the second connection end and the control end of the transistor Q1 are respectively the emitter, the collector and the base of the PNP transistor; the transistor Q3 is an NPN transistor, and the first connection end, the second connection end and the control end of the transistor Q3 are respectively the collector, the emitter and the base of the NPN transistor; the transistor Q4 is an NPN transistor, and the first connection end, the second connection end and the control end of the transistor Q4 are respectively the collector, the emitter and the base of the NPN transistor.
[0013] Further, when the voltage of the input power supply terminal Vin is greater than a preset voltage value, the output voltage of the linear voltage regulator circuit in the switch control circuit is divided by the resistor R5 and the resistor R8, so that the voltage of the node B is greater than the turn-on voltage of the transistor Q3, the transistor Q3 is turned on, and the transistor Q1 is turned on, thereby controlling the voltage of the node D so that the MOS tube Q2 is turned on; when the voltage of the input power supply terminal Vin is less than the preset voltage value, the output voltage of the linear voltage regulator circuit in the switch control circuit is divided by the resistor R5 and the resistor R8, so that the voltage of the node B is less than the turn-on voltage of the transistor Q3, the transistor Q3 is turned off, and the transistor Q1 is turned off, thereby controlling the voltage of the node D so that the MOS tube Q2 is turned off.
[0014] Furthermore, the selection of the resistor R6 and the voltage stabilizing diode D1 satisfies: when the voltage of the input power supply terminal Vin is greater than a preset voltage value, the output voltage of the linear voltage stabilizing circuit is divided by the resistor R5 and the resistor R8, so that the voltage of the node B is greater than the turn-on voltage of the transistor Q3; when the voltage of the input power supply terminal Vin is less than the preset voltage value, the output voltage of the linear voltage stabilizing circuit is divided by the resistor R5 and the resistor R8, so that the voltage of the node B is less than the turn-on voltage of the transistor Q3; the selection of the resistance values of the resistor R5 and the resistor R8 satisfies: when the voltage of the input power supply terminal Vin is greater than the preset voltage value V1, the divided voltage value on the resistor R8 is greater than the turn-on voltage value of the transistor Q3.
[0015] Furthermore, the circuit for adaptively reducing LDO power consumption according to the input voltage also includes a voltage regulator diode D2, the cathode of the voltage regulator diode D2 is connected to the control end of the MOS tube Q2, and the anode of the voltage regulator diode D2 is connected to the second connection end of the MOS tube Q2; the operating voltage value of the voltage regulator diode D2 is greater than the turn-on voltage value of the MOS tube Q2 and less than the maximum rated voltage value between the gate and the source of the MOS tube Q2; the turn-on voltage value of the MOS tube Q2 is less than the maximum rated voltage value between the gate and the source of the MOS tube Q2.
[0016] Furthermore, the circuit for adaptively reducing LDO power consumption according to input voltage also includes capacitor C1, capacitor C2 and capacitor C3, one end of the capacitor C1 is connected to the input end of the LDO circuit, and the other end thereof is grounded; one end of the capacitor C2 is connected to the output end of the LDO circuit, and the other end thereof is grounded; one end of the capacitor C3 is connected to the output end of the LDO circuit, and the other end thereof is grounded.
[0017] Compared with the prior art, the present invention can reduce the current value flowing through the LDO circuit when the input voltage is greater than a certain voltage value according to design requirements, thereby reducing the power consumption of the LDO circuit.
Brief Description of the Drawings
[0018] In order to more clearly illustrate the technical solutions of the embodiments of the present utility model, the following briefly introduces the drawings required for the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present utility model. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative labor. Among them:
[0019] Figure 1 A circuit for adaptively reducing LDO power consumption in the prior art;
[0020] Figure 2 The schematic diagram of a circuit for adaptively reducing LDO power consumption according to input voltage in one embodiment of the utility model. [Specific implementation method]
[0021] In order to make the above-mentioned purposes, features and advantages of the present invention more obvious and easy to understand, the present invention is further described in detail below in conjunction with the accompanying drawings and specific implementation methods.
[0022] The "one embodiment" or "embodiment" referred to herein refers to a specific feature, structure or characteristic that may be included in at least one implementation of the utility model. The "in one embodiment" that appears in different places in this specification does not all refer to the same embodiment, nor is it a separate or selective embodiment that is mutually exclusive with other embodiments. Unless otherwise specified, the words "coupled", "connected", "connected" and "connected" in this document that indicate electrical connection all mean direct or indirect connection. For example, A is connected to B, which includes both direct electrical connection between A and B and connection between A and B through electrical components or circuits.
[0023] In the description of the present invention, it should be understood that the terms "upper", "lower", "front", "back", "front", "back", "left", "right", "vertical", "perpendicular", "horizontal", "top", "bottom", "inside", "outside", etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present invention.
[0024] Please refer to Figure 2 As shown, it is a schematic diagram of a circuit for adaptively reducing LDO power consumption according to input voltage in one embodiment of the utility model. Figure 2The circuit for adaptively reducing LDO power consumption according to input voltage shown includes LDO circuit U1, MOS tube (metal oxide semiconductor, referred to as field effect tube) Q2, resistor R4 and switch control circuit 210. In one embodiment, the LDO circuit U1 is an LDO chip, which will be referred to as LDO chip in the following text. In other embodiments, the LDO circuit may not be a chip.
[0025] Among them, the input terminal Vin of the LDO chip U1 is connected to the input power terminal Vin, and its output terminal Vout is connected to the output power terminal Vout; the first connection terminal of the MOS tube Q2 is connected to the input power terminal Vin, the second connection terminal thereof is connected to the output power terminal Vout, and the control terminal thereof is connected to the node D; one end of the resistor R4 is connected to the output power terminal Vout, and the other end thereof is grounded; the input terminal of the switch control circuit 210 is connected to the input power terminal Vin, and the output terminal thereof is connected to the node D; when the voltage of the input power terminal Vin (i.e., the input voltage Vin) is greater than a preset voltage value, the switch control circuit 210 controls the MOS tube Q2 to be turned on; when the voltage of the input power terminal Vin (i.e., the input voltage Vin) is less than a preset voltage value, the switch control circuit 210 controls the MOS tube Q2 to be turned off. In this way, the influence of the input voltage value Vin on the LDO power consumption can be considered, so that the LDO power consumption can be reduced even in the case of small current and large voltage difference.
[0026] The switch control circuit 210 includes a transistor Q1 , a transistor Q3 , a resistor R1 , a resistor R2 , a resistor R5 , a resistor R7 , a resistor R8 and a linear voltage regulator circuit 212 . The linear voltage regulator circuit 212 includes a transistor Q4 , a resistor R6 and a voltage regulator diode D1 . Among them, the first connection end of transistor Q1 is connected to the input power supply end Vin, the second connection end thereof is connected to node D via resistor R1, and the control end thereof is connected to node C; one end of resistor R2 is connected to the input power supply end Vin, and the other end thereof is connected to node C; the first connection end of transistor Q3 is connected to node C via resistor R7, the second connection end thereof is grounded, and the control end thereof is connected to node B; the first connection end of transistor Q4 is connected to the input power supply end Vin, and the second connection end thereof is connected to node A; the cathode of voltage stabilizing diode D1 is connected to the control end of transistor Q4, and the anode thereof is grounded; one end of resistor R6 is connected to the first connection end of transistor Q4, and the other end thereof is connected to the control end of transistor Q4; the voltage of node A is the output voltage of linear voltage stabilizing circuit 212. One end of resistor R8 is connected to node B, and the other end thereof is grounded; one end of resistor R5 is connected to node A, and the other end thereof is connected to node B.
[0027] exist Figure 2In the specific embodiment shown, the linear voltage stabilization circuit 212 also includes a capacitor C6, one end of which is connected to the cathode of the voltage stabilization diode D1, and the other end of which is grounded. The switch control circuit 210 also includes a capacitor C4 and a capacitor C5, wherein one end of the capacitor C4 is connected to the node A, and the other end of which is grounded; one end of the capacitor C5 is connected to the node B, and the other end of which is grounded. The capacitors C4, C5, and C6 play a filtering role, filtering out the clutter voltage in the circuit.
[0028] Figure 2 The circuit shown for adaptively reducing LDO power consumption according to input voltage also includes capacitor C1, capacitor C2 and capacitor C3, wherein one end of capacitor C1 is connected to the input terminal Vin of LDO chip U1, and the other end thereof is grounded; one end of capacitor C2 is connected to the output terminal Vout of LDO chip U1, and the other end thereof is grounded; one end of capacitor C3 is connected to the output terminal Vout of LDO chip U1, and the other end thereof is grounded. Capacitor C1 is a filter capacitor of the input terminal Vin of LDO chip U1, which reduces the input ripple voltage value of LDO chip U1. Capacitors C2 and C3 are filter capacitors of the output terminal Vout of LDO chip U1, which reduce the output ripple voltage value of LDO chip U1.
[0029] exist Figure 2 In the specific embodiment shown, the MOS transistor (or field effect transistor) Q2 is an NMOS transistor, and the first connection terminal, the second connection terminal and the control terminal of the MOS transistor Q2 are respectively the drain, the source and the gate of the NMOS transistor; the transistor Q1 is a PNP transistor, and the first connection terminal, the second connection terminal and the control terminal of the transistor Q1 are respectively the emitter, the collector and the base of the PNP transistor; the transistor Q3 is an NPN transistor, and the first connection terminal, the second connection terminal and the control terminal of the transistor Q3 are respectively the collector, the emitter and the base of the NPN transistor; the transistor Q4 is an NPN transistor, and the first connection terminal, the second connection terminal and the control terminal of the transistor Q4 are respectively the collector, the emitter and the base of the NPN transistor.
[0030] The selection of resistor R6 and Zener diode D1 satisfies the following conditions: when the voltage of the input power supply terminal Vin is greater than the preset voltage value V1, the output voltage of the linear voltage regulator circuit 212 (i.e., the voltage of node A) is divided by resistors R5 and R8, so that the voltage of node B is greater than the turn-on voltage of transistor Q3; when the voltage of the input power supply terminal Vin is less than the preset voltage value V1, the output voltage of the linear voltage regulator circuit 212 (i.e., the voltage of node A) is divided by resistors R5 and R8, so that the voltage of node B is less than the turn-on voltage of transistor Q3.
[0031] The resistance values of the resistor R5 and the resistor R8 are selected to satisfy the following requirement: when the voltage of the input power supply terminal Vin is greater than the preset voltage value V1, the voltage division value on the resistor R8 (ie, the voltage of the node B) is greater than the turn-on voltage value of the transistor Q3.
[0032] Figure 2 The circuit for adaptively reducing the power consumption of the LDO according to the input voltage shown in the figure also includes a voltage stabilizing diode D2, the cathode of the voltage stabilizing diode D2 is connected to the control end of the MOS tube Q2, and the anode thereof is connected to the second connection end of the MOS tube Q2. The voltage stabilizing diode D2 plays a role in protecting the MOS tube (or field effect tube) Q2, preventing the voltage between the gate and the source of the MOS tube Q2 from exceeding the rated voltage value (or exceeding the gate and source withstand voltage value of the MOS tube). Specifically, the MOS tube (or field effect tube) Q2 will not be burned out because the voltage between the gate and the source of the MOS tube is too high when the power supply generates a pulse, exceeding the withstand voltage value between the source and the gate of the MOS tube (or field effect tube) Q2. It can also be said that the operating voltage value of the voltage stabilizing diode D2 is greater than the turn-on voltage value of the MOS tube Q2 and less than the maximum rated voltage value between the gate and the source of the MOS tube Q2, wherein the turn-on voltage value of the MOS tube Q2 is less than the maximum rated voltage value between the gate and the source of the MOS tube Q2.
[0033] The following is a detailed introduction Figure 2 The working process of the circuit for adaptively reducing the power consumption of the LDO according to the input voltage is shown.
[0034] When the voltage of the input power supply terminal Vin (i.e., the input voltage Vin) is greater than the preset voltage value V1, the output load current is composed of two parts, one part comes from the LDO circuit (or LDO chip U1), and the other part comes from the field effect transistor Q2. Transistor Q4, resistor R6, capacitor C6 and Zener diode D1 form a linear voltage regulator circuit, and it is necessary to adjust the resistor R6 and the Zener diode D1 to achieve that when the input voltage Vin is greater than the preset voltage value V1, node A is at a high level, and the voltage value of node A is the working voltage of the Zener diode D1 minus the body diode voltage drop of the transistor Q4 (it can also be said that the selection of resistor R6 and Zener diode D1 satisfies: when the voltage of the input power supply terminal Vin is greater than the preset voltage value V1, the output voltage of the linear voltage regulator circuit 212 (i.e., the voltage of node A) passes through resistors R5 and R8. After voltage division, the voltage at node B is greater than the turn-on voltage of transistor Q3; when the voltage at the input power supply terminal Vin is less than the preset voltage value V1, the output voltage of the linear voltage regulator circuit 212 (i.e., the voltage at node A) is divided by resistors R5 and R8, so that the voltage at node B is less than the turn-on voltage of transistor Q3, and at this time, the selection of resistors R5 and R8 needs to meet the following requirements: when the voltage at the input power supply terminal Vin is greater than the preset voltage value V1, the divided voltage value of resistor R8 needs to be greater than the turn-on voltage value of transistor Q3, that is, the voltage at node B is greater than the turn-on voltage value of transistor Q3. The transistor Q3 is turned on. At this time, the voltage at node C is the input voltage Vin minus the voltage drop of the body diode of transistor Q1, and transistor Q1 is turned on. The voltage at node D is the input voltage Vin minus the voltage drop between the emitter and collector of transistor Q1. R1 is a current limiting resistor to prevent the gate current flowing through MOS transistor Q2 from being too large and burning MOS transistor Q2. At this time, the voltage drop between the voltage at node D and the output power supply terminal Vout is greater than the turn-on voltage value of MOS transistor Q2, so MOS transistor Q2 is in the on state. At this time, part of the current at the load end flows through MOS transistor Q2, from The current of the input terminal Vin of the LDO chip U1 is reduced, the power consumption of the LDO chip U1 is reduced, the heating of the LDO chip U1 is alleviated, and the LDO chip U1 is protected. That is to say, when the voltage of the input power terminal Vin is greater than the preset voltage value V1, the output voltage of the linear voltage regulator circuit 212 in the switch control circuit 210 (i.e., the voltage of the node A) is divided by the resistors R5 and R8, so that the voltage of the node B is greater than the turn-on voltage of the transistor Q3, the transistor Q3 is turned on, the transistor Q1 is turned on, and the voltage of the node D is controlled to turn on the MOS tube Q2.
[0035] When the voltage of the input power supply terminal Vin (i.e., the input voltage Vin) is less than the preset voltage value V1, according to the selection of the resistor R6 and the voltage regulator D1, the output voltage of the linear voltage regulator circuit 212 (i.e., the voltage of the node A) is divided by the resistors R5 and R8, so that the voltage of the node B is less than the turn-on voltage of the transistor Q3, and the transistor Q3 is in the cut-off (or off) state. At this time, the voltage drop between the voltage of the node C and the input voltage Vin is less than the body diode voltage of the transistor Q1, so the transistor Q1 is in the off (or off) state, so the voltage drop between the voltage of the node D and the output power supply terminal Vout is less than the turn-on voltage value of the MOS tube Q2, and the MOS tube Q2 is in the off (or off) state. At this time, the load current only flows through the LDO chip U1, and the circuit can work normally. At this time, since the switch control circuit 210 and the MOS tube Q2 do not work, the circuit efficiency will not be affected. That is to say, when the voltage of the input power supply terminal Vin is less than the preset voltage value V1, the output voltage of the linear voltage regulator circuit 212 in the switch control circuit 210 (i.e., the voltage of the node A) is divided by the resistors R5 and R8, so that the voltage of the node B is less than the turn-on voltage of the transistor Q3, the transistor Q3 is turned off, the transistor Q1 is turned off, and the voltage of the node D is controlled to turn off the MOS tube Q2.
[0036] Compared with the prior art, the circuit provided by the utility model for adaptively reducing the power consumption of LDO according to the input voltage has the following beneficial effects:
[0037] 1. The utility model triggers the design circuit (i.e., the switch control circuit 210 and the MOS tube Q2) by the size of the input voltage Vin. When the input voltage Vin is less than the preset voltage value V1, the design circuit does not work and does not affect the overall circuit efficiency.
[0038] 2. The utility model takes into account the influence of the input voltage Vin on the power consumption of the LDO chip, and realizes that the power consumption of the LDO chip can be reduced even in the case of small current and large voltage difference.
[0039] It should be noted that any changes made by those skilled in the art to the specific implementation of the present invention do not deviate from the scope of the claims of the present invention. Accordingly, the scope of the claims of the present invention is not limited to the aforementioned specific implementation.
Claims
1. A circuit for adaptively reducing LDO power consumption according to input voltage, characterized in that: It includes: An LDO circuit, an input end of which is connected to an input power supply end Vin, and an output end of which is connected to an output power supply end Vout; MOS transistor Q2, a first connection end of which is connected to the input power supply end Vin, a second connection end of which is connected to the output power supply end Vout, and a control end of which is connected to the node D; A resistor R4, one end of which is connected to the output power supply terminal Vout, and the other end of which is grounded; a switch control circuit, whose input end is connected to the input power supply end Vin, and whose output end is connected to the node D; When the voltage of the input power terminal Vin is greater than a preset voltage value, the switch control circuit controls the MOS tube Q2 to be turned on; when the voltage of the input power terminal Vin is less than the preset voltage value, the switch control circuit controls the MOS tube Q2 to be turned off.
2. The circuit for adaptively reducing LDO power consumption according to input voltage according to claim 1, characterized in that: The switch control circuit includes a transistor Q1, a transistor Q3, a resistor R1, a resistor R2, a resistor R5, a resistor R7, a resistor R8 and a linear voltage stabilization circuit, and the linear voltage stabilization circuit includes a transistor Q4, a resistor R6 and a voltage stabilization diode D1. The first connection end of the transistor Q1 is connected to the input power supply end Vin, the second connection end thereof is connected to the node D via the resistor R1, and the control end thereof is connected to the node C; one end of the resistor R2 is connected to the input power supply end Vin, and the other end thereof is connected to the node C; the first connection end of the transistor Q3 is connected to the node C via the resistor R7, the second connection end thereof is grounded, and the control end thereof is connected to the node B; the first connection end of the transistor Q4 is connected to the input power supply end Vin, and the second connection end thereof is connected to the node A; the cathode of the voltage stabilizing diode D1 is connected to the control end of the transistor Q4, and the anode thereof is grounded; one end of the resistor R6 is connected to the first connection end of the transistor Q4, and the other end thereof is connected to the control end of the transistor Q4; one end of the resistor R8 is connected to the node B, and the other end thereof is grounded; One end of the resistor R5 is connected to the node A, and the other end thereof is connected to the node B. The voltage of the node A is the output voltage of the linear voltage stabilization circuit.
3. The circuit for adaptively reducing LDO power consumption according to input voltage according to claim 2, characterized in that: The linear voltage stabilization circuit further includes a capacitor C6, The switch control circuit also includes capacitors C4 and C5. One end of the capacitor C4 is connected to the node A, and the other end thereof is grounded; One end of the capacitor C5 is connected to the node B, and the other end thereof is grounded; One end of the capacitor C6 is connected to the cathode of the voltage stabilizing diode D1 , and the other end thereof is grounded.
4. The circuit for adaptively reducing LDO power consumption according to input voltage according to claim 2, characterized in that: The MOS transistor Q2 is an NMOS transistor, and the first connection terminal, the second connection terminal and the control terminal of the MOS transistor Q2 are respectively the drain, the source and the gate of the NMOS transistor; The transistor Q1 is a PNP transistor, and the first connection end, the second connection end and the control end of the transistor Q1 are respectively the emitter, the collector and the base of the PNP transistor; The transistor Q3 is an NPN transistor, and the first connection end, the second connection end and the control end of the transistor Q3 are respectively the collector, the emitter and the base of the NPN transistor; The transistor Q4 is an NPN transistor, and the first connection end, the second connection end and the control end of the transistor Q4 are respectively the collector, the emitter and the base of the NPN transistor.
5. The circuit for adaptively reducing LDO power consumption according to input voltage according to claim 4, characterized in that: When the voltage of the input power supply terminal Vin is greater than a preset voltage value, the output voltage of the linear voltage regulator circuit in the switch control circuit is divided by the resistors R5 and R8, so that the voltage of the node B is greater than the turn-on voltage of the transistor Q3, the transistor Q3 is turned on, the transistor Q1 is turned on, and the voltage of the node D is controlled to turn on the MOS transistor Q2; When the voltage of the input power supply terminal Vin is less than a preset voltage value, the output voltage of the linear voltage regulator circuit in the switch control circuit is divided by the resistors R5 and R8, so that the voltage of the node B is less than the turn-on voltage of the transistor Q3, the transistor Q3 is turned off, the transistor Q1 is turned off, and the voltage of the node D is controlled to turn off the MOS transistor Q2.
6. The circuit for adaptively reducing LDO power consumption according to input voltage according to claim 5, characterized in that: The selection of the resistor R6 and the voltage stabilizing diode D1 satisfies: when the voltage of the input power supply terminal Vin is greater than the preset voltage value, the output voltage of the linear voltage stabilizing circuit is divided by the resistor R5 and the resistor R8, so that the voltage of the node B is greater than the turn-on voltage of the transistor Q3; when the voltage of the input power supply terminal Vin is less than the preset voltage value, the output voltage of the linear voltage stabilizing circuit is divided by the resistor R5 and the resistor R8, so that the voltage of the node B is less than the turn-on voltage of the transistor Q3; The resistance values of the resistor R5 and the resistor R8 are selected to satisfy the following requirement: when the voltage of the input power supply terminal Vin is greater than a preset voltage value V1, the divided voltage value on the resistor R8 is greater than the turn-on voltage value of the transistor Q3.
7. The circuit for adaptively reducing LDO power consumption according to input voltage according to claim 1, characterized in that: It also includes a Zener diode D2, The cathode of the voltage stabilizing diode D2 is connected to the control end of the MOS transistor Q2, and the anode of the voltage stabilizing diode D2 is connected to the second connection end of the MOS transistor Q2; The operating voltage value of the voltage stabilizing diode D2 is greater than the turn-on voltage value of the MOS transistor Q2 and less than the maximum rated voltage value between the gate and the source of the MOS transistor Q2; The turn-on voltage value of the MOS transistor Q2 is less than the maximum rated voltage value between the gate and the source of the MOS transistor Q2.
8. The circuit for adaptively reducing LDO power consumption according to input voltage according to any one of claims 1 to 7, characterized in that: It also includes capacitor C1, capacitor C2 and capacitor C3, One end of the capacitor C1 is connected to the input end of the LDO circuit, and the other end thereof is grounded; One end of the capacitor C2 is connected to the output end of the LDO circuit, and the other end thereof is grounded; One end of the capacitor C3 is connected to the output end of the LDO circuit, and the other end thereof is grounded.