Data transceiving device based on DPU (Data Processing Unit)

Abstract

The utility model provides a data transceiving device based on a DPU (Data Processing Unit), which is applied to a DPU card for connecting main equipment and network equipment, and comprises a first protocol processing module, a second protocol processing module and a storage module, the first protocol processing module is configured to respond to a data receiving and transmitting instruction of the main equipment, perform communication negotiation with the second protocol processing module to determine a data access address corresponding to the data receiving and transmitting instruction in the storage module, and transmit data between the main equipment and the storage module based on a first protocol format and the data access address; the second protocol processing module is configured to transfer data between the network device and the storage module based on a format different from the second protocol and the data access address. Therefore, the protocol conversion processing is unloaded from the main device to the DPU card, so that the CPU resource occupancy rate of the data receiving and transmitting service to the host can be reduced.

Description

Technical Field

[0001] The present application relates to the technical field of data transmission, and in particular to a data transceiver device based on DPU. Background Art

[0002] NVMe over Fabric (NVMe oF for short) is a relatively new protocol specification designed to use NVMe to connect host devices to network storage devices through a network structure. Currently, the fabric transmissions supported and used by NVMe include NVMe-oF using RDMA (also known as NVMe over RDMA), NVMe-oF using Fibre Channel, and NVMe-oF using TCP. Among them, the NVMe over RDMA specification uses remote direct memory access (RDMA) to enable data and memory to be transferred between computers and storage devices over the network.

[0003] Although RDMA is the fastest and lowest-cost transmission mechanism for transmitting data over the network in the existing technology, it needs to be implemented by running RDMA user-mode drivers or kernel-mode drivers. In some application scenarios, when the network bandwidth reaches 50Gbps, 100Gbps or even higher, a large amount of CPU resources are required to specifically process RDMA, NVMe-oF and other protocol stacks.

[0004] In addition, software-implemented NVMe over RDMA can easily cause various storage performance indicators (for example, latency, throughput, IOPS, etc.) to reach performance bottlenecks earlier during disk read and write processes. If you want to achieve the same execution performance as hardware, you need to consume more CPU resources. Utility Model Content

[0005] In view of this, an embodiment of the present application provides a data transceiver device based on DPU, which improves the data transceiver processing efficiency and reduces the CPU resource consumption of the main device for the data transceiver task by offloading the protocol conversion processing in the data transceiver task from the main device to the DPU card.

[0006] The DPU-based data transceiver method of the present application is applied to a DPU card connecting a main device and a network device, and the device includes:

[0007] A first protocol processing module connected to the main device, a second protocol processing module connected to the network device, and a storage module connected to the first protocol processing module and the second protocol processing module; wherein,

[0008] The first protocol processing module is configured to: in response to a data transceiver instruction of the master device, communicate and negotiate with the second protocol processing module to determine a data access address corresponding to the data transceiver instruction in the storage module, and transmit transmission data of the data transceiver instruction between the master device and the storage module based on a first protocol format and the data access address;

[0009] The second protocol processing module is configured to: transmit the transmission data of the data sending and receiving instruction between the network device and the storage module based on a second protocol format different from the first protocol format and the data access address, so as to cooperate with the first protocol processing module to perform the data sending and receiving operation of the data sending and receiving instruction.

[0010] To sum up, the DPU-based data transceiver device provided in the present application offloads the protocol conversion processing from the main device to the DPU card to execute the data transceiver (read and write) task of the main device, which not only reduces the CPU resources of the main device required to execute the data transceiver task, but also has the advantages of simple hardware architecture design and low hardware implementation cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the embodiments of the present disclosure. For ordinary technicians in this field, other drawings can also be obtained based on these drawings.

[0012] Figure 1 This is a system architecture diagram of a DPU-based data transceiver device according to an exemplary embodiment of the present application.

[0013] Figure 2 This is a system architecture diagram of a DPU-based data transceiver device according to another exemplary embodiment of the present application.

[0014] Figure 3 Based on Figure 1 or Figure 2 An exemplary flow chart of a data transceiving method performed by a DPU-based data transceiving device.

[0015] Figure 4 Based on Figure 1 or Figure 2 Another exemplary flow chart of a data transceiving method performed by a DPU-based data transceiving device.

[0016] Figure 5 Based on Figure 1 or Figure 2Another exemplary flow chart of a data transceiving method performed by a DPU-based data transceiving device. DETAILED DESCRIPTION

[0017] In order to enable those skilled in the art to better understand the technical solutions in the embodiments of the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. All other embodiments obtained by ordinary technicians in this field based on the embodiments in the embodiments of the present application should fall within the scope of protection of the embodiments of the present application.

[0018] NVMe over Fabrics, also known as NVMe oF, is a relatively new protocol specification designed to connect hosts to network storage through a network fabric using NVMe. Compared to the traditional iSCSI protocol for network storage access, NVMe-oF supports organizations to create ultra-high-performance storage networks with latency comparable to direct-attached storage. As a result, fast storage devices can be shared between servers on demand. NVMe-oF can be seen as an alternative to SCSI or iSCSI over Fibre Channel, with the advantages of lower latency, higher I / O rates, and better productivity.

[0019] Currently, NVMe supports and uses three types of structural transmissions: NVMe-oF using RDMA (or NVMe over RDMA), NVMe-oF using Fibre Channel, and NVMe-oF using TCP. Among them, the NVMe over RDMA specification enables data and memory to be transferred between computers and storage devices over the network by using remote direct memory access (RDMA).

[0020] Specifically, RDMA (Remote Direct Memory Access) technology, i.e. remote direct memory access, is a high-performance network communication technology. It can use dedicated hardware on the network adapter, such as the RDMA engine on the network card, to bypass the operating system kernel and directly transmit data under the network transport layer. This direct memory access method can reduce the delay of data transmission and the load of the CPU, improve the efficiency of network communication, and is currently the fastest and lowest-cost data transmission mechanism for transmitting data over the network. However, this data transmission mechanism needs to be implemented by running the RDMA user-mode driver or kernel-mode driver. When the network bandwidth reaches 50Gbps, 100Gbps or even higher, it is necessary to consume CPU resources in the main device to specifically process RDMA, NVMe-oF and other protocol stacks.

[0021] Furthermore, software-implemented NVMe over RDMA can easily cause various storage performance indicators (such as latency, throughput, IOPS, etc.) to reach performance bottlenecks earlier during the data reading and writing process. If you want to achieve the same execution performance as hardware, you need to consume more CPU resources.

[0022] In order to solve the performance problems caused by the software-based implementation of NVMe over RDMA, the embodiments of the present disclosure propose a semi-unload system and implementation scheme of NVMe over RDMA (Initiator), which can reduce the occupancy rate of the CPU resources of the main device for data transmission and reception services, while taking into account the complexity of hardware implementation. The specific implementation of each embodiment of the present application will be described in detail below in conjunction with the accompanying drawings.

[0023] Figure 1 FIG. 1 is a schematic diagram of the hardware architecture of a data transceiver device based on a DPU according to an exemplary embodiment of the present application. Figure 1 As shown, the data transceiver device 100 is applied to a DPU (Data Processing Unit) card 130 connecting a main device 110 and a network device 130 and connecting a standby device 110 and a network device 120 .

[0024] The host device 110 may be any suitable device for storing information, data, programs and / or any other suitable type of content, including but not limited to: a storage system device, a server cluster, a cloud server, etc.

[0025] In some embodiments, the master device 110 may include a host memory 112 for storing the data sent and received by the master device 110. For example, the host memory 112 may include, but is not limited to, a DDR memory (double data rate synchronous dynamic random access memory).

[0026] The network device 130 can be connected to the main device 110 for communication and interaction of network data transmission, and the network device 130 may include but is not limited to: storage system equipment, server clusters, cloud servers, etc. It should be noted that the number of network devices 130 is not limited to the number shown in the drawings, and can be increased or decreased according to actual needs, and this application does not limit this.

[0027] The DPU card 120 can be respectively connected to the main device 110 and the network device 130 for communication, so as to read data from the main device 110 and send it to the network device 130, or receive data from the network device 130 and write it to the main device 110, thereby realizing the data sending and receiving operation of the main device 110.

[0028] For example, in Figure 2In the data transceiver device 200 shown, the DPU card 220 can be plugged into the main device 210 through the PCIE (Peripheral Component Interconnect Express) module 221, so that the DPU card 220 becomes a peripheral device of the main device 210. In addition, the DPU card 220 can be connected to the network device 230 through the MAC (Medium Access Control) module 229 to provide data transmission operations between the main device 210 and the network device 230, wherein the MAC module 229 is responsible for performing the conversion between the RDMA data format and the MAC format to perform the network data transmission and reception operations.

[0029] In some embodiments, the DPU card 120 may include a first protocol processing module 122 connected to the main device 110, a second protocol processing module 124 connected to the network device 130, a coprocessor 128 connected to the first protocol processing module 122 and the second protocol processing module 124, and a storage module 126 connected to the first protocol processing module 122, the second protocol processing module 124, and the coprocessor 128.

[0030] Combined with reference Figure 1 and Figure 2 The first protocol processing module 122 may be an NVMe oF protocol processing module 222, and the second protocol processing module 124 may be an RDMA protocol processing module 224, so as to implement conversion processing between NVMe oF and RDMA based on the hardware level.

[0031] The coprocessor 128 may include an embedded soft core (e.g., microblaze soft core 228), which is configured to convert the NVMe format commands issued by the master device 210 into RDMA format commands, and notify the RDMA protocol processing module 224 to establish a link with the RDMA protocol processing module 224, and configure the established link information into the NVMe oF protocol processing module 222.

[0032] The storage module 126 may include a DDR module (double data rate synchronous dynamic random access memory) 226, wherein the NVMe oF protocol processing module 222, the RDMA protocol processing module 224 and the microblaze soft core 228 may access the DDR module 226 to achieve data sharing. The NVMe oF protocol processing module 222 may move data between the host device 210 (host memory 212), the RDMA protocol processing module 224 and the DDR module 226 according to the execution command of the microblaze soft core 228.

[0033] It should be noted that the technical solution of this embodiment can be implemented in any type of accelerator card, not limited to the DPU card shown in the accompanying drawings. Figure 1 The DPU card 120 is equivalently replaced by an FPGA card to implement the data transceiver device of each embodiment of the present disclosure.

[0034] The following will be combined Figures 3 to 5 , the description is based on the above Figure 1 or Figure 2 The data transceiving devices 100 and 200 shown here perform a data transceiving method.

[0035] like Figure 3 As shown, according to an embodiment of the present disclosure, a data transceiving method 300 performed by a DPU-based data transceiving device 100, 200 is provided, which mainly includes the following steps:

[0036] Step 302: In response to the data receiving and sending instruction of the master device, the first protocol processing module communicates and negotiates with the second protocol processing module to determine the data access address corresponding to the data receiving and sending instruction in the storage module.

[0037] In some embodiments, the first protocol processing module 122 can obtain data sending and receiving instructions from the main device 110, and notify the coprocessor 128 to execute the data sending and receiving operations corresponding to the data sending and receiving instructions, so that the coprocessor 128 can initiate a link request to the second protocol processing module 124, and negotiate to determine the data access address in the storage module 126 corresponding to the data sending and receiving instructions.

[0038] In some embodiments, the data transceiving instruction may include a data sending instruction or a data receiving instruction.

[0039] In some embodiments, the coprocessor 128 may respond to a data transceiver instruction of the master device 110, convert the data transceiver instruction from a first protocol format to a second protocol format, and send the data instruction in the second protocol format to the second protocol processing module, so as to cooperate with the second protocol processing module to determine the data access address in the storage module corresponding to the data transceiver instruction.

[0040] For example, refer to Figure 2 The microblaze soft core 228 converts the data receiving and sending instructions of the main device 210 from the NVMe format to the RDMA format, and sends it to the RDMA protocol processing module 224, so that the RDMA protocol processing module 224 establishes a link with the RDMA protocol processing module 224 to negotiate and determine the data access address corresponding to the data receiving and sending instructions in the DDR module 226.

[0041] Step 304: Transmitting the transmission data of the data receiving and sending instructions between the main device and the storage module through the first protocol processing module based on the first protocol format and the data access address; transmitting the transmission data of the data receiving and sending instructions between the network device and the storage module through the second protocol processing module based on the second protocol format different from the first protocol format and the data access address, so as to collaboratively execute the data receiving and sending operations of the data receiving and sending instructions.

[0042] In some embodiments, when the data receiving and sending instructions are data sending instructions, the first protocol processing module 122 can obtain the transmission data of the data sending instruction from the host memory 112 of the main device 110 based on the first protocol format and the data access address, and store it in the storage module 126, and then the second protocol processing module 124 can read the transmission data of the data sending instruction from the storage module 126 based on the second protocol format and the data access address, and send it to the network device 130.

[0043] For example, refer to Figure 2 The NVMe oF protocol processing module 222 can obtain the transmission data of the data sending instruction from the host memory 212 based on the NVMe oF protocol and the data access address, and store it in the DDR module 226. Then, the RDMA protocol processing module 224 can read the transmission data of the data sending instruction from the DDR module 226 based on the RDMA protocol format and the data access address, and send it to the network device 230.

[0044] In some embodiments, when the data sending and receiving instruction is a data receiving instruction, the second protocol processing module 124 can receive the transmission data of the data receiving instruction from the network device 130 based on the second protocol format and the data access address, and store it in the storage module 126. Then, the first protocol processing module 122 can obtain the transmission data of the data receiving instruction from the storage module 126 based on the first protocol format and the data access address, and write it into the host memory 112 of the master device 110.

[0045] For example, refer to Figure 2 The RDMA protocol processing module 224 can obtain the transmission data of the data receiving instruction from the network device 230 based on the RDMA protocol format and the data access address, and store it in the DDR module 226. Then, the NVMe oF protocol processing module 222 can read the transmission data of the data receiving instruction from the DDR module 226 based on the NVMe oF protocol and the data access address, and write it into the host memory 212.

[0046] In some embodiments, the NVMe oF protocol processing module 222 also includes an access router 2226, wherein the DMA engine 2224, the microblaze soft core 228, and the RDMA protocol processing module 224 can respectively access the DDR module 226 via the access router 2226 to perform data access operations.

[0047] To sum up, the DPU-based data transmission and reception method of this embodiment, by plugging a DPU card into the main device, offloads NVMe-oF and the corresponding RDMA protocol from the main device to the DPU card for processing, which can greatly reduce the CPU resource consumption of the main device in high-bandwidth application scenarios and improve the utilization rate of the CPU resources of the main device.

[0048] Furthermore, this embodiment sets a MAC module, a first protocol processing module, and a second protocol processing module in the DPU card to implement the conversion processing of the network protocol, NVMe-oF, and RDMA in the DPU card in a hardware-based form, and uses a coprocessor to be responsible for the software control part of the data sending and receiving service. In this way, it can not only simplify the hardware design complexity in the DPU card to reduce the hardware implementation cost, but also obtain a larger data bandwidth and lower data processing delay, thereby improving the data sending and receiving processing efficiency.

[0049] In addition, the present embodiment adopts the microblaze soft core to replace the SOC, which can realize the programmability of the microprocessor in hardware, so as to facilitate the transplantation of the technical solution of the present embodiment to any type of acceleration card for implementation.

[0050] Figure 4 The method 400 of this embodiment shows the processing flow of executing the data sending instruction of the master device through the DPU card, which mainly includes the following steps:

[0051] Step 402: Obtain a data sending instruction from the master device through the first protocol processing module.

[0052] In some embodiments, the NVMe oF protocol processing module 222 includes a shared register 2222.

[0053] The master device 210 may store the data to be sent into the host memory 212 of the master device 210 , and send a corresponding data sending instruction to the shared register 2222 .

[0054] Step 404: In response to the data sending instruction of the master device, the coprocessor communicates with the second protocol processing module to determine the data access address in the storage module corresponding to the data sending instruction.

[0055] In some embodiments, the shared register 2222 can be used to notify the microblaze soft core 228 to communicate and negotiate with the RDMA protocol processing module 224 according to the data sending instruction of the master device 210 to determine the data access address in the DDR module 226 corresponding to the data sending instruction.

[0056] Step 406: trigger the first protocol processing module through the coprocessor, read the transmission data of the data sending instruction from the main device based on the first protocol format and the data access address, and write the transmission data into the storage module.

[0057] In some embodiments, the NVMe oF protocol processing module 222 includes a DMA (Direct Memory Access) engine 2224.

[0058] The microblaze soft core 228 can respond to the determination result of the data access address and notify the DMA engine 2224 to take the data in the host memory 212. The DMA engine 2224 can read the transmission data of the data sending instruction from the host memory 212 based on the NVMe oF protocol format and the data access address, and store it in the specified area of ​​the DDR module 226, that is, the storage area in the DDR module 226 corresponding to the data access address.

[0059] Step 408: Through the coprocessor, in response to the determination result that the transmission data has been written into the storage module, trigger the second protocol processing module to read the transmission data from the storage module based on the second protocol format and the data access address, and send the transmission data to the network device.

[0060] In some embodiments, the microblaze soft core 228 can respond to the determination result that the transmission data of the data sending instruction has been stored in the DDR module 226, and notify the RDMA protocol processing module 224 to take the data in the DDR module 226. The RDMA protocol processing module 224 reads the transmission data of the data sending instruction from the DDR module 226 based on the RDMA protocol and the data access address, and converts the transmission data from the RDMA protocol format to the MAC format via the MAC module 229, and then sends it to the network device 230.

[0061] Figure 5 The method 500 of this embodiment shows the processing flow of executing the data receiving instruction of the main device through the DPU card, which mainly includes the following steps:

[0062] Step 502: Obtain a data receiving instruction from the master device through the first protocol processing module.

[0063] In some embodiments, the NVMe oF protocol processing module 222 includes a shared register 2222.

[0064] The master device 210 may send a data receiving instruction to the shared register 2222 of the NVMe oF protocol processing module 222 to inform that external network data needs to be requested.

[0065] Step 504: In response to the data receiving instruction, the coprocessor communicates with the second protocol processing module to determine the data access address in the storage module corresponding to the data receiving instruction.

[0066] In some embodiments, the microblaze soft core 228 can be notified to communicate and negotiate with the RDMA protocol processing module 224 through the shared register 2222 according to the data receiving instruction of the master device 210 to determine the data access address corresponding to the data receiving instruction in the DDR module 226.

[0067] Step 506: trigger the second protocol processing module through the coprocessor to read the transmission data of the data receiving instruction from the network device based on the second protocol format and the data access address, and write the transmission data into the storage module.

[0068] In some embodiments, the microblaze soft core 228 can respond to the determination result of the data access address to notify the RDMA protocol processing module 224 to receive external network data. The RDMA protocol processing module 224 can obtain the transmission data of the data receiving instruction from the network device 230 via the MAC module 229, wherein the MAC module 229 is responsible for converting the transmission data received from the network device 230 from the MAC format to the RDMA format, and sending it to the RDMA protocol processing module 224. The RDMA protocol processing module 224 writes the transmission data into the DDR module 226 based on the second protocol format and the data access address.

[0069] Step 508: In response to the determination result that the transmission data has been written into the storage module, the coprocessor triggers the DMA engine to read the transmission data from the storage module based on the first protocol format and the data access address, and write the transmission data into the host device.

[0070] In some embodiments, the microblaze soft core 228 can respond to the determination result that the transmission data of the data receiving instruction has been stored in the DDR module 226, and notify the DMA engine 2224 to obtain the transmission data of the data receiving instruction from the DDR module 226 based on the NVMe oF protocol format and the data access address and store it in the host memory 212 of the master device 210.

[0071] In summary, through the embodiments of the present application, by inserting a DPU card in the main device, using the NVMe-oF protocol processing module and the RDMA protocol processing module in the DPU card, the conversion processing of the NVMe-oF protocol and the corresponding RDMA protocol is performed in a hardware-based manner, and by setting the microblaze soft core in the DPU card, the execution logic of the data transceiver service is controlled in a software-based manner. Thus, the present disclosure implements the semi-unloading of the NVMe over RDMA protocol by combining hardware with software, which can reduce the CPU resource consumption of the main device by NVMe over RDMA, especially in high-bandwidth application scenarios, which can greatly reduce the CPU consumption of the data transceiver service for the main device, reduce the processing delay of NVMe command requests, and increase data throughput. In addition, the hardware design complexity of the design scheme disclosed in the present disclosure is low, and it has a low hardware implementation cost.

[0072] It should be pointed out that, according to the needs of implementation, the various components / steps described in the embodiments of the present disclosure can be split into more components / steps, or two or more components / steps or partial operations of components / steps can be combined into new components / steps to achieve the purpose of the embodiments of the present disclosure.

[0073] The above implementation methods are only used to illustrate the embodiments of the present disclosure, and are not limitations of the embodiments of the present disclosure. Ordinary technicians in the relevant technical field may make various changes and modifications without departing from the spirit and scope of the embodiments of the present disclosure. Therefore, all equivalent technical solutions also belong to the scope of the embodiments of the present disclosure. The scope of patent protection of the embodiments of the present disclosure should be defined by the claims.

Claims

1. A data transceiver device based on DPU, characterized in that: A DPU card used to connect a main device and a network device, the device comprising: A first protocol processing module connected to the main device, a second protocol processing module connected to the network device, and a storage module connected to the first protocol processing module and the second protocol processing module; wherein, The first protocol processing module is configured to: in response to a data transceiver instruction of the master device, communicate and negotiate with the second protocol processing module to determine a data access address corresponding to the data transceiver instruction in the storage module, and transmit transmission data of the data transceiver instruction between the master device and the storage module based on a first protocol format and the data access address; The second protocol processing module is configured to: transmit the transmission data of the data sending and receiving instruction between the network device and the storage module based on a second protocol format different from the first protocol format and the data access address, so as to cooperate with the first protocol processing module to perform the data sending and receiving operation of the data sending and receiving instruction.

2. The device according to claim 1, characterized in that The device includes a coprocessor, and the first protocol processing module includes a shared register; wherein, The shared register is configured to obtain a data receiving and sending instruction of the master device and send the instruction to the coprocessor; The coprocessor is configured to communicate with the second protocol processing module in response to the data transceiving instruction to determine a data access address in the storage module corresponding to the data transceiving instruction.

3. The device according to claim 2, characterized in that The data receiving and sending instruction obtained from the master device has a first protocol format; The coprocessor is configured to: in response to the data transceiving instruction, convert the data transceiving instruction from the first protocol format to the second protocol format, and send the data instruction in the second protocol format to the second protocol processing module, so as to cooperate with the second protocol processing module to determine the data access address in the storage module corresponding to the data transceiving instruction.

4. The device according to claim 2, characterized in that The data transceiver instruction includes a data sending instruction, and the first protocol processing module includes a DMA engine; Wherein, the coprocessor is configured as: triggering the DMA engine to read the transmission data of the data sending instruction from the master device based on the first protocol format and the data access address, and write the transmission data into the storage module; In response to the determination result that the transmission data has been written to the storage module, the second protocol processing module is triggered to read the transmission data from the storage module based on the second protocol format and the data access address, and send the transmission data to the network device.

5. The device according to claim 2, characterized in that The data transceiver instruction includes a data receiving instruction, and the first protocol processing module includes a DMA engine; Wherein, the coprocessor is configured as: triggering the second protocol processing module to read the transmission data of the data receiving instruction from the network device based on the second protocol format and the data access address, and write the transmission data into the storage module; In response to a determination result that the transmission data has been written to the storage module, the DMA engine is triggered to read the transmission data from the storage module based on the first protocol format and the data access address, and write the transmission data to the master device.

6. The device according to any one of claims 1, 4 and 5, characterized in that: The first protocol processing module includes an NVMe oF protocol processing module.

7. The device according to any one of claims 1, 4 and 5, characterized in that: The second protocol processing module includes an RDMA protocol processing module, and the apparatus includes a MAC module connecting the RDMA protocol processing module and the network device, which is configured as follows: The transmission data of the data receiving and sending instruction is interchanged between the RDMA protocol format and the MAC protocol format, so as to transmit the transmission data of the data receiving and sending instruction between the network device and the RDMA protocol processing module.

8. The device according to any one of claims 1, 4 and 5, characterized in that: The host device includes a host memory; Wherein, the first protocol processing module is configured as follows: Based on the first protocol format and the data access address, transmission data of the data receiving and sending instruction is transmitted between the host memory and the storage module.

9. The device according to claim 2, characterized in that The coprocessor includes an access router connecting a protocol coprocessor, a DMA engine, a data transceiver module and the storage module, and is configured as follows: An access path to the storage module is provided so that the protocol coprocessor, the DMA engine, and the data transceiver module can access the storage module via the access router.

10. The device according to claim 9, characterized in that The protocol coprocessor includes a Microblaze soft core processor.

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