Array substrate and display panel

Abstract

The utility model discloses an array substrate and a display panel. The array substrate comprises a data line and a test transistor. The data line comprises a first data line and a second data line; the test transistor comprises a first electrode and a second electrode; the first data line is electrically connected with the first electrode, the second data line is electrically connected with the second electrode, and the second data line extends from a non-display area of the array substrate to a display area of the array substrate; the first data line is configured to transmit a test voltage to the first electrode, the test transistor is configured to transmit the test voltage from the first electrode to the second data line during conduction, and the second data line is configured to transmit the test voltage to the display area. The array substrate provided by the utility model has more testable items, and can detect the test transistor in advance before a lighting test, so that the display panel can be better tested.

Description

Technical Field

[0001] The utility model relates to the field of display technology, and in particular to an array substrate and a display panel. Background Art

[0002] With the rapid development of display technology, display panels formed by organic light emitting diodes are increasingly widely used.

[0003] In order to ensure the reliability of the display panel, the display panel needs to be tested. Generally, a test circuit is set to perform a lighting test on the light-emitting elements of the display panel. However, the existing display panel has the problem that it cannot be tested well. Utility Model Content

[0004] The utility model provides an array substrate and a display panel to solve the problem that the display panel cannot be well tested.

[0005] According to one aspect of the present invention, an array substrate is provided, the array substrate comprising:

[0006] Data lines, the data lines comprising a first data line and a second data line;

[0007] A test transistor, the test transistor comprising a first electrode and a second electrode; the first data line is electrically connected to the first electrode, the second data line is electrically connected to the second electrode, and the second data line extends from the non-display area of ​​the array substrate to the display area of ​​the array substrate; the first data line is configured to transmit a test voltage to the first electrode, the test transistor is configured to transmit the test voltage from the first electrode to the second data line when turned on, and the second data line is configured to transmit the test voltage to the display area.

[0008] Optionally, the test transistor comprises an active layer;

[0009] The first electrode is connected to the active layer, and the second electrode is connected to the active layer.

[0010] Optionally, the array substrate further includes:

[0011] A control signal line is connected to the test transistor, and the control signal line is configured to control the on or off of the test transistor according to a control signal on the control signal line.

[0012] Optionally, the test transistor further includes a third electrode; and the control signal line is electrically connected to the third electrode.

[0013] Optionally, an extension direction of the control signal line intersects with an extension direction of the data line.

[0014] Optionally, the array substrate further includes:

[0015] A first connection portion is connected between the control signal line and the third electrode.

[0016] Optionally, the array substrate further comprises: a substrate;

[0017] The first electrode and the second electrode are located on one side of the substrate;

[0018] The data line is located at a side of the first electrode away from the substrate, and the control signal line is located at a side of the data line away from the substrate.

[0019] Optionally, the array substrate further includes:

[0020] a substrate; the first electrode and the second electrode are located on one side of the substrate, and the data line is located on a side of the first electrode away from the substrate;

[0021] At least one voltage line, the voltage line is electrically connected to the first electrode of the test transistor; the extension direction of the voltage line intersects with the extension direction of the data line; the voltage line is located on a side of the data line away from the substrate.

[0022] Optionally, the array substrate comprises three voltage lines; the arrangement direction of the three voltage lines is the same as the extension direction of the data lines;

[0023] Different voltage lines are connected to different test transistors.

[0024] Optionally, the array substrate further includes a pixel circuit, and the pixel circuit is located in the display area;

[0025] The second data line is connected to the pixel circuit.

[0026] Optionally, the pixel circuit includes a data writing transistor, a driving transistor and a storage capacitor;

[0027] A first electrode of the data writing transistor is electrically connected to the second data line, and a second electrode of the data writing transistor is connected to the driving transistor;

[0028] The first electrode of the driving transistor is connected to a first power supply;

[0029] A first electrode of the storage capacitor is connected to the first power source, and a second electrode of the storage capacitor is connected to a control electrode of the data writing transistor.

[0030] According to another aspect of the present invention, a display panel is provided. The display panel includes the array substrate described in any embodiment of the present invention.

[0031] The technical solution of the embodiment of the utility model is to set the data line to include a first data line and a second data line, the first data line is electrically connected to the first electrode, and the second data line is electrically connected to the second electrode. While testing the devices in the pixel circuit of the array substrate, it is possible to detect whether the test transistor has a fault. In this way, the array substrate provided by the embodiment of the utility model has more testable items, so before the display panel formed by the array substrate is tested for lighting, the array substrate provided by the embodiment of the utility model can be used to test the test transistor, and when a problem occurs in the lighting test, it can be better traced. Therefore, the display panel made of the array substrate of this embodiment can be better tested.

[0032] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present utility model, nor are they intended to limit the scope of the present utility model. Other features of the present utility model will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0034] Figure 1 It is a structural schematic diagram of an array substrate provided by an embodiment of the utility model;

[0035] Figure 2 yes Figure 1 Cross-sectional view along the direction a1-a2;

[0036] Figure 3 This is a structural schematic diagram of another array substrate provided by an embodiment of the utility model;

[0037] Figure 4 yes Figure 3 A cross-sectional view along the direction a3-a4;

[0038] Figure 5 This is a structural schematic diagram of another array substrate provided by an embodiment of the utility model;

[0039] Figure 6 yes Figure 5 A cross-sectional view along the direction a5-a6;

[0040] Figure 7 It is a structural schematic diagram of a pixel circuit provided by an embodiment of the utility model;

[0041] Figure 8 It is a structural schematic diagram of a display panel provided by an embodiment of the utility model. DETAILED DESCRIPTION

[0042] In order to enable those skilled in the art to better understand the solution of the utility model, the technical solution in the embodiment of the utility model will be clearly and completely described below in conjunction with the drawings in the embodiment of the utility model. Obviously, the described embodiment is only a part of the embodiment of the utility model, not all of the embodiments. Based on the embodiment of the utility model, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the utility model.

[0043] It should be noted that the terms "first", "second", etc. in the specification and claims of the utility model and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the utility model described here can be implemented in an order other than those illustrated or described here. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0044] As mentioned in the background technology, the existing detection scheme has the problem of not being able to detect the display panel well. The inventor has found through research that the reason for this problem is that the display panel includes a pixel circuit and a light-emitting element, the pixel circuit is connected to the light-emitting element, and the pixel circuit can generate a driving current so that the light-emitting element emits light in response to the driving current. The display panel may include a data line and a test switch, and the data line is connected to the pixel circuit in the same column. The data line is connected to the first pole of the test switch, and the power line is connected to the second pole of the test switch. During the test, the test switch is turned on, so that the data voltage on the power line can be transmitted to the data line, and the data voltage on the data line can be transmitted to the pixel circuit, and the pixel circuit generates a driving current according to the data voltage to light up the light-emitting element, thereby detecting whether the light-emitting element can emit light normally.

[0045] The display panel may include an array substrate, and the array substrate includes a pixel circuit. In the preparation process of the array substrate, a complete light-emitting element is not prepared. In the related art, when the device in the pixel circuit is tested, the voltage is directly transmitted from the external device to the data line, and the data line can directly transmit the voltage to the pixel circuit, so that the voltage does not need to be transmitted through the test switch. In the array test phase, the test switch cannot be tested. When the light-emitting element is subsequently tested for lighting, if the light-emitting element cannot be lit, it is difficult to determine whether it is a problem with the test switch or the light-emitting element, that is, it is difficult to determine the cause of the display abnormality and difficult to trace the problem. The display panel has the problem of not being able to be tested well.

[0046] In view of the above technical problems, the present invention provides an array substrate. Figure 1 is a schematic diagram of the structure of an array substrate provided by an embodiment of the utility model, with reference to Figure 1 , the array substrate comprises:

[0047] Data lines 110, the data lines 110 include a first data line 111 and a second data line 112;

[0048] A test transistor 120, the test transistor 120 includes a first electrode 121 and a second electrode 122; the first data line 111 is electrically connected to the first electrode 121, the second data line 112 is electrically connected to the second electrode 122, and the second data line 112 extends from the non-display area NA of the array substrate to the display area AA of the array substrate; the first data line 111 is configured to transmit a test voltage to the first electrode 121, the test transistor 120 is configured to transmit the test voltage from the first electrode 121 to the second data line 112 when turned on, and the second data line 112 is configured to transmit the test voltage to the display area AA.

[0049] Among them, the data line 110 can be connected to the pixel circuit in the array substrate, and the data line 110 can provide a data voltage and a test voltage for the pixel circuit. The pixel circuit can be a 2T1C pixel circuit and its deformation, or a 7T1C pixel circuit and its deformation. The 2T1C pixel circuit may include a driving transistor, a data writing transistor and a storage capacitor. The 7T1C pixel circuit may include a driving transistor, a data writing transistor, a storage capacitor, a threshold compensation transistor, a first initialization transistor, a second initialization transistor, a first light emission control transistor and a second light emission control transistor. The pixel circuit is, for example, located in the display area AA of the array substrate. The first data line 111 and the second data line 112 have the same extension direction, for example, the first data line 111 and the second data line 112 extend along the first direction Y. For example, the second data line 112 is connected to the pixel circuit. The array substrate may include a plurality of test transistors 120 and a plurality of data lines 110, for example, the data lines 110 and the test transistors 120 are arranged in a one-to-one correspondence, for example, one data line 110 corresponds to one column of pixel circuits.

[0050] The test transistor 120 may be a switch transistor, the first electrode 121 of the test transistor 120 may be a source, and the second electrode 122 of the test transistor 120 may be a drain; or the first electrode 121 of the test transistor 120 may be a drain, and the second electrode 122 of the test transistor 120 may be a source.

[0051] Specifically, the data line 110 includes a first data line 111 and a second data line 112, the first data line 111 is electrically connected to the first electrode 121, and the second data line 112 is electrically connected to the second electrode 122. In the array test phase, for example, when testing the device in the pixel circuit of the array substrate, the test transistor 120 is turned on, and the test voltage is transmitted from the external device to the first data line 111, and the test voltage on the first data line 111 can be transmitted to the first electrode 121, and the test voltage on the first electrode 121 is transmitted to the second electrode 122, and the test voltage on the second electrode 122 can be transmitted to the second data line 112, and the second data line 112 transmits the test voltage to the display area AA. Then, the test voltage can be transmitted to the pixel circuit of the display area AA, and the device in the pixel circuit can be tested, for example, whether the data writing transistor in the pixel circuit can write data normally, and whether the storage capacitor in the pixel circuit can store voltage normally, etc.

[0052] Furthermore, by setting the first data line 111 to be electrically connected to the first electrode 121 and the second data line 112 to be electrically connected to the second electrode 122, it is possible to detect whether the test transistor 120 can be normally turned on. If the test transistor 120 is controlled to be turned on, and after the test voltage is transmitted to the first data line 111, the test voltage is not detected on the second data line 112, it can be determined that the test transistor 120 may be faulty. In this way, the array substrate provided in this embodiment has more testable items, so that before the display panel formed by the array substrate is tested for lighting, the test transistor can be tested, and when a problem occurs in the lighting test, the source can be better traced. Therefore, the display panel made of the array substrate of this embodiment can be better tested.

[0053] When sending the test voltage to the first data line 111, an external device may be used to contact the first data line 111, and the test voltage may be directly sent to the first data line 111. A test pad may also be provided on the array substrate, the first data line 111 is connected to the test pad, and an external device is used to send the test voltage to the test pad, thereby sending the test voltage to the first data line 111. After the test is completed, the test pad may be removed or not, which is not limited in this embodiment.

[0054] The technical solution of this embodiment is to set the data line to include a first data line and a second data line, the first data line is electrically connected to the first electrode, and the second data line is electrically connected to the second electrode. While testing the devices in the pixel circuit of the array substrate, it is possible to detect whether the test transistor has a fault. In this way, the array substrate provided by this embodiment has more testable items, so before the display panel formed by the array substrate is tested for lighting, the array substrate provided by this embodiment can be used to test the test transistor, and when a problem occurs in the lighting test, it can be better traced. Therefore, the display panel made of the array substrate of this embodiment can be better tested.

[0055] Based on the above technical solutions, Figure 2 yes Figure 1 A cross-sectional view along the direction a1-a2, optionally, referring to Figure 2 , the test transistor 120 includes an active layer 123;

[0056] The first electrode 121 is connected to the active layer 123 , and the second electrode 122 is connected to the active layer 123 .

[0057] For example, if the first electrode 121 is a source electrode, the first electrode 121 is connected to the source region of the active layer 123, and the second electrode 122 is a drain electrode, and the second electrode 122 is connected to the drain region of the active layer 123. Alternatively, if the first electrode 121 is a drain electrode, the first electrode 121 is connected to the drain region of the active layer 123, and the second electrode 122 is a source electrode, and the second electrode 122 is connected to the source region of the active layer 123.

[0058] Specifically, by setting the first electrode 121 to be connected to the active layer 123, and the second electrode 122 to be connected to the active layer 123, when the test transistor 120 is turned on, the first electrode 121 and the second electrode 122 are connected through the active layer 123, and the test voltage on the first data line 111 can be transmitted to the second data line 112 through the first electrode 121, the active layer 123 and the second electrode 122. In this way, by detecting the voltage on the second data line 112, it can be determined whether the test transistor 120 is faulty, so that the array substrate of this embodiment can be used to test the test transistor 120.

[0059] Alternatively, if Figure 2 As shown, the first data line 111 is electrically connected to the first electrode 121 through a via hole, and the second data line 112 is electrically connected to the second electrode 122 through a via hole.

[0060] On the basis of the above technical solutions, Figure 3 is a schematic diagram of the structure of another array substrate provided by an embodiment of the utility model. Figure 3 The array substrate further includes a control signal line 130 , which is connected to the test transistor 120 , and the control signal line 130 is configured to control the on or off of the test transistor 120 according to a control signal on the control signal line 130 .

[0061] Specifically, the control signal line 130 can transmit a control signal, and the control signal can, for example, alternately output a valid level and an invalid level, for example, the valid level is a high level, and the invalid level is a low level; or the valid level is a low level, and the invalid level is a high level, which is not limited here. When the control signal transmitted on the control signal line 130 is a valid level, the test transistor 120 is turned on, and when the control signal transmitted on the control signal line 130 is an invalid level, the test transistor 120 is turned off. Therefore, when testing the device and the test transistor of the pixel circuit, the valid level can be transmitted to the test transistor 120 through the control signal line 130, so that the test transistor 120 is turned on, so that the array substrate of this embodiment can test the test transistor 120.

[0062] Based on the above technical solutions, Figure 4 yes Figure 3 A cross-sectional view along the direction a3-a4, optionally, with reference to Figure 4 and Figure 3 , the test transistor 120 further includes a third electrode 124 ; the control signal line 130 is electrically connected to the third electrode 124 .

[0063] Specifically, the third electrode 124 is a control electrode of the test transistor 120, for example, a gate. Figure 3 The array substrate further includes a first connection portion 131, and the first connection portion 131 is connected between the control signal line 130 and the third electrode 124. The first connection portion 131 is a metal connection line, which can connect the control signal line 130 and the third electrode 124. For example, the first connection portion 131 and the control signal line 130 are arranged on the same layer.

[0064] like Figure 3 and Figure 4 As shown, the control signal line 130 is electrically connected to the third electrode 124 through the first connection portion 131. Figure 4 As shown, the first connection portion 131 is electrically connected to the third electrode 124 through a via hole. In this way, the control signal on the control signal line 130 is easily transmitted to the third electrode 124, so that the test transistor 120 is turned on in response to the effective level on the control signal line 130 and turned off in response to the invalid level on the control signal line 130.

[0065] Optionally, refer to Figure 3 , the extension direction of the control signal line 130 intersects with the extension direction of the data line 110.

[0066] Exemplarily, the data lines 110 (the first data lines 111 and the second data lines 112) extend along the first direction Y. The control signal lines 130 extend along the second direction X, and the second direction X intersects the first direction Y. In this way, one control signal line 130 can be connected to a plurality of test transistors 120, so as to transmit the control signal to the plurality of test transistors 120, which can reduce the number of control signal lines 130, thereby reducing the occupied space and facilitating the realization of a narrow frame.

[0067] Optionally, refer to Figure 4 , the array substrate further includes: a substrate 100; a first electrode 121 and a second electrode 122 located on one side of the substrate 100;

[0068] The data line 110 is located at a side of the first electrode 121 away from the substrate 100 , and the control signal line 130 is located at a side of the data line 110 away from the substrate 100 .

[0069] Specifically, the data line 110 is located on the side of the first electrode 121 away from the substrate 100, that is, the first data line 111 and the second data line 112 are located on the side of the first electrode 121 away from the substrate 100. The control signal line 130 is disposed on the same layer as the first connection portion 131. Figure 4 The position of the first connection part 131 is shown in FIG. 1 , which shows that the first connection part 131 is located on the side of the data line 110 away from the substrate 100, and the control signal line 130 is located on the side of the data line 110 away from the substrate 100. By arranging the control signal line 130 on the side of the data line 110 away from the substrate 100, the control signal line 130 and the data line 110 are arranged in different layers, that is, the control signal line 130 and the second data line 112 are arranged in different layers, and the second data line 112 is prevented from crossing the control signal line 130, thereby ensuring the reliability and accuracy of signal transmission.

[0070] On the basis of the above technical solutions, Figure 5 is a schematic diagram of the structure of another array substrate provided by an embodiment of the utility model. Figure 5 The array substrate further includes: at least one voltage line 140 , the voltage line 140 is electrically connected to the first electrode 121 of the test transistor 120 ; an extension direction of the voltage line 140 intersects with an extension direction of the data line 110 .

[0071] Specifically, the voltage line 140 can transmit a test data voltage. When the test transistor 120 is turned on in response to the effective level of the control signal, the test data voltage on the voltage line 140 can be transmitted to the second data line 112 through the first electrode 121 and the second electrode 122, and the second data line 112 can transmit the test data voltage to the pixel circuit.

[0072] The display panel formed by the array substrate includes light-emitting elements of at least one color. Different voltage lines 140 can transmit test data voltages for pixel circuits connected to light-emitting elements of different colors. For example, the array substrate is provided with two voltage lines 140, one voltage line 140 transmits a test data voltage for a pixel circuit connected to a red light-emitting element, and the other voltage line 140 transmits a test data voltage for a pixel circuit connected to a green light-emitting element, thereby satisfying the conduction conditions of light-emitting elements of different colors and detecting light-emitting elements of different colors.

[0073] Alternatively, if Figure 5 As shown, the array substrate further includes a second connection portion 141, and the second connection portion 141 is connected between the voltage line 140 and the first electrode 121. Thus, the voltage line 140 is connected to the first electrode 121. For example, the voltage line 140 and the second connection portion 141 are arranged in the same layer.

[0074] Figure 6 yes Figure 5 Cross-sectional view along the a5-a6 direction, refer to Figure 6The voltage line 140 is located on the side of the data line 110 away from the substrate 100. That is, the voltage line 140 is located on the side of the first data line 111 away from the substrate 100, so that the voltage line 140 does not affect the routing of the first data line 111, which facilitates routing design.

[0075] Alternatively, if Figure 6 As shown, the second connection portion 141 is electrically connected to the first electrode 121 through a via hole.

[0076] Optionally, the voltage line 140 is arranged in the same layer as the control signal line 130. This arrangement can prevent the voltage line 140 from crossing the first data line 111, and prevent the voltage line 140 from affecting the routing of the first data line 111, thereby ensuring the reliability and stability of signal transmission. In addition, the number of film layers can be reduced, which is conducive to realizing a lightweight design of the display panel.

[0077] Optionally, refer to Figure 5 , the array substrate includes three voltage lines 140 ; ​​the arrangement direction of the three voltage lines 140 is the same as the extension direction of the data line 110 ; different voltage lines 140 are connected to different test transistors 120 .

[0078] The data lines 110 (the first data lines 111 and the second data lines 112 ) extend along a first direction Y, and the three voltage lines 140 are arranged along the first direction Y.

[0079] Exemplarily, the display panel formed by the array substrate may include a red light-emitting element, a green light-emitting element, and a blue light-emitting element. The three voltage lines 140 are respectively the voltage lines corresponding to the red light-emitting element, the voltage lines corresponding to the green light-emitting element, and the voltage lines corresponding to the blue light-emitting element. Then the test data voltages can be provided for the pixel circuits corresponding to the light-emitting elements of different colors, respectively, so as to meet the conduction conditions of the light-emitting elements of different colors, and the light-emitting elements of different colors are detected. For example, if the first voltage line 140 is the voltage line corresponding to the red light-emitting element, the first voltage line 140 is connected to the test transistor 120 corresponding to the pixel circuit connected to the red light-emitting element, so that the test data voltage on the first voltage line 140 can be transmitted to the second data line 112 corresponding to the pixel circuit connected to the red light-emitting element through the corresponding test transistor 120, so that the pixel circuit connected to the red light-emitting element obtains the test data voltage on the first voltage line 140, thereby driving the red light-emitting element to emit light. For example, if the second voltage line 140 is the voltage line corresponding to the green light-emitting element, the second voltage line 140 is connected to the test transistor 120 corresponding to the pixel circuit connected to the green light-emitting element. For example, if the third voltage line 140 is a voltage line corresponding to a blue light-emitting element, the third voltage line 140 is connected to the test transistor 120 corresponding to the pixel circuit connected to the blue light-emitting element. In this way, it is possible to provide a test data voltage to the pixel circuits connected to light-emitting elements of different colors, meet the conduction conditions of light-emitting elements of different colors, and detect light-emitting elements of different colors.

[0080] Optionally, refer to Figure 5 , the array substrate further includes a pixel circuit 150, which is located in the display area AA; the second data line 112 is connected to the pixel circuit 150. In this way, when testing the device in the pixel circuit of the array substrate, the test transistor 120 is turned on and sends a test voltage to the first data line 111, the first data line 111 can transmit the test voltage to the first electrode 121, the first electrode 121 transmits the test voltage to the second electrode 122, the second electrode 122 transmits the test voltage to the second data line 112, and the second data line 112 transmits the test voltage to the pixel circuit 150, so that the device in the pixel circuit 150 can be tested.

[0081] Figure 7 is a schematic diagram of a pixel circuit provided by an embodiment of the utility model. Figure 7 , the pixel circuit 150 includes a data writing transistor T1, a driving transistor T2 and a storage capacitor C1;

[0082] A first electrode of the data writing transistor T1 is electrically connected to the second data line 112, and a second electrode of the data writing transistor T1 is connected to the driving transistor T2;

[0083] A first electrode of the driving transistor T2 is connected to a first power source VDD;

[0084] A first electrode of the storage capacitor C1 is connected to a first power source VDD, and a second electrode of the storage capacitor C1 is connected to a control electrode of the data writing transistor T1.

[0085] Exemplarily, the control electrode of the data writing transistor T1 is connected to the scanning line Scan. When the scanning signal on the scanning line Scan is at a valid level, the data writing transistor T1 is turned on, and the data writing transistor T1 transmits the test voltage to the control electrode of the driving transistor T2, that is, writes the second electrode of the storage capacitor C1. By detecting the voltage of the second electrode of the storage capacitor C1, it can be determined whether the data writing transistor T1 is faulty, and it can also be determined whether the storage capacitor C1 is faulty, so as to detect the device in the pixel circuit 150. Among them, the data writing transistor T1 can be electrically connected to the first electrode of the driving transistor T2, and it can also be electrically connected to the control electrode of the driving transistor T2. Figure 7 The data writing transistor T1 is shown to be electrically connected to the first electrode of the driving transistor T2, but this is not limited. In some other implementations, the pixel circuit 150 may also include other transistors, such as an initialization transistor, a threshold compensation transistor, and a light emission control transistor, which are not limited in this embodiment.

[0086] The second electrode of the driving transistor T2 may be electrically connected to the first electrode of the light emitting element 160 in the display panel, and the second electrode of the light emitting element 160 is connected to the second power source VSS.

[0087] It should be noted that the transistors in the pixel circuit 150 may be P-type transistors; may be N-type transistors; may be partially N-type transistors and partially P-type transistors. Figure 7 2 shows a case where all transistors in the pixel circuit 150 are P-type transistors, but this is not limiting.

[0088] It should also be noted that, in this embodiment, the first power supply voltage provided by the first power supply VDD may be a positive voltage, and the second power supply voltage provided by the second power supply VSS may be a zero or negative voltage, which is not limited in this embodiment.

[0089] The embodiment of the utility model further provides a display panel, Figure 8 is a schematic diagram of the structure of a display panel provided by an embodiment of the utility model, referring to Figure 8, the display panel 20 includes the array substrate 21 provided by any embodiment of the present invention. The display panel 20 includes the array substrate 21 provided by any embodiment of the present invention, and thus has the same beneficial effects as the array substrate provided by any embodiment of the present invention, which will not be described in detail here. The display panel can be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, etc.

[0090] The above specific implementations do not constitute a limitation on the protection scope of the present utility model. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present utility model shall be included in the protection scope of the present utility model.

Claims

1. An array substrate, characterized in that: include: Data lines, the data lines comprising a first data line and a second data line; A test transistor, the test transistor comprising a first electrode and a second electrode; the first data line is electrically connected to the first electrode, the second data line is electrically connected to the second electrode, and the second data line extends from the non-display area of ​​the array substrate to the display area of ​​the array substrate; the first data line is configured to transmit a test voltage to the first electrode, the test transistor is configured to transmit the test voltage from the first electrode to the second data line when turned on, and the second data line is configured to transmit the test voltage to the display area.

2. The array substrate according to claim 1, characterized in that: The test transistor includes an active layer; The first electrode is connected to the active layer, and the second electrode is connected to the active layer.

3. The array substrate according to claim 1, characterized in that: Also includes: A control signal line is connected to the test transistor, and the control signal line is configured to control the on or off of the test transistor according to a control signal on the control signal line.

4. The array substrate according to claim 3, characterized in that: The test transistor further includes a third electrode; the control signal line is electrically connected to the third electrode; An extending direction of the control signal line intersects with an extending direction of the data line.

5. The array substrate according to claim 4, characterized in that: Also includes: A first connection portion is connected between the control signal line and the third electrode.

6. The array substrate according to claim 4, characterized in that: Also includes: substrate; The first electrode and the second electrode are located on one side of the substrate; The data line is located at a side of the first electrode away from the substrate, and the control signal line is located at a side of the data line away from the substrate.

7. The array substrate according to claim 1, characterized in that: The array substrate further includes: a substrate; the first electrode and the second electrode are located on one side of the substrate, and the data line is located on a side of the first electrode away from the substrate; At least one voltage line, the voltage line is electrically connected to the first electrode of the test transistor; the extension direction of the voltage line intersects with the extension direction of the data line; the voltage line is located on a side of the data line away from the substrate.

8. The array substrate according to claim 1, characterized in that: The array substrate further comprises a pixel circuit, and the pixel circuit is located in the display area; The second data line is connected to the pixel circuit.

9. The array substrate according to claim 8, characterized in that: The pixel circuit includes a data writing transistor, a driving transistor and a storage capacitor; A first electrode of the data writing transistor is electrically connected to the second data line, and a second electrode of the data writing transistor is connected to the driving transistor; The first electrode of the driving transistor is connected to a first power supply; A first electrode of the storage capacitor is connected to the first power source, and a second electrode of the storage capacitor is connected to a control electrode of the data writing transistor.

10. A display panel, characterized in that: The invention comprises the array substrate according to any one of claims 1 to 9.

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