Circuit structure for peak current protection detection

Abstract

The utility model relates to a circuit structure for peak current protection detection, which is characterized in that a dual-comparator amplifier chip is selected, an OCPALR is in high level in a normal state, an IPOS is a current sensor positive current output interface network point and is connected to a pin 2 of U1A after low-pass filtering, a pin 3 of U1A is an overcurrent protection threshold point of forward peak current, and when the voltage of the pin 2 of U1A is greater than that of the pin 3 of U1A, the OCPALR is in high level in a normal state and is connected to a pin 2 of U1A after low-pass filtering. The voltage OCPALR of the pin 1 of the U1A is pulled to a low level; the IPOS is a negative current output interface network point of the current sensor and is connected to a pin 6 of the U1B after low-pass filtering, a pin 5 of the U1B is an overcurrent protection threshold point of reverse peak current, when the voltage of the pin 6 of the U1B is larger than that of the pin 5 of the U1B, the voltage of a pin 7 of the U1B can be pulled to be low level, the OCPALR is pulled to be low level through an R8 and an R6, and a triode Q1 is in an amplification state. Positive and negative peak currents are detected in real time, a protection signal is normalized to the OCPALR, and the circuit has the advantages of being clear in circuit logic, stable, reliable, rapid and real-time in monitoring and the like.

Description

Technical Field

[0001] The utility model relates to a circuit structure used for peak current protection detection. Background Art

[0002] With the development of power electronics technology, switching power supply technology is constantly innovating, new power devices and new circuit topologies are constantly updated, and the operating frequency of power switch tubes is becoming higher and higher, especially in low-voltage and high-current electroplating, electrolysis, metal smelting and other industrial energy sources. The power switch tube has large current and high voltage, and a single power tube is expensive. In many circuit topologies, the power switch tube will work in the positive and negative half-cycles, and there will be positive and negative current values. Overcurrent and short circuit are common causes of power tube damage. The conventional protection circuit uses a current transformer to take samples and then monitor the power tube current after full-bridge rectification. However, it has defects such as transformer saturation, waveform distortion after full-wave rectification, and misjudgment of power tube overcurrent and short-circuit protection, resulting in frequent no output of the entire power supply. Therefore, it is very necessary to design a circuit that can quickly, reliably and monitor the peak current in real time. Utility Model Content

[0003] In view of the above situation, it is necessary to provide a circuit that solves at least one of the above problems.

[0004] A circuit structure for peak current protection detection includes a first network point I_POS, a second network point I_NEG, a third network point RST_OCP and a fourth network point OCP_OFF_PWM;

[0005] Also includes a first comparator U1A, a second comparator U1B and a third comparator U2;

[0006] The first network point I_POS and the second network point I_NEG are respectively a positive current output interface network point and a negative current output interface network point of the current sensor;

[0007] The third network point RST_OCP and the fourth network point OCP_OFF_PWM are respectively the output interface and the input interface of the PWM master control chip;

[0008] The first network point I_POS is connected to pin 2 of the first comparator U1A, the second network point I_NEG is connected to pin 5 of the second comparator U1B, and pin 1 of the first comparator U1A and pin 7 of the second comparator U1B are commonly connected to a fifth network point OCP_ALR;

[0009] The fifth network point OCP_ALR is connected to the 2nd pin of the third comparator U2, the third network point RST_OCP is connected to the 3rd pin of the third comparator U2, and the fourth network point OCP_OFF_PWM is connected to the 1st pin of the third comparator U2;

[0010] Pin 3 of the first comparator U1A, pin 5 of the second comparator U1B, and pin 3 of the third comparator U2 are comparison value threshold points.

[0011] As a further solution of the utility model: low-pass filters are provided between the first network point I_POS and pin 2 of the first comparator U1A, between the second network point I_NEG and pin 5 of the second comparator U1B, and between the fifth network point OCP_ALR and pin 2 of the third comparator U2.

[0012] As a further solution of the utility model: Pin 7 of the second comparator U1B is connected in series with Pin 2 of the transistor Q1, Pin 1 of the transistor Q1 is grounded, and Pin 2 is connected to Pin 1 of the first comparator U1A;

[0013] The resistor R8 is connected to the 7th pin of the second comparator U1B and the fifth network point OCP_ALR respectively;

[0014] The resistor R6 is connected in parallel between the pin 1 and the pin 3 of the transistor Q1 .

[0015] As a further solution of the utility model: a transistor Q2 is arranged between the third network point RST_OCP and the 3rd pin of the third comparator U2, and the 2nd pin of the transistor Q2 is connected to the third network point RST_OCP;

[0016] Pin 3 of the transistor Q2 is connected to pin 3 of the third comparator U2;

[0017] Pin 1 of the transistor Q2 is grounded.

[0018] As a further solution of the utility model: a transistor D1 and a resistor R18 are connected in series between the fourth network point OCP_OFF_PWM and the 3rd pin of the third comparator U2;

[0019] Pins 1 and 2 of the transistor D1 are connected to the fourth network point OCP_OFF_PWM;

[0020] Pin 3 of the transistor D1 is connected to the resistor R18;

[0021] The node between the resistor R18 and the pin 3 of the third comparator U2 is grounded through the resistor R17.

[0022] The above circuit structure uses a dual comparator amplifier chip. OCP_ALR is a high-level voltage under normal conditions. I_POS is the positive current output interface network point of the current sensor. It is connected to the 2nd pin of U1A after low-pass filtering by R1 and C1. The 3rd pin of U1A is the overcurrent protection threshold point of the forward peak current. When the voltage of the 2nd pin of U1A is greater than the voltage of the 3rd pin of U1A, the voltage OCP_ALR of the 1st pin of U1A will be pulled to a low level. I_NEG is the negative current output interface network point of the current sensor. It is connected to the 6th pin of U1B after low-pass filtering by R12 and C3. The 5th pin of U1B It is the overcurrent protection threshold point of the reverse peak current. When the voltage of pin 6 of U1B is greater than the voltage of pin 5 of U1B, the voltage of pin 7 of U1B will be pulled to a low level, and OCP_ALR will be pulled to a low level through R8 and R6, and the Q1 transistor is in an amplified state. The present invention cleverly uses the principle of dual comparator circuits, sets I_POS and I_NEG peak current protection threshold points through peripheral voltage divider circuits, detects positive and negative peak currents in real time, and normalizes the protection signal to the same network point OCP_ALR, which has the advantages of clear circuit logic, stable and reliable, and fast real-time monitoring. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 It is a circuit principle diagram of an embodiment of the utility model. DETAILED DESCRIPTION

[0024] In order to make the purpose, technical solution and advantages of the utility model more clear, the utility model is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described here are only used to explain the utility model and are not used to limit the utility model.

[0025] In the description of the present invention, unless otherwise specified, "multiple" means two or more; the terms "center", "longitudinal", "lateral", "up", "down", "left", "right", "inside", "outside", "front end", "rear end", "head", "tail", "vertical", "horizontal", "top", "bottom", "inside", "outside" and the like indicate positions or positional relationships based on the positions or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation, and therefore cannot be understood as limiting the present invention. In addition, the terms "first", "second", "third", etc. are only used for descriptive purposes and cannot be understood as indicating or implying relative importance.

[0026] In the description of the present invention, it should be noted that, unless otherwise clearly specified and limited, the terms "installation", "connection" and "connection" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be an indirect connection through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood by specific circumstances.

[0027] like Figure 1 As shown, the utility model provides a circuit structure for peak current protection detection, including a first network point I_POS, a second network point I_NEG, a third network point RST_OCP and a fourth network point OCP_OFF_PWM;

[0028] Also includes a first comparator U1A, a second comparator U1B and a third comparator U2;

[0029] The first network point I_POS and the second network point I_NEG are respectively a positive current output interface network point and a negative current output interface network point of the current sensor;

[0030] The third network point RST_OCP and the fourth network point OCP_OFF_PWM are respectively the output interface and the input interface of the PWM master control chip;

[0031] The first network point I_POS is connected to pin 2 of the first comparator U1A, the second network point I_NEG is connected to pin 5 of the second comparator U1B, and pin 1 of the first comparator U1A and pin 7 of the second comparator U1B are commonly connected to a fifth network point OCP_ALR;

[0032] The fifth network point OCP_ALR is connected to the 2nd pin of the third comparator U2, the third network point RST_OCP is connected to the 3rd pin of the third comparator U2, and the fourth network point OCP_OFF_PWM is connected to the 1st pin of the third comparator U2;

[0033] Pin 3 of the first comparator U1A, pin 5 of the second comparator U1B, and pin 3 of the third comparator U2 are comparison value threshold points.

[0034] As a further solution of the utility model: low-pass filters are provided between the first network point I_POS and pin 2 of the first comparator U1A, between the second network point I_NEG and pin 5 of the second comparator U1B, and between the fifth network point OCP_ALR and pin 2 of the third comparator U2.

[0035] As a further solution of the utility model: Pin 7 of the second comparator U1B is connected in series with Pin 2 of the transistor Q1, Pin 1 of the transistor Q1 is grounded, and Pin 2 is connected to Pin 1 of the first comparator U1A;

[0036] The resistor R8 is connected to the 7th pin of the second comparator U1B and the fifth network point OCP_ALR respectively;

[0037] The resistor R6 is connected in parallel between the pin 1 and the pin 3 of the transistor Q1 .

[0038] As a further solution of the utility model: a transistor Q2 is arranged between the third network point RST_OCP and the 3rd pin of the third comparator U2, and the 2nd pin of the transistor Q2 is connected to the third network point RST_OCP;

[0039] Pin 3 of the transistor Q2 is connected to pin 3 of the third comparator U2;

[0040] Pin 1 of the transistor Q2 is grounded.

[0041] As a further solution of the utility model: a transistor D1 and a resistor R18 are connected in series between the fourth network point OCP_OFF_PWM and the 3rd pin of the third comparator U2;

[0042] Pins 1 and 2 of the transistor D1 are connected to the fourth network point OCP_OFF_PWM;

[0043] Pin 3 of the transistor D1 is connected to the resistor R18;

[0044] The node between the resistor R18 and the pin 3 of the third comparator U2 is grounded through the resistor R17.

[0045] The above description is only a preferred embodiment of the present invention and does not constitute any form of limitation to the present invention. Although the present invention has been disclosed as a preferred embodiment as above, it is not intended to limit the present invention. Any technician familiar with the profession can make some changes or modify the technical contents disclosed above into equivalent embodiments without departing from the scope of the technical solution of the present invention. However, any simple modification, equivalent change and modification made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention still fall within the scope of the technical solution of the present invention.

Claims

1. A circuit structure for peak current protection detection, characterized in that: It includes a first network point I_POS, a second network point I_NEG, a third network point RST_OCP and a fourth network point OCP_OFF_PWM; Also includes a first comparator U1A, a second comparator U1B and a third comparator U2; The first network point I_POS and the second network point I_NEG are respectively a positive current output interface network point and a negative current output interface network point of the current sensor; The third network point RST_OCP and the fourth network point OCP_OFF_PWM are respectively the output interface and the input interface of the PWM master control chip; The first network point I_POS is connected to pin 2 of the first comparator U1A, the second network point I_NEG is connected to pin 5 of the second comparator U1B, and pin 1 of the first comparator U1A and pin 7 of the second comparator U1B are commonly connected to a fifth network point OCP_ALR; The fifth network point OCP_ALR is connected to the 2nd pin of the third comparator U2, the third network point RST_OCP is connected to the 3rd pin of the third comparator U2, and the fourth network point OCP_OFF_PWM is connected to the 1st pin of the third comparator U2; Pin 3 of the first comparator U1A, pin 5 of the second comparator U1B, and pin 3 of the third comparator U2 are comparison value threshold points.

2. The circuit structure according to claim 1, characterized in that: Low-pass filters are provided between the first network point I_POS and the 2nd pin of the first comparator U1A, between the second network point I_NEG and the 5th pin of the second comparator U1B, and between the fifth network point OCP_ALR and the 2nd pin of the third comparator U2.

3. The circuit structure according to claim 1, characterized in that: Pin 7 of the second comparator U1B is connected in series to pin 2 of the transistor Q1, pin 1 of the transistor Q1 is grounded, and pin 2 is connected to pin 1 of the first comparator U1A; The resistor R8 is connected to the 7th pin of the second comparator U1B and the fifth network point OCP_ALR respectively; The resistor R6 is connected in parallel between the pin 1 and the pin 3 of the transistor Q1 .

4. The circuit structure according to claim 1, characterized in that: A transistor Q2 is arranged between the third network point RST_OCP and the 3rd pin of the third comparator U2, and the 2nd pin of the transistor Q2 is connected to the third network point RST_OCP; Pin 3 of the transistor Q2 is connected to pin 3 of the third comparator U2; Pin 1 of the transistor Q2 is grounded.

5. The circuit structure according to claim 1, characterized in that: A transistor D1 and a resistor R18 are connected in series between the fourth network point OCP_OFF_PWM and the 3rd pin of the third comparator U2; Pins 1 and 2 of the transistor D1 are connected to the fourth network point OCP_OFF_PWM; Pin 3 of the transistor D1 is connected to the resistor R18; The node between the resistor R18 and the pin 3 of the third comparator U2 is grounded through the resistor R17.

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